1/* 2 * Copyright (C) 2016 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* 18 Art assembly interpreter notes: 19 20 First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't 21 handle invoke, allows higher-level code to create frame & shadow frame. 22 23 Once that's working, support direct entry code & eliminate shadow frame (and 24 excess locals allocation. 25 26 Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the 27 base of the vreg array within the shadow frame. Access the other fields, 28 dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue 29 the shadow frame mechanism of double-storing object references - via rFP & 30 number_of_vregs_. 31 32 */ 33 34/* 35x86_64 ABI general notes: 36 37Caller save set: 38 rax, rdx, rcx, rsi, rdi, r8-r11, st(0)-st(7) 39Callee save set: 40 rbx, rbp, r12-r15 41Return regs: 42 32-bit in eax 43 64-bit in rax 44 fp on xmm0 45 46First 8 fp parameters came in xmm0-xmm7. 47First 6 non-fp parameters came in rdi, rsi, rdx, rcx, r8, r9. 48Other parameters passed on stack, pushed right-to-left. On entry to target, first 49param is at 8(%esp). Traditional entry code is: 50 51Stack must be 16-byte aligned to support SSE in native code. 52 53If we're not doing variable stack allocation (alloca), the frame pointer can be 54eliminated and all arg references adjusted to be esp relative. 55*/ 56 57/* 58Mterp and x86_64 notes: 59 60Some key interpreter variables will be assigned to registers. 61 62 nick reg purpose 63 rPROFILE rbp countdown register for jit profiling 64 rPC r12 interpreted program counter, used for fetching instructions 65 rFP r13 interpreted frame pointer, used for accessing locals and args 66 rINSTw bx first 16-bit code of current instruction 67 rINSTbl bl opcode portion of instruction word 68 rINSTbh bh high byte of inst word, usually contains src/tgt reg names 69 rIBASE r14 base of instruction handler table 70 rREFS r15 base of object references in shadow frame. 71 72Notes: 73 o High order 16 bits of ebx must be zero on entry to handler 74 o rPC, rFP, rINSTw/rINSTbl valid on handler entry and exit 75 o eax and ecx are scratch, rINSTw/ebx sometimes scratch 76 77Macros are provided for common operations. Each macro MUST emit only 78one instruction to make instruction-counting easier. They MUST NOT alter 79unspecified registers or condition codes. 80*/ 81 82/* 83 * This is a #include, not a %include, because we want the C pre-processor 84 * to expand the macros into assembler assignment statements. 85 */ 86#include "asm_support.h" 87#include "interpreter/cfi_asm_support.h" 88 89/* 90 * Handle mac compiler specific 91 */ 92#if defined(__APPLE__) 93 #define MACRO_LITERAL(value) $$(value) 94 #define FUNCTION_TYPE(name) 95 #define SIZE(start,end) 96 // Mac OS' symbols have an _ prefix. 97 #define SYMBOL(name) _ ## name 98#else 99 #define MACRO_LITERAL(value) $$value 100 #define FUNCTION_TYPE(name) .type name, @function 101 #define SIZE(start,end) .size start, .-end 102 #define SYMBOL(name) name 103#endif 104 105.macro PUSH _reg 106 pushq \_reg 107 .cfi_adjust_cfa_offset 8 108 .cfi_rel_offset \_reg, 0 109.endm 110 111.macro POP _reg 112 popq \_reg 113 .cfi_adjust_cfa_offset -8 114 .cfi_restore \_reg 115.endm 116 117/* 118 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, 119 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 120 */ 121#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 122#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 123#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 124#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 125#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 126#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 127#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 128#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) 129#define OFF_FP_COUNTDOWN_OFFSET OFF_FP(SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET) 130#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET) 131 132/* Frame size must be 16-byte aligned. 133 * Remember about 8 bytes for return address + 6 * 8 for spills. 134 */ 135#define FRAME_SIZE 8 136 137/* Frame diagram while executing ExecuteMterpImpl, high to low addresses */ 138#define IN_ARG3 %rcx 139#define IN_ARG2 %rdx 140#define IN_ARG1 %rsi 141#define IN_ARG0 %rdi 142/* Spill offsets relative to %esp */ 143#define SELF_SPILL (FRAME_SIZE - 8) 144/* Out Args */ 145#define OUT_ARG3 %rcx 146#define OUT_ARG2 %rdx 147#define OUT_ARG1 %rsi 148#define OUT_ARG0 %rdi 149#define OUT_32_ARG3 %ecx 150#define OUT_32_ARG2 %edx 151#define OUT_32_ARG1 %esi 152#define OUT_32_ARG0 %edi 153#define OUT_FP_ARG1 %xmm1 154#define OUT_FP_ARG0 %xmm0 155 156/* During bringup, we'll use the shadow frame model instead of rFP */ 157/* single-purpose registers, given names for clarity */ 158#define rSELF SELF_SPILL(%rsp) 159#define rPC %r12 160#define CFI_DEX 12 // DWARF register number of the register holding dex-pc (rPC). 161#define CFI_TMP 5 // DWARF register number of the first argument register (rdi). 162#define rFP %r13 163#define rINST %ebx 164#define rINSTq %rbx 165#define rINSTw %bx 166#define rINSTbh %bh 167#define rINSTbl %bl 168#define rIBASE %r14 169#define rREFS %r15 170#define rPROFILE %ebp 171 172#define MTERP_LOGGING 0 173 174/* 175 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 176 * be done *before* something throws. 177 * 178 * It's okay to do this more than once. 179 * 180 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 181 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 182 * offset into the code_items_[] array. For effiency, we will "export" the 183 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 184 * to convert to a dex pc when needed. 185 */ 186.macro EXPORT_PC 187 movq rPC, OFF_FP_DEX_PC_PTR(rFP) 188.endm 189 190/* 191 * Refresh handler table. 192 * IBase handles uses the caller save register so we must restore it after each call. 193 * Also it is used as a result of some 64-bit operations (like imul) and we should 194 * restore it in such cases also. 195 * 196 */ 197.macro REFRESH_IBASE_REG self_reg 198 movq THREAD_CURRENT_IBASE_OFFSET(\self_reg), rIBASE 199.endm 200.macro REFRESH_IBASE 201 movq rSELF, rIBASE 202 REFRESH_IBASE_REG rIBASE 203.endm 204 205/* 206 * Refresh rINST. 207 * At enter to handler rINST does not contain the opcode number. 208 * However some utilities require the full value, so this macro 209 * restores the opcode number. 210 */ 211.macro REFRESH_INST _opnum 212 movb rINSTbl, rINSTbh 213 movb $$\_opnum, rINSTbl 214.endm 215 216/* 217 * Fetch the next instruction from rPC into rINSTw. Does not advance rPC. 218 */ 219.macro FETCH_INST 220 movzwq (rPC), rINSTq 221.endm 222 223/* 224 * Remove opcode from rINST, compute the address of handler and jump to it. 225 */ 226.macro GOTO_NEXT 227 movzx rINSTbl,%eax 228 movzbl rINSTbh,rINST 229 shll MACRO_LITERAL(${handler_size_bits}), %eax 230 addq rIBASE, %rax 231 jmp *%rax 232.endm 233 234/* 235 * Advance rPC by instruction count. 236 */ 237.macro ADVANCE_PC _count 238 leaq 2*\_count(rPC), rPC 239.endm 240 241/* 242 * Advance rPC by instruction count, fetch instruction and jump to handler. 243 */ 244.macro ADVANCE_PC_FETCH_AND_GOTO_NEXT _count 245 ADVANCE_PC \_count 246 FETCH_INST 247 GOTO_NEXT 248.endm 249 250/* 251 * Get/set the 32-bit value from a Dalvik register. 252 */ 253#define VREG_ADDRESS(_vreg) (rFP,_vreg,4) 254#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4) 255 256.macro GET_VREG _reg _vreg 257 movl (rFP,\_vreg,4), \_reg 258.endm 259 260/* Read wide value. */ 261.macro GET_WIDE_VREG _reg _vreg 262 movq (rFP,\_vreg,4), \_reg 263.endm 264 265.macro SET_VREG _reg _vreg 266 movl \_reg, (rFP,\_vreg,4) 267 movl MACRO_LITERAL(0), (rREFS,\_vreg,4) 268.endm 269 270/* Write wide value. reg is clobbered. */ 271.macro SET_WIDE_VREG _reg _vreg 272 movq \_reg, (rFP,\_vreg,4) 273 xorq \_reg, \_reg 274 movq \_reg, (rREFS,\_vreg,4) 275.endm 276 277.macro SET_VREG_OBJECT _reg _vreg 278 movl \_reg, (rFP,\_vreg,4) 279 movl \_reg, (rREFS,\_vreg,4) 280.endm 281 282.macro GET_VREG_HIGH _reg _vreg 283 movl 4(rFP,\_vreg,4), \_reg 284.endm 285 286.macro SET_VREG_HIGH _reg _vreg 287 movl \_reg, 4(rFP,\_vreg,4) 288 movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) 289.endm 290 291.macro CLEAR_REF _vreg 292 movl MACRO_LITERAL(0), (rREFS,\_vreg,4) 293.endm 294 295.macro CLEAR_WIDE_REF _vreg 296 movl MACRO_LITERAL(0), (rREFS,\_vreg,4) 297 movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4) 298.endm 299