1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __ARM_KVM_H__ 20 #define __ARM_KVM_H__ 21 #include <linux/types.h> 22 #include <linux/psci.h> 23 #include <asm/ptrace.h> 24 #define __KVM_HAVE_GUEST_DEBUG 25 #define __KVM_HAVE_IRQ_LINE 26 #define __KVM_HAVE_READONLY_MEM 27 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 28 #define KVM_REG_SIZE(id) (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 29 #define KVM_ARM_SVC_sp svc_regs[0] 30 #define KVM_ARM_SVC_lr svc_regs[1] 31 #define KVM_ARM_SVC_spsr svc_regs[2] 32 #define KVM_ARM_ABT_sp abt_regs[0] 33 #define KVM_ARM_ABT_lr abt_regs[1] 34 #define KVM_ARM_ABT_spsr abt_regs[2] 35 #define KVM_ARM_UND_sp und_regs[0] 36 #define KVM_ARM_UND_lr und_regs[1] 37 #define KVM_ARM_UND_spsr und_regs[2] 38 #define KVM_ARM_IRQ_sp irq_regs[0] 39 #define KVM_ARM_IRQ_lr irq_regs[1] 40 #define KVM_ARM_IRQ_spsr irq_regs[2] 41 #define KVM_ARM_FIQ_r8 fiq_regs[0] 42 #define KVM_ARM_FIQ_r9 fiq_regs[1] 43 #define KVM_ARM_FIQ_r10 fiq_regs[2] 44 #define KVM_ARM_FIQ_fp fiq_regs[3] 45 #define KVM_ARM_FIQ_ip fiq_regs[4] 46 #define KVM_ARM_FIQ_sp fiq_regs[5] 47 #define KVM_ARM_FIQ_lr fiq_regs[6] 48 #define KVM_ARM_FIQ_spsr fiq_regs[7] 49 struct kvm_regs { 50 struct pt_regs usr_regs; 51 unsigned long svc_regs[3]; 52 unsigned long abt_regs[3]; 53 unsigned long und_regs[3]; 54 unsigned long irq_regs[3]; 55 unsigned long fiq_regs[8]; 56 }; 57 #define KVM_ARM_TARGET_CORTEX_A15 0 58 #define KVM_ARM_TARGET_CORTEX_A7 1 59 #define KVM_ARM_NUM_TARGETS 2 60 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 61 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 62 #define KVM_ARM_DEVICE_ID_SHIFT 16 63 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 64 #define KVM_ARM_DEVICE_VGIC_V2 0 65 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 66 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 67 #define KVM_VGIC_V2_DIST_SIZE 0x1000 68 #define KVM_VGIC_V2_CPU_SIZE 0x2000 69 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 70 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 71 #define KVM_VGIC_ITS_ADDR_TYPE 4 72 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 73 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 74 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 75 #define KVM_ARM_VCPU_POWER_OFF 0 76 #define KVM_ARM_VCPU_PSCI_0_2 1 77 struct kvm_vcpu_init { 78 __u32 target; 79 __u32 features[7]; 80 }; 81 struct kvm_sregs { 82 }; 83 struct kvm_fpu { 84 }; 85 struct kvm_guest_debug_arch { 86 }; 87 struct kvm_debug_exit_arch { 88 }; 89 struct kvm_sync_regs { 90 __u64 device_irq_level; 91 }; 92 struct kvm_arch_memory_slot { 93 }; 94 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 95 #define KVM_REG_ARM_COPROC_SHIFT 16 96 #define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007 97 #define KVM_REG_ARM_32_OPC2_SHIFT 0 98 #define KVM_REG_ARM_OPC1_MASK 0x0000000000000078 99 #define KVM_REG_ARM_OPC1_SHIFT 3 100 #define KVM_REG_ARM_CRM_MASK 0x0000000000000780 101 #define KVM_REG_ARM_CRM_SHIFT 7 102 #define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800 103 #define KVM_REG_ARM_32_CRN_SHIFT 11 104 #define ARM_CP15_REG_SHIFT_MASK(x,n) (((x) << KVM_REG_ARM_ ##n ##_SHIFT) & KVM_REG_ARM_ ##n ##_MASK) 105 #define __ARM_CP15_REG(op1,crn,crm,op2) (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | ARM_CP15_REG_SHIFT_MASK(crm, CRM) | ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2)) 106 #define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32) 107 #define __ARM_CP15_REG64(op1,crm) (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64) 108 #define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__) 109 #define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1) 110 #define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14) 111 #define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14) 112 #define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1) 113 #define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14) 114 #define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14) 115 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 116 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4) 117 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 118 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 119 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 120 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 121 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 122 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 123 #define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT) 124 #define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF 125 #define KVM_REG_ARM_VFP_BASE_REG 0x0 126 #define KVM_REG_ARM_VFP_FPSID 0x1000 127 #define KVM_REG_ARM_VFP_FPSCR 0x1001 128 #define KVM_REG_ARM_VFP_MVFR1 0x1006 129 #define KVM_REG_ARM_VFP_MVFR0 0x1007 130 #define KVM_REG_ARM_VFP_FPEXC 0x1008 131 #define KVM_REG_ARM_VFP_FPINST 0x1009 132 #define KVM_REG_ARM_VFP_FPINST2 0x100A 133 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 134 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 135 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 136 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 137 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 138 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 139 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 140 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 141 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 142 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 143 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 144 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 145 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 146 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 147 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 148 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 149 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 150 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 151 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 152 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 153 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 154 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 155 #define KVM_ARM_VCPU_PMU_V3_INIT 1 156 #define KVM_ARM_VCPU_TIMER_CTRL 1 157 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 158 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 159 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 160 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 161 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 162 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 163 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 164 #define KVM_ARM_IRQ_TYPE_SHIFT 24 165 #define KVM_ARM_IRQ_TYPE_MASK 0xff 166 #define KVM_ARM_IRQ_VCPU_SHIFT 16 167 #define KVM_ARM_IRQ_VCPU_MASK 0xff 168 #define KVM_ARM_IRQ_NUM_SHIFT 0 169 #define KVM_ARM_IRQ_NUM_MASK 0xffff 170 #define KVM_ARM_IRQ_TYPE_CPU 0 171 #define KVM_ARM_IRQ_TYPE_SPI 1 172 #define KVM_ARM_IRQ_TYPE_PPI 2 173 #define KVM_ARM_IRQ_CPU_IRQ 0 174 #define KVM_ARM_IRQ_CPU_FIQ 1 175 #define KVM_ARM_IRQ_GIC_MAX 127 176 #define KVM_NR_IRQCHIPS 1 177 #define KVM_PSCI_FN_BASE 0x95c1ba5e 178 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 179 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 180 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 181 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 182 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 183 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 184 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 185 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 186 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 187 #endif 188