1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __AMDGPU_DRM_H__ 20 #define __AMDGPU_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 #endif 24 #define DRM_AMDGPU_GEM_CREATE 0x00 25 #define DRM_AMDGPU_GEM_MMAP 0x01 26 #define DRM_AMDGPU_CTX 0x02 27 #define DRM_AMDGPU_BO_LIST 0x03 28 #define DRM_AMDGPU_CS 0x04 29 #define DRM_AMDGPU_INFO 0x05 30 #define DRM_AMDGPU_GEM_METADATA 0x06 31 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 32 #define DRM_AMDGPU_GEM_VA 0x08 33 #define DRM_AMDGPU_WAIT_CS 0x09 34 #define DRM_AMDGPU_GEM_OP 0x10 35 #define DRM_AMDGPU_GEM_USERPTR 0x11 36 #define DRM_AMDGPU_WAIT_FENCES 0x12 37 #define DRM_AMDGPU_VM 0x13 38 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 39 #define DRM_AMDGPU_SCHED 0x15 40 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 41 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 42 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 43 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 44 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 45 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 46 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 47 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 48 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 49 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 50 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 51 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 52 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 53 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 54 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 55 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 56 #define AMDGPU_GEM_DOMAIN_CPU 0x1 57 #define AMDGPU_GEM_DOMAIN_GTT 0x2 58 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 59 #define AMDGPU_GEM_DOMAIN_GDS 0x8 60 #define AMDGPU_GEM_DOMAIN_GWS 0x10 61 #define AMDGPU_GEM_DOMAIN_OA 0x20 62 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 63 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 64 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 65 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 66 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 67 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 68 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 69 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 70 struct drm_amdgpu_gem_create_in { 71 __u64 bo_size; 72 __u64 alignment; 73 __u64 domains; 74 __u64 domain_flags; 75 }; 76 struct drm_amdgpu_gem_create_out { 77 __u32 handle; 78 __u32 _pad; 79 }; 80 union drm_amdgpu_gem_create { 81 struct drm_amdgpu_gem_create_in in; 82 struct drm_amdgpu_gem_create_out out; 83 }; 84 #define AMDGPU_BO_LIST_OP_CREATE 0 85 #define AMDGPU_BO_LIST_OP_DESTROY 1 86 #define AMDGPU_BO_LIST_OP_UPDATE 2 87 struct drm_amdgpu_bo_list_in { 88 __u32 operation; 89 __u32 list_handle; 90 __u32 bo_number; 91 __u32 bo_info_size; 92 __u64 bo_info_ptr; 93 }; 94 struct drm_amdgpu_bo_list_entry { 95 __u32 bo_handle; 96 __u32 bo_priority; 97 }; 98 struct drm_amdgpu_bo_list_out { 99 __u32 list_handle; 100 __u32 _pad; 101 }; 102 union drm_amdgpu_bo_list { 103 struct drm_amdgpu_bo_list_in in; 104 struct drm_amdgpu_bo_list_out out; 105 }; 106 #define AMDGPU_CTX_OP_ALLOC_CTX 1 107 #define AMDGPU_CTX_OP_FREE_CTX 2 108 #define AMDGPU_CTX_OP_QUERY_STATE 3 109 #define AMDGPU_CTX_NO_RESET 0 110 #define AMDGPU_CTX_GUILTY_RESET 1 111 #define AMDGPU_CTX_INNOCENT_RESET 2 112 #define AMDGPU_CTX_UNKNOWN_RESET 3 113 #define AMDGPU_CTX_PRIORITY_UNSET - 2048 114 #define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023 115 #define AMDGPU_CTX_PRIORITY_LOW - 512 116 #define AMDGPU_CTX_PRIORITY_NORMAL 0 117 #define AMDGPU_CTX_PRIORITY_HIGH 512 118 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 119 struct drm_amdgpu_ctx_in { 120 __u32 op; 121 __u32 flags; 122 __u32 ctx_id; 123 __s32 priority; 124 }; 125 union drm_amdgpu_ctx_out { 126 struct { 127 __u32 ctx_id; 128 __u32 _pad; 129 } alloc; 130 struct { 131 __u64 flags; 132 __u32 hangs; 133 __u32 reset_status; 134 } state; 135 }; 136 union drm_amdgpu_ctx { 137 struct drm_amdgpu_ctx_in in; 138 union drm_amdgpu_ctx_out out; 139 }; 140 #define AMDGPU_VM_OP_RESERVE_VMID 1 141 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 142 struct drm_amdgpu_vm_in { 143 __u32 op; 144 __u32 flags; 145 }; 146 struct drm_amdgpu_vm_out { 147 __u64 flags; 148 }; 149 union drm_amdgpu_vm { 150 struct drm_amdgpu_vm_in in; 151 struct drm_amdgpu_vm_out out; 152 }; 153 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 154 struct drm_amdgpu_sched_in { 155 __u32 op; 156 __u32 fd; 157 __s32 priority; 158 __u32 flags; 159 }; 160 union drm_amdgpu_sched { 161 struct drm_amdgpu_sched_in in; 162 }; 163 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 164 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 165 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 166 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 167 struct drm_amdgpu_gem_userptr { 168 __u64 addr; 169 __u64 size; 170 __u32 flags; 171 __u32 handle; 172 }; 173 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 174 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 175 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 176 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 177 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 178 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 179 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 180 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 181 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 182 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 183 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 184 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 185 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 186 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 187 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 188 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 189 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 190 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 191 #define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 192 #define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 193 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 194 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 195 struct drm_amdgpu_gem_metadata { 196 __u32 handle; 197 __u32 op; 198 struct { 199 __u64 flags; 200 __u64 tiling_info; 201 __u32 data_size_bytes; 202 __u32 data[64]; 203 } data; 204 }; 205 struct drm_amdgpu_gem_mmap_in { 206 __u32 handle; 207 __u32 _pad; 208 }; 209 struct drm_amdgpu_gem_mmap_out { 210 __u64 addr_ptr; 211 }; 212 union drm_amdgpu_gem_mmap { 213 struct drm_amdgpu_gem_mmap_in in; 214 struct drm_amdgpu_gem_mmap_out out; 215 }; 216 struct drm_amdgpu_gem_wait_idle_in { 217 __u32 handle; 218 __u32 flags; 219 __u64 timeout; 220 }; 221 struct drm_amdgpu_gem_wait_idle_out { 222 __u32 status; 223 __u32 domain; 224 }; 225 union drm_amdgpu_gem_wait_idle { 226 struct drm_amdgpu_gem_wait_idle_in in; 227 struct drm_amdgpu_gem_wait_idle_out out; 228 }; 229 struct drm_amdgpu_wait_cs_in { 230 __u64 handle; 231 __u64 timeout; 232 __u32 ip_type; 233 __u32 ip_instance; 234 __u32 ring; 235 __u32 ctx_id; 236 }; 237 struct drm_amdgpu_wait_cs_out { 238 __u64 status; 239 }; 240 union drm_amdgpu_wait_cs { 241 struct drm_amdgpu_wait_cs_in in; 242 struct drm_amdgpu_wait_cs_out out; 243 }; 244 struct drm_amdgpu_fence { 245 __u32 ctx_id; 246 __u32 ip_type; 247 __u32 ip_instance; 248 __u32 ring; 249 __u64 seq_no; 250 }; 251 struct drm_amdgpu_wait_fences_in { 252 __u64 fences; 253 __u32 fence_count; 254 __u32 wait_all; 255 __u64 timeout_ns; 256 }; 257 struct drm_amdgpu_wait_fences_out { 258 __u32 status; 259 __u32 first_signaled; 260 }; 261 union drm_amdgpu_wait_fences { 262 struct drm_amdgpu_wait_fences_in in; 263 struct drm_amdgpu_wait_fences_out out; 264 }; 265 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 266 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 267 struct drm_amdgpu_gem_op { 268 __u32 handle; 269 __u32 op; 270 __u64 value; 271 }; 272 #define AMDGPU_VA_OP_MAP 1 273 #define AMDGPU_VA_OP_UNMAP 2 274 #define AMDGPU_VA_OP_CLEAR 3 275 #define AMDGPU_VA_OP_REPLACE 4 276 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 277 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 278 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 279 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 280 #define AMDGPU_VM_PAGE_PRT (1 << 4) 281 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 282 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 283 #define AMDGPU_VM_MTYPE_NC (1 << 5) 284 #define AMDGPU_VM_MTYPE_WC (2 << 5) 285 #define AMDGPU_VM_MTYPE_CC (3 << 5) 286 #define AMDGPU_VM_MTYPE_UC (4 << 5) 287 struct drm_amdgpu_gem_va { 288 __u32 handle; 289 __u32 _pad; 290 __u32 operation; 291 __u32 flags; 292 __u64 va_address; 293 __u64 offset_in_bo; 294 __u64 map_size; 295 }; 296 #define AMDGPU_HW_IP_GFX 0 297 #define AMDGPU_HW_IP_COMPUTE 1 298 #define AMDGPU_HW_IP_DMA 2 299 #define AMDGPU_HW_IP_UVD 3 300 #define AMDGPU_HW_IP_VCE 4 301 #define AMDGPU_HW_IP_UVD_ENC 5 302 #define AMDGPU_HW_IP_VCN_DEC 6 303 #define AMDGPU_HW_IP_VCN_ENC 7 304 #define AMDGPU_HW_IP_NUM 8 305 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 306 #define AMDGPU_CHUNK_ID_IB 0x01 307 #define AMDGPU_CHUNK_ID_FENCE 0x02 308 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 309 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 310 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 311 struct drm_amdgpu_cs_chunk { 312 __u32 chunk_id; 313 __u32 length_dw; 314 __u64 chunk_data; 315 }; 316 struct drm_amdgpu_cs_in { 317 __u32 ctx_id; 318 __u32 bo_list_handle; 319 __u32 num_chunks; 320 __u32 _pad; 321 __u64 chunks; 322 }; 323 struct drm_amdgpu_cs_out { 324 __u64 handle; 325 }; 326 union drm_amdgpu_cs { 327 struct drm_amdgpu_cs_in in; 328 struct drm_amdgpu_cs_out out; 329 }; 330 #define AMDGPU_IB_FLAG_CE (1 << 0) 331 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 332 #define AMDGPU_IB_FLAG_PREEMPT (1 << 2) 333 struct drm_amdgpu_cs_chunk_ib { 334 __u32 _pad; 335 __u32 flags; 336 __u64 va_start; 337 __u32 ib_bytes; 338 __u32 ip_type; 339 __u32 ip_instance; 340 __u32 ring; 341 }; 342 struct drm_amdgpu_cs_chunk_dep { 343 __u32 ip_type; 344 __u32 ip_instance; 345 __u32 ring; 346 __u32 ctx_id; 347 __u64 handle; 348 }; 349 struct drm_amdgpu_cs_chunk_fence { 350 __u32 handle; 351 __u32 offset; 352 }; 353 struct drm_amdgpu_cs_chunk_sem { 354 __u32 handle; 355 }; 356 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 357 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 358 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 359 union drm_amdgpu_fence_to_handle { 360 struct { 361 struct drm_amdgpu_fence fence; 362 __u32 what; 363 __u32 pad; 364 } in; 365 struct { 366 __u32 handle; 367 } out; 368 }; 369 struct drm_amdgpu_cs_chunk_data { 370 union { 371 struct drm_amdgpu_cs_chunk_ib ib_data; 372 struct drm_amdgpu_cs_chunk_fence fence_data; 373 }; 374 }; 375 #define AMDGPU_IDS_FLAGS_FUSION 0x1 376 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 377 #define AMDGPU_INFO_ACCEL_WORKING 0x00 378 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 379 #define AMDGPU_INFO_HW_IP_INFO 0x02 380 #define AMDGPU_INFO_HW_IP_COUNT 0x03 381 #define AMDGPU_INFO_TIMESTAMP 0x05 382 #define AMDGPU_INFO_FW_VERSION 0x0e 383 #define AMDGPU_INFO_FW_VCE 0x1 384 #define AMDGPU_INFO_FW_UVD 0x2 385 #define AMDGPU_INFO_FW_GMC 0x03 386 #define AMDGPU_INFO_FW_GFX_ME 0x04 387 #define AMDGPU_INFO_FW_GFX_PFP 0x05 388 #define AMDGPU_INFO_FW_GFX_CE 0x06 389 #define AMDGPU_INFO_FW_GFX_RLC 0x07 390 #define AMDGPU_INFO_FW_GFX_MEC 0x08 391 #define AMDGPU_INFO_FW_SMC 0x0a 392 #define AMDGPU_INFO_FW_SDMA 0x0b 393 #define AMDGPU_INFO_FW_SOS 0x0c 394 #define AMDGPU_INFO_FW_ASD 0x0d 395 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 396 #define AMDGPU_INFO_VRAM_USAGE 0x10 397 #define AMDGPU_INFO_GTT_USAGE 0x11 398 #define AMDGPU_INFO_GDS_CONFIG 0x13 399 #define AMDGPU_INFO_VRAM_GTT 0x14 400 #define AMDGPU_INFO_READ_MMR_REG 0x15 401 #define AMDGPU_INFO_DEV_INFO 0x16 402 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 403 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 404 #define AMDGPU_INFO_MEMORY 0x19 405 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 406 #define AMDGPU_INFO_VBIOS 0x1B 407 #define AMDGPU_INFO_VBIOS_SIZE 0x1 408 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 409 #define AMDGPU_INFO_NUM_HANDLES 0x1C 410 #define AMDGPU_INFO_SENSOR 0x1D 411 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 412 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 413 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 414 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 415 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 416 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 417 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 418 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 419 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 420 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 421 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 422 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 423 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 424 struct drm_amdgpu_query_fw { 425 __u32 fw_type; 426 __u32 ip_instance; 427 __u32 index; 428 __u32 _pad; 429 }; 430 struct drm_amdgpu_info { 431 __u64 return_pointer; 432 __u32 return_size; 433 __u32 query; 434 union { 435 struct { 436 __u32 id; 437 __u32 _pad; 438 } mode_crtc; 439 struct { 440 __u32 type; 441 __u32 ip_instance; 442 } query_hw_ip; 443 struct { 444 __u32 dword_offset; 445 __u32 count; 446 __u32 instance; 447 __u32 flags; 448 } read_mmr_reg; 449 struct drm_amdgpu_query_fw query_fw; 450 struct { 451 __u32 type; 452 __u32 offset; 453 } vbios_info; 454 struct { 455 __u32 type; 456 } sensor_info; 457 }; 458 }; 459 struct drm_amdgpu_info_gds { 460 __u32 gds_gfx_partition_size; 461 __u32 compute_partition_size; 462 __u32 gds_total_size; 463 __u32 gws_per_gfx_partition; 464 __u32 gws_per_compute_partition; 465 __u32 oa_per_gfx_partition; 466 __u32 oa_per_compute_partition; 467 __u32 _pad; 468 }; 469 struct drm_amdgpu_info_vram_gtt { 470 __u64 vram_size; 471 __u64 vram_cpu_accessible_size; 472 __u64 gtt_size; 473 }; 474 struct drm_amdgpu_heap_info { 475 __u64 total_heap_size; 476 __u64 usable_heap_size; 477 __u64 heap_usage; 478 __u64 max_allocation; 479 }; 480 struct drm_amdgpu_memory_info { 481 struct drm_amdgpu_heap_info vram; 482 struct drm_amdgpu_heap_info cpu_accessible_vram; 483 struct drm_amdgpu_heap_info gtt; 484 }; 485 struct drm_amdgpu_info_firmware { 486 __u32 ver; 487 __u32 feature; 488 }; 489 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 490 #define AMDGPU_VRAM_TYPE_GDDR1 1 491 #define AMDGPU_VRAM_TYPE_DDR2 2 492 #define AMDGPU_VRAM_TYPE_GDDR3 3 493 #define AMDGPU_VRAM_TYPE_GDDR4 4 494 #define AMDGPU_VRAM_TYPE_GDDR5 5 495 #define AMDGPU_VRAM_TYPE_HBM 6 496 #define AMDGPU_VRAM_TYPE_DDR3 7 497 struct drm_amdgpu_info_device { 498 __u32 device_id; 499 __u32 chip_rev; 500 __u32 external_rev; 501 __u32 pci_rev; 502 __u32 family; 503 __u32 num_shader_engines; 504 __u32 num_shader_arrays_per_engine; 505 __u32 gpu_counter_freq; 506 __u64 max_engine_clock; 507 __u64 max_memory_clock; 508 __u32 cu_active_number; 509 __u32 cu_ao_mask; 510 __u32 cu_bitmap[4][4]; 511 __u32 enabled_rb_pipes_mask; 512 __u32 num_rb_pipes; 513 __u32 num_hw_gfx_contexts; 514 __u32 _pad; 515 __u64 ids_flags; 516 __u64 virtual_address_offset; 517 __u64 virtual_address_max; 518 __u32 virtual_address_alignment; 519 __u32 pte_fragment_size; 520 __u32 gart_page_size; 521 __u32 ce_ram_size; 522 __u32 vram_type; 523 __u32 vram_bit_width; 524 __u32 vce_harvest_config; 525 __u32 gc_double_offchip_lds_buf; 526 __u64 prim_buf_gpu_addr; 527 __u64 pos_buf_gpu_addr; 528 __u64 cntl_sb_buf_gpu_addr; 529 __u64 param_buf_gpu_addr; 530 __u32 prim_buf_size; 531 __u32 pos_buf_size; 532 __u32 cntl_sb_buf_size; 533 __u32 param_buf_size; 534 __u32 wave_front_size; 535 __u32 num_shader_visible_vgprs; 536 __u32 num_cu_per_sh; 537 __u32 num_tcc_blocks; 538 __u32 gs_vgt_table_depth; 539 __u32 gs_prim_buffer_depth; 540 __u32 max_gs_waves_per_vgt; 541 __u32 _pad1; 542 __u32 cu_ao_bitmap[4][4]; 543 }; 544 struct drm_amdgpu_info_hw_ip { 545 __u32 hw_ip_version_major; 546 __u32 hw_ip_version_minor; 547 __u64 capabilities_flags; 548 __u32 ib_start_alignment; 549 __u32 ib_size_alignment; 550 __u32 available_rings; 551 __u32 _pad; 552 }; 553 struct drm_amdgpu_info_num_handles { 554 __u32 uvd_max_handles; 555 __u32 uvd_used_handles; 556 }; 557 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 558 struct drm_amdgpu_info_vce_clock_table_entry { 559 __u32 sclk; 560 __u32 mclk; 561 __u32 eclk; 562 __u32 pad; 563 }; 564 struct drm_amdgpu_info_vce_clock_table { 565 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 566 __u32 num_valid_entries; 567 __u32 pad; 568 }; 569 #define AMDGPU_FAMILY_UNKNOWN 0 570 #define AMDGPU_FAMILY_SI 110 571 #define AMDGPU_FAMILY_CI 120 572 #define AMDGPU_FAMILY_KV 125 573 #define AMDGPU_FAMILY_VI 130 574 #define AMDGPU_FAMILY_CZ 135 575 #define AMDGPU_FAMILY_AI 141 576 #define AMDGPU_FAMILY_RV 142 577 #ifdef __cplusplus 578 #endif 579 #endif 580