1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_EXYNOS_DRM_H_ 20 #define _UAPI_EXYNOS_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 #endif 24 struct drm_exynos_gem_create { 25 __u64 size; 26 __u32 flags; 27 __u32 handle; 28 }; 29 struct drm_exynos_gem_map { 30 __u32 handle; 31 __u32 reserved; 32 __u64 offset; 33 }; 34 struct drm_exynos_gem_info { 35 __u32 handle; 36 __u32 flags; 37 __u64 size; 38 }; 39 struct drm_exynos_vidi_connection { 40 __u32 connection; 41 __u32 extensions; 42 __u64 edid; 43 }; 44 enum e_drm_exynos_gem_mem_type { 45 EXYNOS_BO_CONTIG = 0 << 0, 46 EXYNOS_BO_NONCONTIG = 1 << 0, 47 EXYNOS_BO_NONCACHABLE = 0 << 1, 48 EXYNOS_BO_CACHABLE = 1 << 1, 49 EXYNOS_BO_WC = 1 << 2, 50 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | EXYNOS_BO_WC 51 }; 52 struct drm_exynos_g2d_get_ver { 53 __u32 major; 54 __u32 minor; 55 }; 56 struct drm_exynos_g2d_cmd { 57 __u32 offset; 58 __u32 data; 59 }; 60 enum drm_exynos_g2d_buf_type { 61 G2D_BUF_USERPTR = 1 << 31, 62 }; 63 enum drm_exynos_g2d_event_type { 64 G2D_EVENT_NOT, 65 G2D_EVENT_NONSTOP, 66 G2D_EVENT_STOP, 67 }; 68 struct drm_exynos_g2d_userptr { 69 unsigned long userptr; 70 unsigned long size; 71 }; 72 struct drm_exynos_g2d_set_cmdlist { 73 __u64 cmd; 74 __u64 cmd_buf; 75 __u32 cmd_nr; 76 __u32 cmd_buf_nr; 77 __u64 event_type; 78 __u64 user_data; 79 }; 80 struct drm_exynos_g2d_exec { 81 __u64 async; 82 }; 83 enum drm_exynos_ops_id { 84 EXYNOS_DRM_OPS_SRC, 85 EXYNOS_DRM_OPS_DST, 86 EXYNOS_DRM_OPS_MAX, 87 }; 88 struct drm_exynos_sz { 89 __u32 hsize; 90 __u32 vsize; 91 }; 92 struct drm_exynos_pos { 93 __u32 x; 94 __u32 y; 95 __u32 w; 96 __u32 h; 97 }; 98 enum drm_exynos_flip { 99 EXYNOS_DRM_FLIP_NONE = (0 << 0), 100 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), 101 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), 102 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | EXYNOS_DRM_FLIP_HORIZONTAL, 103 }; 104 enum drm_exynos_degree { 105 EXYNOS_DRM_DEGREE_0, 106 EXYNOS_DRM_DEGREE_90, 107 EXYNOS_DRM_DEGREE_180, 108 EXYNOS_DRM_DEGREE_270, 109 }; 110 enum drm_exynos_planer { 111 EXYNOS_DRM_PLANAR_Y, 112 EXYNOS_DRM_PLANAR_CB, 113 EXYNOS_DRM_PLANAR_CR, 114 EXYNOS_DRM_PLANAR_MAX, 115 }; 116 struct drm_exynos_ipp_prop_list { 117 __u32 version; 118 __u32 ipp_id; 119 __u32 count; 120 __u32 writeback; 121 __u32 flip; 122 __u32 degree; 123 __u32 csc; 124 __u32 crop; 125 __u32 scale; 126 __u32 refresh_min; 127 __u32 refresh_max; 128 __u32 reserved; 129 struct drm_exynos_sz crop_min; 130 struct drm_exynos_sz crop_max; 131 struct drm_exynos_sz scale_min; 132 struct drm_exynos_sz scale_max; 133 }; 134 struct drm_exynos_ipp_config { 135 __u32 ops_id; 136 __u32 flip; 137 __u32 degree; 138 __u32 fmt; 139 struct drm_exynos_sz sz; 140 struct drm_exynos_pos pos; 141 }; 142 enum drm_exynos_ipp_cmd { 143 IPP_CMD_NONE, 144 IPP_CMD_M2M, 145 IPP_CMD_WB, 146 IPP_CMD_OUTPUT, 147 IPP_CMD_MAX, 148 }; 149 struct drm_exynos_ipp_property { 150 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; 151 __u32 cmd; 152 __u32 ipp_id; 153 __u32 prop_id; 154 __u32 refresh_rate; 155 }; 156 enum drm_exynos_ipp_buf_type { 157 IPP_BUF_ENQUEUE, 158 IPP_BUF_DEQUEUE, 159 }; 160 struct drm_exynos_ipp_queue_buf { 161 __u32 ops_id; 162 __u32 buf_type; 163 __u32 prop_id; 164 __u32 buf_id; 165 __u32 handle[EXYNOS_DRM_PLANAR_MAX]; 166 __u32 reserved; 167 __u64 user_data; 168 }; 169 enum drm_exynos_ipp_ctrl { 170 IPP_CTRL_PLAY, 171 IPP_CTRL_STOP, 172 IPP_CTRL_PAUSE, 173 IPP_CTRL_RESUME, 174 IPP_CTRL_MAX, 175 }; 176 struct drm_exynos_ipp_cmd_ctrl { 177 __u32 prop_id; 178 __u32 ctrl; 179 }; 180 #define DRM_EXYNOS_GEM_CREATE 0x00 181 #define DRM_EXYNOS_GEM_MAP 0x01 182 #define DRM_EXYNOS_GEM_GET 0x04 183 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 184 #define DRM_EXYNOS_G2D_GET_VER 0x20 185 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 186 #define DRM_EXYNOS_G2D_EXEC 0x22 187 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 188 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 189 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 190 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 191 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 192 #define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map) 193 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 194 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 195 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 196 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 197 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 198 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) 199 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) 200 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) 201 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) 202 #define DRM_EXYNOS_G2D_EVENT 0x80000000 203 #define DRM_EXYNOS_IPP_EVENT 0x80000001 204 struct drm_exynos_g2d_event { 205 struct drm_event base; 206 __u64 user_data; 207 __u32 tv_sec; 208 __u32 tv_usec; 209 __u32 cmdlist_no; 210 __u32 reserved; 211 }; 212 struct drm_exynos_ipp_event { 213 struct drm_event base; 214 __u64 user_data; 215 __u32 tv_sec; 216 __u32 tv_usec; 217 __u32 prop_id; 218 __u32 reserved; 219 __u32 buf_id[EXYNOS_DRM_OPS_MAX]; 220 }; 221 #ifdef __cplusplus 222 #endif 223 #endif 224