1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef MLX5_ABI_USER_H 20 #define MLX5_ABI_USER_H 21 #include <linux/types.h> 22 #include <linux/if_ether.h> 23 enum { 24 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 25 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 26 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 27 }; 28 enum { 29 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 30 }; 31 enum { 32 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 33 }; 34 #define MLX5_IB_UVERBS_ABI_VERSION 1 35 struct mlx5_ib_alloc_ucontext_req { 36 __u32 total_num_bfregs; 37 __u32 num_low_latency_bfregs; 38 }; 39 enum mlx5_lib_caps { 40 MLX5_LIB_CAP_4K_UAR = (__u64) 1 << 0, 41 }; 42 struct mlx5_ib_alloc_ucontext_req_v2 { 43 __u32 total_num_bfregs; 44 __u32 num_low_latency_bfregs; 45 __u32 flags; 46 __u32 comp_mask; 47 __u8 max_cqe_version; 48 __u8 reserved0; 49 __u16 reserved1; 50 __u32 reserved2; 51 __u64 lib_caps; 52 }; 53 enum mlx5_ib_alloc_ucontext_resp_mask { 54 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 55 }; 56 enum mlx5_user_cmds_supp_uhw { 57 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 58 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 59 }; 60 enum mlx5_user_inline_mode { 61 MLX5_USER_INLINE_MODE_NA, 62 MLX5_USER_INLINE_MODE_NONE, 63 MLX5_USER_INLINE_MODE_L2, 64 MLX5_USER_INLINE_MODE_IP, 65 MLX5_USER_INLINE_MODE_TCP_UDP, 66 }; 67 struct mlx5_ib_alloc_ucontext_resp { 68 __u32 qp_tab_size; 69 __u32 bf_reg_size; 70 __u32 tot_bfregs; 71 __u32 cache_line_size; 72 __u16 max_sq_desc_sz; 73 __u16 max_rq_desc_sz; 74 __u32 max_send_wqebb; 75 __u32 max_recv_wr; 76 __u32 max_srq_recv_wr; 77 __u16 num_ports; 78 __u16 reserved1; 79 __u32 comp_mask; 80 __u32 response_length; 81 __u8 cqe_version; 82 __u8 cmds_supp_uhw; 83 __u8 eth_min_inline; 84 __u8 reserved2; 85 __u64 hca_core_clock_offset; 86 __u32 log_uar_size; 87 __u32 num_uars_per_page; 88 }; 89 struct mlx5_ib_alloc_pd_resp { 90 __u32 pdn; 91 }; 92 struct mlx5_ib_tso_caps { 93 __u32 max_tso; 94 __u32 supported_qpts; 95 }; 96 struct mlx5_ib_rss_caps { 97 __u64 rx_hash_fields_mask; 98 __u8 rx_hash_function; 99 __u8 reserved[7]; 100 }; 101 enum mlx5_ib_cqe_comp_res_format { 102 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 103 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 104 MLX5_IB_CQE_RES_RESERVED = 1 << 2, 105 }; 106 struct mlx5_ib_cqe_comp_caps { 107 __u32 max_num; 108 __u32 supported_format; 109 }; 110 struct mlx5_packet_pacing_caps { 111 __u32 qp_rate_limit_min; 112 __u32 qp_rate_limit_max; 113 __u32 supported_qpts; 114 __u32 reserved; 115 }; 116 enum mlx5_ib_mpw_caps { 117 MPW_RESERVED = 1 << 0, 118 MLX5_IB_ALLOW_MPW = 1 << 1, 119 MLX5_IB_SUPPORT_EMPW = 1 << 2, 120 }; 121 enum mlx5_ib_sw_parsing_offloads { 122 MLX5_IB_SW_PARSING = 1 << 0, 123 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 124 MLX5_IB_SW_PARSING_LSO = 1 << 2, 125 }; 126 struct mlx5_ib_sw_parsing_caps { 127 __u32 sw_parsing_offloads; 128 __u32 supported_qpts; 129 }; 130 struct mlx5_ib_striding_rq_caps { 131 __u32 min_single_stride_log_num_of_bytes; 132 __u32 max_single_stride_log_num_of_bytes; 133 __u32 min_single_wqe_log_num_of_strides; 134 __u32 max_single_wqe_log_num_of_strides; 135 __u32 supported_qpts; 136 __u32 reserved; 137 }; 138 enum mlx5_ib_query_dev_resp_flags { 139 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 140 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 141 }; 142 enum mlx5_ib_tunnel_offloads { 143 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 144 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 145 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2 146 }; 147 struct mlx5_ib_query_device_resp { 148 __u32 comp_mask; 149 __u32 response_length; 150 struct mlx5_ib_tso_caps tso_caps; 151 struct mlx5_ib_rss_caps rss_caps; 152 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 153 struct mlx5_packet_pacing_caps packet_pacing_caps; 154 __u32 mlx5_ib_support_multi_pkt_send_wqes; 155 __u32 flags; 156 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 157 struct mlx5_ib_striding_rq_caps striding_rq_caps; 158 __u32 tunnel_offloads_caps; 159 __u32 reserved; 160 }; 161 enum mlx5_ib_create_cq_flags { 162 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 163 }; 164 struct mlx5_ib_create_cq { 165 __u64 buf_addr; 166 __u64 db_addr; 167 __u32 cqe_size; 168 __u8 cqe_comp_en; 169 __u8 cqe_comp_res_format; 170 __u16 flags; 171 }; 172 struct mlx5_ib_create_cq_resp { 173 __u32 cqn; 174 __u32 reserved; 175 }; 176 struct mlx5_ib_resize_cq { 177 __u64 buf_addr; 178 __u16 cqe_size; 179 __u16 reserved0; 180 __u32 reserved1; 181 }; 182 struct mlx5_ib_create_srq { 183 __u64 buf_addr; 184 __u64 db_addr; 185 __u32 flags; 186 __u32 reserved0; 187 __u32 uidx; 188 __u32 reserved1; 189 }; 190 struct mlx5_ib_create_srq_resp { 191 __u32 srqn; 192 __u32 reserved; 193 }; 194 struct mlx5_ib_create_qp { 195 __u64 buf_addr; 196 __u64 db_addr; 197 __u32 sq_wqe_count; 198 __u32 rq_wqe_count; 199 __u32 rq_wqe_shift; 200 __u32 flags; 201 __u32 uidx; 202 __u32 reserved0; 203 __u64 sq_buf_addr; 204 }; 205 enum mlx5_rx_hash_function_flags { 206 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 207 }; 208 enum mlx5_rx_hash_fields { 209 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 210 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 211 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 212 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 213 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 214 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 215 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 216 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 217 MLX5_RX_HASH_INNER = 1 << 31 218 }; 219 struct mlx5_ib_create_qp_rss { 220 __u64 rx_hash_fields_mask; 221 __u8 rx_hash_function; 222 __u8 rx_key_len; 223 __u8 reserved[6]; 224 __u8 rx_hash_key[128]; 225 __u32 comp_mask; 226 __u32 flags; 227 }; 228 struct mlx5_ib_create_qp_resp { 229 __u32 bfreg_index; 230 }; 231 struct mlx5_ib_alloc_mw { 232 __u32 comp_mask; 233 __u8 num_klms; 234 __u8 reserved1; 235 __u16 reserved2; 236 }; 237 enum mlx5_ib_create_wq_mask { 238 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 239 }; 240 struct mlx5_ib_create_wq { 241 __u64 buf_addr; 242 __u64 db_addr; 243 __u32 rq_wqe_count; 244 __u32 rq_wqe_shift; 245 __u32 user_index; 246 __u32 flags; 247 __u32 comp_mask; 248 __u32 single_stride_log_num_of_bytes; 249 __u32 single_wqe_log_num_of_strides; 250 __u32 two_byte_shift_en; 251 }; 252 struct mlx5_ib_create_ah_resp { 253 __u32 response_length; 254 __u8 dmac[ETH_ALEN]; 255 __u8 reserved[6]; 256 }; 257 struct mlx5_ib_create_wq_resp { 258 __u32 response_length; 259 __u32 reserved; 260 }; 261 struct mlx5_ib_create_rwq_ind_tbl_resp { 262 __u32 response_length; 263 __u32 reserved; 264 }; 265 struct mlx5_ib_modify_wq { 266 __u32 comp_mask; 267 __u32 reserved; 268 }; 269 #endif 270