1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|*Target Register Enum Values *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9/* Capstone Disassembly Engine */ 10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ 11 12 13#ifdef GET_REGINFO_ENUM 14#undef GET_REGINFO_ENUM 15 16enum { 17 SP_NoRegister, 18 SP_ICC = 1, 19 SP_Y = 2, 20 SP_D0 = 3, 21 SP_D1 = 4, 22 SP_D2 = 5, 23 SP_D3 = 6, 24 SP_D4 = 7, 25 SP_D5 = 8, 26 SP_D6 = 9, 27 SP_D7 = 10, 28 SP_D8 = 11, 29 SP_D9 = 12, 30 SP_D10 = 13, 31 SP_D11 = 14, 32 SP_D12 = 15, 33 SP_D13 = 16, 34 SP_D14 = 17, 35 SP_D15 = 18, 36 SP_D16 = 19, 37 SP_D17 = 20, 38 SP_D18 = 21, 39 SP_D19 = 22, 40 SP_D20 = 23, 41 SP_D21 = 24, 42 SP_D22 = 25, 43 SP_D23 = 26, 44 SP_D24 = 27, 45 SP_D25 = 28, 46 SP_D26 = 29, 47 SP_D27 = 30, 48 SP_D28 = 31, 49 SP_D29 = 32, 50 SP_D30 = 33, 51 SP_D31 = 34, 52 SP_F0 = 35, 53 SP_F1 = 36, 54 SP_F2 = 37, 55 SP_F3 = 38, 56 SP_F4 = 39, 57 SP_F5 = 40, 58 SP_F6 = 41, 59 SP_F7 = 42, 60 SP_F8 = 43, 61 SP_F9 = 44, 62 SP_F10 = 45, 63 SP_F11 = 46, 64 SP_F12 = 47, 65 SP_F13 = 48, 66 SP_F14 = 49, 67 SP_F15 = 50, 68 SP_F16 = 51, 69 SP_F17 = 52, 70 SP_F18 = 53, 71 SP_F19 = 54, 72 SP_F20 = 55, 73 SP_F21 = 56, 74 SP_F22 = 57, 75 SP_F23 = 58, 76 SP_F24 = 59, 77 SP_F25 = 60, 78 SP_F26 = 61, 79 SP_F27 = 62, 80 SP_F28 = 63, 81 SP_F29 = 64, 82 SP_F30 = 65, 83 SP_F31 = 66, 84 SP_FCC0 = 67, 85 SP_FCC1 = 68, 86 SP_FCC2 = 69, 87 SP_FCC3 = 70, 88 SP_G0 = 71, 89 SP_G1 = 72, 90 SP_G2 = 73, 91 SP_G3 = 74, 92 SP_G4 = 75, 93 SP_G5 = 76, 94 SP_G6 = 77, 95 SP_G7 = 78, 96 SP_I0 = 79, 97 SP_I1 = 80, 98 SP_I2 = 81, 99 SP_I3 = 82, 100 SP_I4 = 83, 101 SP_I5 = 84, 102 SP_I6 = 85, 103 SP_I7 = 86, 104 SP_L0 = 87, 105 SP_L1 = 88, 106 SP_L2 = 89, 107 SP_L3 = 90, 108 SP_L4 = 91, 109 SP_L5 = 92, 110 SP_L6 = 93, 111 SP_L7 = 94, 112 SP_O0 = 95, 113 SP_O1 = 96, 114 SP_O2 = 97, 115 SP_O3 = 98, 116 SP_O4 = 99, 117 SP_O5 = 100, 118 SP_O6 = 101, 119 SP_O7 = 102, 120 SP_Q0 = 103, 121 SP_Q1 = 104, 122 SP_Q2 = 105, 123 SP_Q3 = 106, 124 SP_Q4 = 107, 125 SP_Q5 = 108, 126 SP_Q6 = 109, 127 SP_Q7 = 110, 128 SP_Q8 = 111, 129 SP_Q9 = 112, 130 SP_Q10 = 113, 131 SP_Q11 = 114, 132 SP_Q12 = 115, 133 SP_Q13 = 116, 134 SP_Q14 = 117, 135 SP_Q15 = 118, 136 SP_NUM_TARGET_REGS // 119 137}; 138 139// Register classes 140enum { 141 SP_FCCRegsRegClassID = 0, 142 SP_FPRegsRegClassID = 1, 143 SP_IntRegsRegClassID = 2, 144 SP_DFPRegsRegClassID = 3, 145 SP_I64RegsRegClassID = 4, 146 SP_DFPRegs_with_sub_evenRegClassID = 5, 147 SP_QFPRegsRegClassID = 6, 148 SP_QFPRegs_with_sub_evenRegClassID = 7 149}; 150 151// Subregister indices 152enum { 153 SP_NoSubRegister, 154 SP_sub_even, // 1 155 SP_sub_even64, // 2 156 SP_sub_odd, // 3 157 SP_sub_odd64, // 4 158 SP_sub_odd64_then_sub_even, // 5 159 SP_sub_odd64_then_sub_odd, // 6 160 SP_NUM_TARGET_SUBREGS 161}; 162#endif // GET_REGINFO_ENUM 163 164/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 165|* *| 166|*MC Register Information *| 167|* *| 168|* Automatically generated file, do not edit! *| 169|* *| 170\*===----------------------------------------------------------------------===*/ 171 172 173#ifdef GET_REGINFO_MC_DESC 174#undef GET_REGINFO_MC_DESC 175 176static MCPhysReg SparcRegDiffLists[] = { 177 /* 0 */ 65126, 1, 1, 1, 0, 178 /* 5 */ 32, 1, 0, 179 /* 8 */ 65436, 32, 1, 65504, 33, 1, 0, 180 /* 15 */ 34, 1, 0, 181 /* 18 */ 65437, 34, 1, 65502, 35, 1, 0, 182 /* 25 */ 36, 1, 0, 183 /* 28 */ 65438, 36, 1, 65500, 37, 1, 0, 184 /* 35 */ 38, 1, 0, 185 /* 38 */ 65439, 38, 1, 65498, 39, 1, 0, 186 /* 45 */ 40, 1, 0, 187 /* 48 */ 65440, 40, 1, 65496, 41, 1, 0, 188 /* 55 */ 42, 1, 0, 189 /* 58 */ 65441, 42, 1, 65494, 43, 1, 0, 190 /* 65 */ 44, 1, 0, 191 /* 68 */ 65442, 44, 1, 65492, 45, 1, 0, 192 /* 75 */ 46, 1, 0, 193 /* 78 */ 65443, 46, 1, 65490, 47, 1, 0, 194 /* 85 */ 65348, 1, 0, 195 /* 88 */ 65444, 1, 0, 196 /* 91 */ 65445, 1, 0, 197 /* 94 */ 65446, 1, 0, 198 /* 97 */ 65447, 1, 0, 199 /* 100 */ 65448, 1, 0, 200 /* 103 */ 65449, 1, 0, 201 /* 106 */ 65450, 1, 0, 202 /* 109 */ 65451, 1, 0, 203 /* 112 */ 65532, 1, 0, 204 /* 115 */ 15, 0, 205 /* 117 */ 84, 0, 206 /* 119 */ 85, 0, 207 /* 121 */ 86, 0, 208 /* 123 */ 87, 0, 209 /* 125 */ 88, 0, 210 /* 127 */ 89, 0, 211 /* 129 */ 90, 0, 212 /* 131 */ 91, 0, 213 /* 133 */ 65488, 92, 0, 214 /* 136 */ 65489, 92, 0, 215 /* 139 */ 65489, 93, 0, 216 /* 142 */ 65490, 93, 0, 217 /* 145 */ 65491, 93, 0, 218 /* 148 */ 65491, 94, 0, 219 /* 151 */ 65492, 94, 0, 220 /* 154 */ 65493, 94, 0, 221 /* 157 */ 65493, 95, 0, 222 /* 160 */ 65494, 95, 0, 223 /* 163 */ 65495, 95, 0, 224 /* 166 */ 65495, 96, 0, 225 /* 169 */ 65496, 96, 0, 226 /* 172 */ 65497, 96, 0, 227 /* 175 */ 65497, 97, 0, 228 /* 178 */ 65498, 97, 0, 229 /* 181 */ 65499, 97, 0, 230 /* 184 */ 65499, 98, 0, 231 /* 187 */ 65500, 98, 0, 232 /* 190 */ 65501, 98, 0, 233 /* 193 */ 65501, 99, 0, 234 /* 196 */ 65502, 99, 0, 235 /* 199 */ 65503, 99, 0, 236 /* 202 */ 65503, 100, 0, 237 /* 205 */ 65504, 100, 0, 238 /* 208 */ 65503, 0, 239 /* 210 */ 65519, 0, 240 /* 212 */ 65535, 0, 241}; 242 243static uint16_t SparcSubRegIdxLists[] = { 244 /* 0 */ 1, 3, 0, 245 /* 3 */ 2, 4, 0, 246 /* 6 */ 2, 1, 3, 4, 5, 6, 0, 247}; 248 249static MCRegisterDesc SparcRegDesc[] = { // Descriptors 250 { 3, 0, 0, 0, 0 }, 251 { 406, 4, 4, 2, 3393 }, 252 { 410, 4, 4, 2, 3393 }, 253 { 33, 5, 203, 0, 1794 }, 254 { 87, 12, 194, 0, 1794 }, 255 { 133, 15, 194, 0, 1794 }, 256 { 179, 22, 185, 0, 1794 }, 257 { 220, 25, 185, 0, 1794 }, 258 { 261, 32, 176, 0, 1794 }, 259 { 298, 35, 176, 0, 1794 }, 260 { 335, 42, 167, 0, 1794 }, 261 { 372, 45, 167, 0, 1794 }, 262 { 397, 52, 158, 0, 1794 }, 263 { 0, 55, 158, 0, 1794 }, 264 { 54, 62, 149, 0, 1794 }, 265 { 108, 65, 149, 0, 1794 }, 266 { 154, 72, 140, 0, 1794 }, 267 { 200, 75, 140, 0, 1794 }, 268 { 241, 82, 134, 0, 1794 }, 269 { 282, 4, 134, 2, 1841 }, 270 { 319, 4, 131, 2, 1841 }, 271 { 356, 4, 131, 2, 1841 }, 272 { 381, 4, 129, 2, 1841 }, 273 { 12, 4, 129, 2, 1841 }, 274 { 66, 4, 127, 2, 1841 }, 275 { 120, 4, 127, 2, 1841 }, 276 { 166, 4, 125, 2, 1841 }, 277 { 212, 4, 125, 2, 1841 }, 278 { 253, 4, 123, 2, 1841 }, 279 { 290, 4, 123, 2, 1841 }, 280 { 327, 4, 121, 2, 1841 }, 281 { 364, 4, 121, 2, 1841 }, 282 { 389, 4, 119, 2, 1841 }, 283 { 20, 4, 119, 2, 1841 }, 284 { 74, 4, 117, 2, 1841 }, 285 { 36, 4, 205, 2, 3329 }, 286 { 90, 4, 202, 2, 3329 }, 287 { 136, 4, 199, 2, 3329 }, 288 { 182, 4, 196, 2, 3329 }, 289 { 223, 4, 196, 2, 3329 }, 290 { 264, 4, 193, 2, 3329 }, 291 { 301, 4, 190, 2, 3329 }, 292 { 338, 4, 187, 2, 3329 }, 293 { 375, 4, 187, 2, 3329 }, 294 { 400, 4, 184, 2, 3329 }, 295 { 4, 4, 181, 2, 3329 }, 296 { 58, 4, 178, 2, 3329 }, 297 { 112, 4, 178, 2, 3329 }, 298 { 158, 4, 175, 2, 3329 }, 299 { 204, 4, 172, 2, 3329 }, 300 { 245, 4, 169, 2, 3329 }, 301 { 286, 4, 169, 2, 3329 }, 302 { 323, 4, 166, 2, 3329 }, 303 { 360, 4, 163, 2, 3329 }, 304 { 385, 4, 160, 2, 3329 }, 305 { 16, 4, 160, 2, 3329 }, 306 { 70, 4, 157, 2, 3329 }, 307 { 124, 4, 154, 2, 3329 }, 308 { 170, 4, 151, 2, 3329 }, 309 { 216, 4, 151, 2, 3329 }, 310 { 257, 4, 148, 2, 3329 }, 311 { 294, 4, 145, 2, 3329 }, 312 { 331, 4, 142, 2, 3329 }, 313 { 368, 4, 142, 2, 3329 }, 314 { 393, 4, 139, 2, 3329 }, 315 { 24, 4, 136, 2, 3329 }, 316 { 78, 4, 133, 2, 3329 }, 317 { 28, 4, 4, 2, 3361 }, 318 { 82, 4, 4, 2, 3361 }, 319 { 128, 4, 4, 2, 3361 }, 320 { 174, 4, 4, 2, 3361 }, 321 { 39, 4, 4, 2, 3361 }, 322 { 93, 4, 4, 2, 3361 }, 323 { 139, 4, 4, 2, 3361 }, 324 { 185, 4, 4, 2, 3361 }, 325 { 226, 4, 4, 2, 3361 }, 326 { 267, 4, 4, 2, 3361 }, 327 { 304, 4, 4, 2, 3361 }, 328 { 341, 4, 4, 2, 3361 }, 329 { 42, 4, 4, 2, 3361 }, 330 { 96, 4, 4, 2, 3361 }, 331 { 142, 4, 4, 2, 3361 }, 332 { 188, 4, 4, 2, 3361 }, 333 { 229, 4, 4, 2, 3361 }, 334 { 270, 4, 4, 2, 3361 }, 335 { 307, 4, 4, 2, 3361 }, 336 { 344, 4, 4, 2, 3361 }, 337 { 45, 4, 4, 2, 3361 }, 338 { 99, 4, 4, 2, 3361 }, 339 { 145, 4, 4, 2, 3361 }, 340 { 191, 4, 4, 2, 3361 }, 341 { 232, 4, 4, 2, 3361 }, 342 { 273, 4, 4, 2, 3361 }, 343 { 310, 4, 4, 2, 3361 }, 344 { 347, 4, 4, 2, 3361 }, 345 { 48, 4, 4, 2, 3361 }, 346 { 102, 4, 4, 2, 3361 }, 347 { 148, 4, 4, 2, 3361 }, 348 { 194, 4, 4, 2, 3361 }, 349 { 235, 4, 4, 2, 3361 }, 350 { 276, 4, 4, 2, 3361 }, 351 { 313, 4, 4, 2, 3361 }, 352 { 350, 4, 4, 2, 3361 }, 353 { 51, 8, 4, 6, 4 }, 354 { 105, 18, 4, 6, 4 }, 355 { 151, 28, 4, 6, 4 }, 356 { 197, 38, 4, 6, 4 }, 357 { 238, 48, 4, 6, 4 }, 358 { 279, 58, 4, 6, 4 }, 359 { 316, 68, 4, 6, 4 }, 360 { 353, 78, 4, 6, 4 }, 361 { 378, 88, 4, 3, 1362 }, 362 { 403, 91, 4, 3, 1362 }, 363 { 8, 94, 4, 3, 1362 }, 364 { 62, 97, 4, 3, 1362 }, 365 { 116, 100, 4, 3, 1362 }, 366 { 162, 103, 4, 3, 1362 }, 367 { 208, 106, 4, 3, 1362 }, 368 { 249, 109, 4, 3, 1362 }, 369}; 370 371 // FCCRegs Register Class... 372 static MCPhysReg FCCRegs[] = { 373 SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3, 374 }; 375 376 // FCCRegs Bit set. 377 static uint8_t FCCRegsBits[] = { 378 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 379 }; 380 381 // FPRegs Register Class... 382 static MCPhysReg FPRegs[] = { 383 SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31, 384 }; 385 386 // FPRegs Bit set. 387 static uint8_t FPRegsBits[] = { 388 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 389 }; 390 391 // IntRegs Register Class... 392 static MCPhysReg IntRegs[] = { 393 SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, 394 }; 395 396 // IntRegs Bit set. 397 static uint8_t IntRegsBits[] = { 398 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 399 }; 400 401 // DFPRegs Register Class... 402 static MCPhysReg DFPRegs[] = { 403 SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31, 404 }; 405 406 // DFPRegs Bit set. 407 static uint8_t DFPRegsBits[] = { 408 0xf8, 0xff, 0xff, 0xff, 0x07, 409 }; 410 411 // I64Regs Register Class... 412 static MCPhysReg I64Regs[] = { 413 SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7, 414 }; 415 416 // I64Regs Bit set. 417 static uint8_t I64RegsBits[] = { 418 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 419 }; 420 421 // DFPRegs_with_sub_even Register Class... 422 static MCPhysReg DFPRegs_with_sub_even[] = { 423 SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, 424 }; 425 426 // DFPRegs_with_sub_even Bit set. 427 static uint8_t DFPRegs_with_sub_evenBits[] = { 428 0xf8, 0xff, 0x07, 429 }; 430 431 // QFPRegs Register Class... 432 static MCPhysReg QFPRegs[] = { 433 SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15, 434 }; 435 436 // QFPRegs Bit set. 437 static uint8_t QFPRegsBits[] = { 438 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 439 }; 440 441 // QFPRegs_with_sub_even Register Class... 442 static MCPhysReg QFPRegs_with_sub_even[] = { 443 SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, 444 }; 445 446 // QFPRegs_with_sub_even Bit set. 447 static uint8_t QFPRegs_with_sub_evenBits[] = { 448 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 449 }; 450 451static MCRegisterClass SparcMCRegisterClasses[] = { 452 { "FCCRegs", FCCRegs, FCCRegsBits, 4, sizeof(FCCRegsBits), SP_FCCRegsRegClassID, 0, 0, 1, 1 }, 453 { "FPRegs", FPRegs, FPRegsBits, 32, sizeof(FPRegsBits), SP_FPRegsRegClassID, 4, 4, 1, 1 }, 454 { "IntRegs", IntRegs, IntRegsBits, 32, sizeof(IntRegsBits), SP_IntRegsRegClassID, 4, 4, 1, 1 }, 455 { "DFPRegs", DFPRegs, DFPRegsBits, 32, sizeof(DFPRegsBits), SP_DFPRegsRegClassID, 8, 8, 1, 1 }, 456 { "I64Regs", I64Regs, I64RegsBits, 32, sizeof(I64RegsBits), SP_I64RegsRegClassID, 8, 8, 1, 1 }, 457 { "DFPRegs_with_sub_even", DFPRegs_with_sub_even, DFPRegs_with_sub_evenBits, 16, sizeof(DFPRegs_with_sub_evenBits), SP_DFPRegs_with_sub_evenRegClassID, 8, 8, 1, 1 }, 458 { "QFPRegs", QFPRegs, QFPRegsBits, 16, sizeof(QFPRegsBits), SP_QFPRegsRegClassID, 16, 16, 1, 1 }, 459 { "QFPRegs_with_sub_even", QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, 8, sizeof(QFPRegs_with_sub_evenBits), SP_QFPRegs_with_sub_evenRegClassID, 16, 16, 1, 1 }, 460}; 461 462#endif // GET_REGINFO_MC_DESC 463