1 // RUN: %clang_cc1 -triple x86_64-apple-darwin -std=c++11 -emit-llvm -o - %s | FileCheck %s 2 3 // Verify assume_safety vectorization is recognized. vectorize_test(int * List,int Length)4 void vectorize_test(int *List, int Length) { 5 // CHECK: define {{.*}} @_Z14vectorize_test 6 // CHECK: [[LOAD1_IV:.+]] = load i32, i32* [[IV1:[^,]+]], {{.*}}!llvm.mem.parallel_loop_access ![[LOOP1_ID:[0-9]+]] 7 // CHECK-NEXT: [[LOAD1_LEN:.+]] = load i32, i32* [[LEN1:.+]], {{.*}}!llvm.mem.parallel_loop_access ![[LOOP1_ID]] 8 // CHECK-NEXT: [[CMP1:.+]] = icmp slt i32[[LOAD1_IV]],[[LOAD1_LEN]] 9 // CHECK-NEXT: br i1[[CMP1]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]] 10 #pragma clang loop vectorize(assume_safety) interleave(disable) unroll(disable) 11 for (int i = 0; i < Length; i++) { 12 // CHECK: [[RHIV1:.+]] = load i32, i32* [[IV1]], {{.*}}!llvm.mem.parallel_loop_access ![[LOOP1_ID]] 13 // CHECK-NEXT: [[CALC1:.+]] = mul nsw i32[[RHIV1]], 2 14 // CHECK-NEXT: [[SIV1:.+]] = load i32, i32* [[IV1]]{{.*}}!llvm.mem.parallel_loop_access ![[LOOP1_ID]] 15 // CHECK-NEXT: [[INDEX1:.+]] = sext i32[[SIV1]] to i64 16 // CHECK-NEXT: [[ARRAY1:.+]] = load i32*, i32** [[LIST1:.*]], {{.*}}!llvm.mem.parallel_loop_access ![[LOOP1_ID]] 17 // CHECK-NEXT: [[PTR1:.+]] = getelementptr inbounds i32, i32*[[ARRAY1]], i64[[INDEX1]] 18 // CHECK-NEXT: store i32[[CALC1]], i32*[[PTR1]], {{.*}}!llvm.mem.parallel_loop_access ![[LOOP1_ID]] 19 // CHECK-NEXT: br label [[LOOP1_INC:[^,]+]] 20 List[i] = i * 2; 21 22 // CHECK: br label [[LOOP1_COND:[^,]+]], !llvm.loop ![[LOOP1_HINTS:[0-9]+]] 23 } 24 } 25 26 // Verify assume_safety interleaving is recognized. interleave_test(int * List,int Length)27 void interleave_test(int *List, int Length) { 28 // CHECK: define {{.*}} @_Z15interleave_test 29 // CHECK: [[LOAD2_IV:.+]] = load i32, i32* [[IV2:[^,]+]], {{.*}}!llvm.mem.parallel_loop_access ![[LOOP2_ID:[0-9]+]] 30 // CHECK-NEXT: [[LOAD2_LEN:.+]] = load i32, i32* [[LEN2:.+]], {{.*}}!llvm.mem.parallel_loop_access ![[LOOP2_ID]] 31 // CHECK-NEXT: [[CMP2:.+]] = icmp slt i32[[LOAD2_IV]],[[LOAD2_LEN]] 32 // CHECK-NEXT: br i1[[CMP2]], label %[[LOOP2_BODY:[^,]+]], label %[[LOOP2_END:[^,]+]] 33 #pragma clang loop interleave(assume_safety) vectorize(disable) unroll(disable) 34 for (int i = 0; i < Length; i++) { 35 // CHECK: [[RHIV2:.+]] = load i32, i32* [[IV2]], {{.*}}!llvm.mem.parallel_loop_access ![[LOOP2_ID]] 36 // CHECK-NEXT: [[CALC2:.+]] = mul nsw i32[[RHIV2]], 2 37 // CHECK-NEXT: [[SIV2:.+]] = load i32, i32* [[IV2]]{{.*}}!llvm.mem.parallel_loop_access ![[LOOP2_ID]] 38 // CHECK-NEXT: [[INDEX2:.+]] = sext i32[[SIV2]] to i64 39 // CHECK-NEXT: [[ARRAY2:.+]] = load i32*, i32** [[LIST2:.*]], {{.*}}!llvm.mem.parallel_loop_access ![[LOOP2_ID]] 40 // CHECK-NEXT: [[PTR2:.+]] = getelementptr inbounds i32, i32*[[ARRAY2]], i64[[INDEX2]] 41 // CHECK-NEXT: store i32[[CALC2]], i32*[[PTR2]], {{.*}}!llvm.mem.parallel_loop_access ![[LOOP2_ID]] 42 // CHECK-NEXT: br label [[LOOP2_INC:[^,]+]] 43 List[i] = i * 2; 44 45 // CHECK: br label [[LOOP2_COND:[^,]+]], !llvm.loop ![[LOOP2_HINTS:[0-9]+]] 46 } 47 } 48 49 // CHECK: ![[LOOP1_HINTS]] = distinct !{![[LOOP1_HINTS]], ![[INTERLEAVE_1:[0-9]+]], ![[INTENABLE_1:[0-9]+]], ![[UNROLL_DISABLE:[0-9]+]]} 50 // CHECK: ![[INTERLEAVE_1]] = !{!"llvm.loop.interleave.count", i32 1} 51 // CHCCK: ![[INTENABLE_1]] = !{!"llvm.loop.vectorize.enable", i1 true} 52 // CHECK: ![[UNROLL_DISABLE]] = !{!"llvm.loop.unroll.disable"} 53 // CHECK: ![[LOOP2_HINTS]] = distinct !{![[LOOP2_HINTS]], ![[WIDTH_1:[0-9]+]], ![[INTENABLE_1]], ![[UNROLL_DISABLE]]} 54 // CHECK: ![[WIDTH_1]] = !{!"llvm.loop.vectorize.width", i32 1} 55