1 /******************************************************************************
2 * *
3 * Copyright (C) 2018 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 #include "string.h"
21 #include "ixheaacd_sbr_common.h"
22 #include <ixheaacd_type_def.h>
23
24 #include <ixheaacd_type_def.h>
25 #include "ixheaacd_constants.h"
26 #include <ixheaacd_basic_ops32.h>
27 #include <ixheaacd_basic_ops16.h>
28 #include <ixheaacd_basic_ops40.h>
29 #include "ixheaacd_bitbuffer.h"
30 #include "ixheaacd_defines.h"
31 #include <ixheaacd_aac_rom.h>
32 #include "ixheaacd_pulsedata.h"
33
34 #include "ixheaacd_pns.h"
35 #include "ixheaacd_drc_data_struct.h"
36
37 #include "ixheaacd_lt_predict.h"
38
39 #include "ixheaacd_channelinfo.h"
40 #include "ixheaacd_drc_dec.h"
41 #include "ixheaacd_sbrdecoder.h"
42
43 #include "ixheaacd_audioobjtypes.h"
44 #include "ixheaacd_sbrdecsettings.h"
45 #include "ixheaacd_memory_standards.h"
46 #include "ixheaacd_error_codes.h"
47
48 #include "ixheaacd_defines.h"
49
50 #include "ixheaacd_sbr_scale.h"
51 #include "ixheaacd_lpp_tran.h"
52 #include "ixheaacd_env_extr_part.h"
53 #include <ixheaacd_sbr_rom.h>
54
55 #include "ixheaacd_hybrid.h"
56 #include "ixheaacd_ps_dec.h"
57 #include "ixheaacd_ps_bitdec.h"
58
59 #include "ixheaacd_pulsedata.h"
60
61 #include "ixheaacd_pns.h"
62
63 #include "ixheaacd_channelinfo.h"
64
65 #include "ixheaacd_env_extr.h"
66 #include "ixheaacd_common_rom.h"
67 #include "ixheaacd_block.h"
68 #include "ixheaacd_channel.h"
69 #include "ixheaacd_audioobjtypes.h"
70 #include "ixheaacd_latmdemux.h"
71 #include "ixheaacd_aacdec.h"
72 #include "ixheaacd_mps_polyphase.h"
73 #include "ixheaacd_config.h"
74 #include "ixheaacd_mps_dec.h"
75 #include "ixheaacd_struct_def.h"
76 #include "ixheaacd_headerdecode.h"
77
78 #include "ixheaacd_multichannel.h"
79
80 #include <ixheaacd_basic_op.h>
81 #include "ixheaacd_intrinsics.h"
82
83 static PLATFORM_INLINE UWORD32
ixheaacd_aac_showbits_7(ia_bit_buf_struct * it_bit_buff)84 ixheaacd_aac_showbits_7(ia_bit_buf_struct *it_bit_buff) {
85 UWORD8 *v = it_bit_buff->ptr_read_next;
86 UWORD32 b = 0;
87 UWORD32 x;
88 b = (((WORD32)v[0] << 8) | (WORD32)(v[1]));
89 x = (UWORD32)b << (15 + 8 - it_bit_buff->bit_pos);
90 x = (UWORD32)x >> (25);
91 return x;
92 }
93
ixheaacd_get_channel_mask(ia_exhaacplus_dec_api_struct * p_obj_enhaacplus_dec)94 WORD ixheaacd_get_channel_mask(
95 ia_exhaacplus_dec_api_struct *p_obj_enhaacplus_dec) {
96 WORD ixheaacd_drc_offset = 0, channel_mask = 0;
97 WORD flag1 = 0, flag2 = 0;
98 WORD ch_idx;
99 WORD *ptr_slot_element = p_obj_enhaacplus_dec->aac_config.slot_element;
100 WORD *ptr_element_type = p_obj_enhaacplus_dec->aac_config.element_type;
101
102 memset(ptr_slot_element, 0, sizeof(WORD) * MAX_BS_ELEMENT);
103
104 for (ch_idx = 0; ch_idx < MAX_BS_ELEMENT; ch_idx++) {
105 if (ptr_element_type[ch_idx] == 1) {
106 channel_mask += 0x3;
107 ptr_slot_element[ch_idx] = ixheaacd_drc_offset;
108 ixheaacd_drc_offset += 2;
109 flag1 = ch_idx + 1;
110 break;
111 }
112 }
113
114 for (ch_idx = 0; ch_idx < MAX_BS_ELEMENT; ch_idx++) {
115 if (ptr_element_type[ch_idx] == 0) {
116 channel_mask += 0x4;
117 ptr_slot_element[ch_idx] = ixheaacd_drc_offset;
118 ixheaacd_drc_offset += 1;
119 flag2 = ch_idx + 1;
120 break;
121 }
122 }
123 for (ch_idx = 0; ch_idx < MAX_BS_ELEMENT; ch_idx++) {
124 if (ptr_element_type[ch_idx] == 3) {
125 channel_mask += 0x8;
126 ptr_slot_element[ch_idx] = ixheaacd_drc_offset;
127 ixheaacd_drc_offset += 1;
128 break;
129 }
130 }
131 for (ch_idx = flag1; ch_idx < MAX_BS_ELEMENT; ch_idx++) {
132 if (ptr_element_type[ch_idx] == 1) {
133 channel_mask += 0x30;
134 ptr_slot_element[ch_idx] = ixheaacd_drc_offset;
135 ixheaacd_drc_offset += 2;
136 flag1 = ch_idx + 1;
137 break;
138 }
139 }
140 for (ch_idx = flag2; ch_idx < MAX_BS_ELEMENT; ch_idx++) {
141 if (ptr_element_type[ch_idx] == 0) {
142 channel_mask += 0x100;
143 ptr_slot_element[ch_idx] = ixheaacd_drc_offset;
144 ixheaacd_drc_offset += 1;
145 break;
146 }
147 }
148 for (ch_idx = flag1; ch_idx < MAX_BS_ELEMENT; ch_idx++) {
149 if (ptr_element_type[ch_idx] == 1) {
150 {
151 channel_mask += (0x40 + 0x80);
152 ptr_slot_element[ch_idx] = ixheaacd_drc_offset;
153 ixheaacd_drc_offset += 2;
154 break;
155 }
156 }
157 }
158
159 return channel_mask;
160 }
161
ixheaacd_read_data_stream_element(ia_bit_buf_struct * it_bit_buff,WORD32 * byte_align_bits,ia_drc_dec_struct * drc_handle)162 VOID ixheaacd_read_data_stream_element(ia_bit_buf_struct *it_bit_buff,
163 WORD32 *byte_align_bits,
164 ia_drc_dec_struct *drc_handle) {
165 ia_bit_buf_struct temp_bs;
166 WORD32 count = ixheaacd_read_bits_buf(it_bit_buff, 13);
167 WORD32 cnt = (count & 0xff);
168 WORD32 start_pos = 0;
169
170 if (cnt == 255) {
171 cnt += ixheaacd_read_bits_buf(it_bit_buff, 8);
172 }
173
174 if ((count & 0x0100) >> 8) {
175 ixheaacd_byte_align(it_bit_buff, byte_align_bits);
176 }
177
178 {
179 memcpy(&temp_bs, it_bit_buff, sizeof(ia_bit_buf_struct));
180 start_pos = temp_bs.cnt_bits;
181
182 if (ixheaacd_read_bits_buf(&temp_bs, 8) == DVB_ANC_DATA_SYNC_BYTE) {
183 int dmx_level_present, compression_present;
184 int coarse_gain_present, fine_grain_present;
185
186 ixheaacd_read_bits_buf(&temp_bs, 8);
187
188 ixheaacd_read_bits_buf(&temp_bs, 3);
189 dmx_level_present = ixheaacd_read_bits_buf(&temp_bs, 1);
190 ixheaacd_read_bits_buf(&temp_bs, 1);
191 compression_present = ixheaacd_read_bits_buf(&temp_bs, 1);
192 coarse_gain_present = ixheaacd_read_bits_buf(&temp_bs, 1);
193 fine_grain_present = ixheaacd_read_bits_buf(&temp_bs, 1);
194
195 if (dmx_level_present) ixheaacd_read_bits_buf(&temp_bs, 8);
196
197 if (compression_present) ixheaacd_read_bits_buf(&temp_bs, 16);
198
199 if (coarse_gain_present) ixheaacd_read_bits_buf(&temp_bs, 16);
200
201 if (fine_grain_present) ixheaacd_read_bits_buf(&temp_bs, 16);
202
203 if (!drc_handle->dvb_anc_data_present && temp_bs.cnt_bits >= 0) {
204 drc_handle->dvb_anc_data_pos = start_pos;
205 drc_handle->dvb_anc_data_present = 1;
206 }
207 }
208 }
209
210 it_bit_buff->ptr_read_next += cnt;
211 it_bit_buff->cnt_bits -= ((cnt) << 3);
212
213 if (it_bit_buff->ptr_read_next > it_bit_buff->ptr_bit_buf_end) {
214 it_bit_buff->ptr_read_next = it_bit_buff->ptr_bit_buf_base;
215 }
216 }
217
ixheaacd_read_fill_element(ia_bit_buf_struct * it_bit_buff,ia_drc_dec_struct * drc_dummy,ia_drc_dec_struct * ptr_drc_dec)218 VOID ixheaacd_read_fill_element(ia_bit_buf_struct *it_bit_buff,
219 ia_drc_dec_struct *drc_dummy,
220 ia_drc_dec_struct *ptr_drc_dec) {
221 WORD32 count;
222 count = ixheaacd_read_bits_buf(it_bit_buff, 4);
223
224 if ((count - 15) == 0) {
225 count = ixheaacd_read_bits_buf(it_bit_buff, 8);
226 count = (count + 14);
227 }
228
229 if (count > 0) {
230 WORD32 extension_type;
231
232 extension_type = ixheaacd_read_bits_buf(it_bit_buff, 4);
233
234 if (extension_type == EXT_DYNAMIC_RANGE) {
235 ptr_drc_dec->drc_element_found = 1;
236 count -=
237 ixheaacd_dec_drc_read_element(ptr_drc_dec, drc_dummy, it_bit_buff);
238
239 } else {
240 ixheaacd_read_bits_buf(it_bit_buff, 4);
241
242 it_bit_buff->ptr_read_next += count - 1;
243 it_bit_buff->cnt_bits -= ((count - 1) << 3);
244
245 if (it_bit_buff->ptr_read_next > it_bit_buff->ptr_bit_buf_end) {
246 it_bit_buff->ptr_read_next = it_bit_buff->ptr_bit_buf_base;
247 }
248 }
249 }
250 }
251
ixheaacd_get_element_index_tag(ia_exhaacplus_dec_api_struct * p_obj_enhaacplus_dec,WORD ch_idx1,WORD * ch_idx,WORD * channel,WORD * ele_idx_order,WORD total_elements,WORD8 * element_used,WORD total_channels,ia_drc_dec_struct * pstr_drc_dec,ia_drc_dec_struct * drc_dummy)252 WORD32 ixheaacd_get_element_index_tag(
253 ia_exhaacplus_dec_api_struct *p_obj_enhaacplus_dec, WORD ch_idx1,
254 WORD *ch_idx, WORD *channel, WORD *ele_idx_order, WORD total_elements,
255 WORD8 *element_used, WORD total_channels, ia_drc_dec_struct *pstr_drc_dec,
256 ia_drc_dec_struct *drc_dummy) {
257 WORD element_tag, j;
258 ia_aac_dec_state_struct *p_state_enhaacplus_dec =
259 p_obj_enhaacplus_dec->p_state_aac;
260
261 ia_bit_buf_struct *it_bit_buff = p_state_enhaacplus_dec->ptr_bit_stream;
262 WORD element_idx;
263 WORD element_type;
264
265 ia_aac_decoder_struct *aac_dec_handle =
266 p_state_enhaacplus_dec->pstr_aac_dec_info[ch_idx1];
267
268 *ch_idx = ch_idx1;
269
270 if (p_state_enhaacplus_dec->bs_format != LOAS_BSFORMAT) {
271 if (ch_idx1 == 0) {
272 ixheaacd_byte_align(it_bit_buff, &aac_dec_handle->byte_align_bits);
273 }
274 }
275 {
276 if (ch_idx1 == 0) {
277 aac_dec_handle->byte_align_bits = it_bit_buff->cnt_bits;
278 }
279 }
280
281 if (it_bit_buff->cnt_bits < 3) {
282 it_bit_buff->cnt_bits = -1;
283 return (WORD16)(
284 (WORD32)IA_ENHAACPLUS_DEC_EXE_NONFATAL_INSUFFICIENT_INPUT_BYTES);
285 }
286
287 element_tag = (WORD)ixheaacd_read_bits_buf(it_bit_buff, 7);
288 ixheaacd_read_bidirection(it_bit_buff, -7);
289
290 element_idx = (element_tag & 0xF);
291 element_type = (element_tag >> 4) & 0x7;
292
293 p_obj_enhaacplus_dec->aac_config.str_prog_config.alignment_bits =
294 it_bit_buff->bit_pos;
295
296 while (element_type == 4 || element_type == 5 || element_type == 6) {
297 WORD type = (WORD)ixheaacd_read_bits_buf(it_bit_buff, 3);
298
299 if (it_bit_buff->cnt_bits < 3) {
300 it_bit_buff->cnt_bits = -1;
301 return (WORD16)(
302 (WORD32)IA_ENHAACPLUS_DEC_EXE_NONFATAL_INSUFFICIENT_INPUT_BYTES);
303 }
304
305 if (type == 4) {
306 ixheaacd_read_data_stream_element(
307 it_bit_buff, &aac_dec_handle->byte_align_bits, pstr_drc_dec);
308 }
309 if (type == 5) {
310 WORD32 error_code = 0;
311 error_code = ixheaacd_decode_pce(
312 it_bit_buff, &p_obj_enhaacplus_dec->aac_config.ui_pce_found_in_hdr,
313 &p_obj_enhaacplus_dec->aac_config.str_prog_config);
314 if (error_code != 0) {
315 if (it_bit_buff->cnt_bits < 0) {
316 return (WORD16)(
317 (WORD32)IA_ENHAACPLUS_DEC_EXE_NONFATAL_INSUFFICIENT_INPUT_BYTES);
318 }
319 return IA_ENHAACPLUS_DEC_EXE_NONFATAL_DECODE_FRAME_ERROR;
320 }
321 }
322 if (type == 6) {
323 ixheaacd_read_fill_element(it_bit_buff, drc_dummy, pstr_drc_dec);
324 }
325
326 if (it_bit_buff->cnt_bits < 7) {
327 it_bit_buff->cnt_bits = -1;
328 return (WORD16)(
329 (WORD32)IA_ENHAACPLUS_DEC_EXE_NONFATAL_INSUFFICIENT_INPUT_BYTES);
330 }
331
332 element_tag = (WORD)ixheaacd_aac_showbits_7(it_bit_buff);
333 element_idx = (element_tag & 0xF);
334 element_type = (element_tag >> 4) & 0x7;
335 }
336
337 if (total_elements == 2 && total_channels == 2 &&
338 p_state_enhaacplus_dec->p_config->ui_pce_found_in_hdr == 2 &&
339 ch_idx1 == 0) {
340 ixheaacd_fill_prog_config_slots(p_state_enhaacplus_dec);
341 }
342
343 *channel = 1;
344 if (element_type == 1) {
345 *channel = 2;
346 }
347
348 for (j = 0; j < total_elements; j++) {
349 if (p_obj_enhaacplus_dec->aac_config.element_type[j] == element_type &&
350 (element_idx == ele_idx_order[j]) && (element_used[j] == 0)) {
351 *ch_idx = j;
352 element_used[j] = 1;
353 break;
354 }
355 }
356
357 if (j == total_elements) {
358 if (it_bit_buff->cnt_bits < 0) {
359 return (WORD16)(
360 (WORD32)IA_ENHAACPLUS_DEC_EXE_NONFATAL_INSUFFICIENT_INPUT_BYTES);
361 }
362
363 ixheaacd_read_bidirection(
364 it_bit_buff, (WORD16)(it_bit_buff->cnt_bits - it_bit_buff->size));
365 return IA_ENHAACPLUS_DEC_EXE_NONFATAL_ELE_INSTANCE_TAG_NOT_FOUND;
366 } else
367 return 0;
368 }
369