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1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides AArch64 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64MCTargetDesc.h"
15 #include "AArch64ELFStreamer.h"
16 #include "AArch64MCAsmInfo.h"
17 #include "InstPrinter/AArch64InstPrinter.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
24 
25 using namespace llvm;
26 
27 #define GET_INSTRINFO_MC_DESC
28 #include "AArch64GenInstrInfo.inc"
29 
30 #define GET_SUBTARGETINFO_MC_DESC
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 #define GET_REGINFO_MC_DESC
34 #include "AArch64GenRegisterInfo.inc"
35 
createAArch64MCInstrInfo()36 static MCInstrInfo *createAArch64MCInstrInfo() {
37   MCInstrInfo *X = new MCInstrInfo();
38   InitAArch64MCInstrInfo(X);
39   return X;
40 }
41 
42 static MCSubtargetInfo *
createAArch64MCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)43 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
44   if (CPU.empty())
45     CPU = "generic";
46 
47   return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
48 }
49 
createAArch64MCRegisterInfo(const Triple & Triple)50 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
51   MCRegisterInfo *X = new MCRegisterInfo();
52   InitAArch64MCRegisterInfo(X, AArch64::LR);
53   return X;
54 }
55 
createAArch64MCAsmInfo(const MCRegisterInfo & MRI,const Triple & TheTriple)56 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
57                                          const Triple &TheTriple) {
58   MCAsmInfo *MAI;
59   if (TheTriple.isOSBinFormatMachO())
60     MAI = new AArch64MCAsmInfoDarwin();
61   else {
62     assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF");
63     MAI = new AArch64MCAsmInfoELF(TheTriple);
64   }
65 
66   // Initial state of the frame pointer is SP.
67   unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
68   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
69   MAI->addInitialFrameState(Inst);
70 
71   return MAI;
72 }
73 
adjustCodeGenOpts(const Triple & TT,Reloc::Model RM,CodeModel::Model & CM)74 static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
75                               CodeModel::Model &CM) {
76   assert((TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()) &&
77          "Only expect Darwin and ELF targets");
78 
79   if (CM == CodeModel::Default)
80     CM = CodeModel::Small;
81   // The default MCJIT memory managers make no guarantees about where they can
82   // find an executable page; JITed code needs to be able to refer to globals
83   // no matter how far away they are.
84   else if (CM == CodeModel::JITDefault)
85     CM = CodeModel::Large;
86   else if (CM != CodeModel::Small && CM != CodeModel::Large)
87     report_fatal_error(
88         "Only small and large code models are allowed on AArch64");
89 }
90 
createAArch64MCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)91 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
92                                                  unsigned SyntaxVariant,
93                                                  const MCAsmInfo &MAI,
94                                                  const MCInstrInfo &MII,
95                                                  const MCRegisterInfo &MRI) {
96   if (SyntaxVariant == 0)
97     return new AArch64InstPrinter(MAI, MII, MRI);
98   if (SyntaxVariant == 1)
99     return new AArch64AppleInstPrinter(MAI, MII, MRI);
100 
101   return nullptr;
102 }
103 
createELFStreamer(const Triple & T,MCContext & Ctx,MCAsmBackend & TAB,raw_pwrite_stream & OS,MCCodeEmitter * Emitter,bool RelaxAll)104 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
105                                      MCAsmBackend &TAB, raw_pwrite_stream &OS,
106                                      MCCodeEmitter *Emitter, bool RelaxAll) {
107   return createAArch64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
108 }
109 
createMachOStreamer(MCContext & Ctx,MCAsmBackend & TAB,raw_pwrite_stream & OS,MCCodeEmitter * Emitter,bool RelaxAll,bool DWARFMustBeAtTheEnd)110 static MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
111                                        raw_pwrite_stream &OS,
112                                        MCCodeEmitter *Emitter, bool RelaxAll,
113                                        bool DWARFMustBeAtTheEnd) {
114   return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
115                              DWARFMustBeAtTheEnd,
116                              /*LabelSections*/ true);
117 }
118 
119 // Force static initialization.
LLVMInitializeAArch64TargetMC()120 extern "C" void LLVMInitializeAArch64TargetMC() {
121   for (Target *T :
122        {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) {
123     // Register the MC asm info.
124     RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
125 
126     // Register the MC codegen info.
127     TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts);
128 
129     // Register the MC instruction info.
130     TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
131 
132     // Register the MC register info.
133     TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
134 
135     // Register the MC subtarget info.
136     TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
137 
138     // Register the MC Code Emitter
139     TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
140 
141     // Register the obj streamers.
142     TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
143     TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
144 
145     // Register the obj target streamer.
146     TargetRegistry::RegisterObjectTargetStreamer(
147         *T, createAArch64ObjectTargetStreamer);
148 
149     // Register the asm streamer.
150     TargetRegistry::RegisterAsmTargetStreamer(*T,
151                                               createAArch64AsmTargetStreamer);
152     // Register the MCInstPrinter.
153     TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
154   }
155 
156   // Register the asm backend.
157   for (Target *T : {&TheAArch64leTarget, &TheARM64Target})
158     TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
159   TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget,
160                                        createAArch64beAsmBackend);
161 }
162