1//===- HexagonImmediates.td - Hexagon immediate processing -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illnois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10def s32ImmOperand : AsmOperandClass { let Name = "s32Imm"; } 11def s23_2ImmOperand : AsmOperandClass { let Name = "s23_2Imm"; } 12def s8ImmOperand : AsmOperandClass { let Name = "s8Imm"; } 13def s8Imm64Operand : AsmOperandClass { let Name = "s8Imm64"; } 14def s6ImmOperand : AsmOperandClass { let Name = "s6Imm"; } 15def s4ImmOperand : AsmOperandClass { let Name = "s4Imm"; } 16def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; } 17def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; } 18def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; } 19def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; } 20def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; } 21def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; } 22def u64ImmOperand : AsmOperandClass { let Name = "u64Imm"; } 23def u32ImmOperand : AsmOperandClass { let Name = "u32Imm"; } 24def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; } 25def u16ImmOperand : AsmOperandClass { let Name = "u16Imm"; } 26def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; } 27def u16_1ImmOperand : AsmOperandClass { let Name = "u16_1Imm"; } 28def u16_2ImmOperand : AsmOperandClass { let Name = "u16_2Imm"; } 29def u16_3ImmOperand : AsmOperandClass { let Name = "u16_3Imm"; } 30def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; } 31def u10ImmOperand : AsmOperandClass { let Name = "u10Imm"; } 32def u9ImmOperand : AsmOperandClass { let Name = "u9Imm"; } 33def u8ImmOperand : AsmOperandClass { let Name = "u8Imm"; } 34def u7ImmOperand : AsmOperandClass { let Name = "u7Imm"; } 35def u6ImmOperand : AsmOperandClass { let Name = "u6Imm"; } 36def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; } 37def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; } 38def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; } 39def u6_3ImmOperand : AsmOperandClass { let Name = "u6_3Imm"; } 40def u5ImmOperand : AsmOperandClass { let Name = "u5Imm"; } 41def u4ImmOperand : AsmOperandClass { let Name = "u4Imm"; } 42def u3ImmOperand : AsmOperandClass { let Name = "u3Imm"; } 43def u2ImmOperand : AsmOperandClass { let Name = "u2Imm"; } 44def u1ImmOperand : AsmOperandClass { let Name = "u1Imm"; } 45def n8ImmOperand : AsmOperandClass { let Name = "n8Imm"; } 46// Immediate operands. 47 48let OperandType = "OPERAND_IMMEDIATE", 49 DecoderMethod = "unsignedImmDecoder" in { 50 def s32Imm : Operand<i32> { let ParserMatchClass = s32ImmOperand; 51 let DecoderMethod = "s32ImmDecoder"; } 52 def s23_2Imm : Operand<i32> { let ParserMatchClass = s23_2ImmOperand; } 53 def s8Imm : Operand<i32> { let ParserMatchClass = s8ImmOperand; 54 let DecoderMethod = "s8ImmDecoder"; } 55 def s8Imm64 : Operand<i64> { let ParserMatchClass = s8Imm64Operand; 56 let DecoderMethod = "s8ImmDecoder"; } 57 def s6Imm : Operand<i32> { let ParserMatchClass = s6ImmOperand; 58 let DecoderMethod = "s6_0ImmDecoder"; } 59 def s6_3Imm : Operand<i32>; 60 def s4Imm : Operand<i32> { let ParserMatchClass = s4ImmOperand; 61 let DecoderMethod = "s4_0ImmDecoder"; } 62 def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; 63 let DecoderMethod = "s4_0ImmDecoder"; } 64 def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; 65 let DecoderMethod = "s4_1ImmDecoder"; } 66 def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; 67 let DecoderMethod = "s4_2ImmDecoder"; } 68 def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; 69 let DecoderMethod = "s4_3ImmDecoder"; } 70 def u64Imm : Operand<i64> { let ParserMatchClass = u64ImmOperand; } 71 def u32Imm : Operand<i32> { let ParserMatchClass = u32ImmOperand; } 72 def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; } 73 def u16Imm : Operand<i32> { let ParserMatchClass = u16ImmOperand; } 74 def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; } 75 def u16_1Imm : Operand<i32> { let ParserMatchClass = u16_1ImmOperand; } 76 def u16_2Imm : Operand<i32> { let ParserMatchClass = u16_2ImmOperand; } 77 def u16_3Imm : Operand<i32> { let ParserMatchClass = u16_3ImmOperand; } 78 def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; } 79 def u10Imm : Operand<i32> { let ParserMatchClass = u10ImmOperand; } 80 def u9Imm : Operand<i32> { let ParserMatchClass = u9ImmOperand; } 81 def u8Imm : Operand<i32> { let ParserMatchClass = u8ImmOperand; } 82 def u7Imm : Operand<i32> { let ParserMatchClass = u7ImmOperand; } 83 def u6Imm : Operand<i32> { let ParserMatchClass = u6ImmOperand; } 84 def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; } 85 def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; } 86 def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; } 87 def u6_3Imm : Operand<i32> { let ParserMatchClass = u6_3ImmOperand; } 88 def u5Imm : Operand<i32> { let ParserMatchClass = u5ImmOperand; } 89 def u5_0Imm : Operand<i32>; 90 def u5_1Imm : Operand<i32>; 91 def u5_2Imm : Operand<i32>; 92 def u5_3Imm : Operand<i32>; 93 def u4Imm : Operand<i32> { let ParserMatchClass = u4ImmOperand; } 94 def u4_0Imm : Operand<i32>; 95 def u4_1Imm : Operand<i32>; 96 def u4_2Imm : Operand<i32>; 97 def u4_3Imm : Operand<i32>; 98 def u3Imm : Operand<i32> { let ParserMatchClass = u3ImmOperand; } 99 def u3_0Imm : Operand<i32>; 100 def u3_1Imm : Operand<i32>; 101 def u3_2Imm : Operand<i32>; 102 def u3_3Imm : Operand<i32>; 103 def u2Imm : Operand<i32> { let ParserMatchClass = u2ImmOperand; } 104 def u1Imm : Operand<i32> { let ParserMatchClass = u1ImmOperand; } 105 def n8Imm : Operand<i32> { let ParserMatchClass = n8ImmOperand; } 106} 107 108let OperandType = "OPERAND_IMMEDIATE" in { 109 def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand; 110 let PrintMethod = "prints4_6ImmOperand"; 111 let DecoderMethod = "s4_6ImmDecoder";} 112 def s4_7Imm : Operand<i32> { let PrintMethod = "prints4_7ImmOperand"; 113 let DecoderMethod = "s4_6ImmDecoder";} 114 def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand; 115 let PrintMethod = "prints3_6ImmOperand"; 116 let DecoderMethod = "s3_6ImmDecoder";} 117 def s3_7Imm : Operand<i32> { let PrintMethod = "prints3_7ImmOperand"; 118 let DecoderMethod = "s3_6ImmDecoder";} 119} 120 121// 122// Immediate predicates 123// 124def s32ImmPred : PatLeaf<(i32 imm), [{ 125 int64_t v = (int64_t)N->getSExtValue(); 126 return isInt<32>(v); 127}]>; 128 129def s32_0ImmPred : PatLeaf<(i32 imm), [{ 130 int64_t v = (int64_t)N->getSExtValue(); 131 return isInt<32>(v); 132}]>; 133 134def s31_1ImmPred : PatLeaf<(i32 imm), [{ 135 int64_t v = (int64_t)N->getSExtValue(); 136 return isShiftedInt<31,1>(v); 137}]>; 138 139def s30_2ImmPred : PatLeaf<(i32 imm), [{ 140 int64_t v = (int64_t)N->getSExtValue(); 141 return isShiftedInt<30,2>(v); 142}]>; 143 144def s29_3ImmPred : PatLeaf<(i32 imm), [{ 145 int64_t v = (int64_t)N->getSExtValue(); 146 return isShiftedInt<29,3>(v); 147}]>; 148 149def s16ImmPred : PatLeaf<(i32 imm), [{ 150 int64_t v = (int64_t)N->getSExtValue(); 151 return isInt<16>(v); 152}]>; 153 154def s11_0ImmPred : PatLeaf<(i32 imm), [{ 155 int64_t v = (int64_t)N->getSExtValue(); 156 return isInt<11>(v); 157}]>; 158 159def s11_1ImmPred : PatLeaf<(i32 imm), [{ 160 int64_t v = (int64_t)N->getSExtValue(); 161 return isShiftedInt<11,1>(v); 162}]>; 163 164def s11_2ImmPred : PatLeaf<(i32 imm), [{ 165 int64_t v = (int64_t)N->getSExtValue(); 166 return isShiftedInt<11,2>(v); 167}]>; 168 169def s11_3ImmPred : PatLeaf<(i32 imm), [{ 170 int64_t v = (int64_t)N->getSExtValue(); 171 return isShiftedInt<11,3>(v); 172}]>; 173 174def s10ImmPred : PatLeaf<(i32 imm), [{ 175 int64_t v = (int64_t)N->getSExtValue(); 176 return isInt<10>(v); 177}]>; 178 179def s8ImmPred : PatLeaf<(i32 imm), [{ 180 int64_t v = (int64_t)N->getSExtValue(); 181 return isInt<8>(v); 182}]>; 183 184def s8Imm64Pred : PatLeaf<(i64 imm), [{ 185 int64_t v = (int64_t)N->getSExtValue(); 186 return isInt<8>(v); 187}]>; 188 189def s6ImmPred : PatLeaf<(i32 imm), [{ 190 int64_t v = (int64_t)N->getSExtValue(); 191 return isInt<6>(v); 192}]>; 193 194def s4_0ImmPred : PatLeaf<(i32 imm), [{ 195 int64_t v = (int64_t)N->getSExtValue(); 196 return isInt<4>(v); 197}]>; 198 199def s4_1ImmPred : PatLeaf<(i32 imm), [{ 200 int64_t v = (int64_t)N->getSExtValue(); 201 return isShiftedInt<4,1>(v); 202}]>; 203 204def s4_2ImmPred : PatLeaf<(i32 imm), [{ 205 int64_t v = (int64_t)N->getSExtValue(); 206 return isShiftedInt<4,2>(v); 207}]>; 208 209def s4_3ImmPred : PatLeaf<(i32 imm), [{ 210 int64_t v = (int64_t)N->getSExtValue(); 211 return isShiftedInt<4,3>(v); 212}]>; 213 214def u64ImmPred : PatLeaf<(i64 imm), [{ 215 // Adding "N ||" to suppress gcc unused warning. 216 return (N || true); 217}]>; 218 219def u32ImmPred : PatLeaf<(i32 imm), [{ 220 int64_t v = (int64_t)N->getSExtValue(); 221 return isUInt<32>(v); 222}]>; 223 224def u32_0ImmPred : PatLeaf<(i32 imm), [{ 225 int64_t v = (int64_t)N->getSExtValue(); 226 return isUInt<32>(v); 227}]>; 228 229def u31_1ImmPred : PatLeaf<(i32 imm), [{ 230 int64_t v = (int64_t)N->getSExtValue(); 231 return isShiftedUInt<31,1>(v); 232}]>; 233 234def u30_2ImmPred : PatLeaf<(i32 imm), [{ 235 int64_t v = (int64_t)N->getSExtValue(); 236 return isShiftedUInt<30,2>(v); 237}]>; 238 239def u29_3ImmPred : PatLeaf<(i32 imm), [{ 240 int64_t v = (int64_t)N->getSExtValue(); 241 return isShiftedUInt<29,3>(v); 242}]>; 243 244def u26_6ImmPred : PatLeaf<(i32 imm), [{ 245 int64_t v = (int64_t)N->getSExtValue(); 246 return isShiftedUInt<26,6>(v); 247}]>; 248 249def u16_0ImmPred : PatLeaf<(i32 imm), [{ 250 int64_t v = (int64_t)N->getSExtValue(); 251 return isUInt<16>(v); 252}]>; 253 254def u16_1ImmPred : PatLeaf<(i32 imm), [{ 255 int64_t v = (int64_t)N->getSExtValue(); 256 return isShiftedUInt<16,1>(v); 257}]>; 258 259def u16_2ImmPred : PatLeaf<(i32 imm), [{ 260 int64_t v = (int64_t)N->getSExtValue(); 261 return isShiftedUInt<16,2>(v); 262}]>; 263 264def u11_3ImmPred : PatLeaf<(i32 imm), [{ 265 int64_t v = (int64_t)N->getSExtValue(); 266 return isShiftedUInt<11,3>(v); 267}]>; 268 269def u10ImmPred : PatLeaf<(i32 imm), [{ 270 int64_t v = (int64_t)N->getSExtValue(); 271 return isUInt<10>(v); 272}]>; 273 274def u9ImmPred : PatLeaf<(i32 imm), [{ 275 int64_t v = (int64_t)N->getSExtValue(); 276 return isUInt<9>(v); 277}]>; 278 279def u8ImmPred : PatLeaf<(i32 imm), [{ 280 int64_t v = (int64_t)N->getSExtValue(); 281 return isUInt<8>(v); 282}]>; 283 284def u7StrictPosImmPred : ImmLeaf<i32, [{ 285 // u7StrictPosImmPred predicate - True if the immediate fits in an 7-bit 286 // unsigned field and is strictly greater than 0. 287 return isUInt<7>(Imm) && Imm > 0; 288}]>; 289 290def u7ImmPred : PatLeaf<(i32 imm), [{ 291 int64_t v = (int64_t)N->getSExtValue(); 292 return isUInt<7>(v); 293}]>; 294 295def u6ImmPred : PatLeaf<(i32 imm), [{ 296 int64_t v = (int64_t)N->getSExtValue(); 297 return isUInt<6>(v); 298}]>; 299 300def u6_0ImmPred : PatLeaf<(i32 imm), [{ 301 int64_t v = (int64_t)N->getSExtValue(); 302 return isUInt<6>(v); 303}]>; 304 305def u6_1ImmPred : PatLeaf<(i32 imm), [{ 306 int64_t v = (int64_t)N->getSExtValue(); 307 return isShiftedUInt<6,1>(v); 308}]>; 309 310def u6_2ImmPred : PatLeaf<(i32 imm), [{ 311 int64_t v = (int64_t)N->getSExtValue(); 312 return isShiftedUInt<6,2>(v); 313}]>; 314 315def u6_3ImmPred : PatLeaf<(i32 imm), [{ 316 int64_t v = (int64_t)N->getSExtValue(); 317 return isShiftedUInt<6,3>(v); 318}]>; 319 320def u5ImmPred : PatLeaf<(i32 imm), [{ 321 int64_t v = (int64_t)N->getSExtValue(); 322 return isUInt<5>(v); 323}]>; 324 325def u4ImmPred : PatLeaf<(i32 imm), [{ 326 int64_t v = (int64_t)N->getSExtValue(); 327 return isUInt<4>(v); 328}]>; 329 330def u3ImmPred : PatLeaf<(i32 imm), [{ 331 int64_t v = (int64_t)N->getSExtValue(); 332 return isUInt<3>(v); 333}]>; 334 335def u2ImmPred : PatLeaf<(i32 imm), [{ 336 int64_t v = (int64_t)N->getSExtValue(); 337 return isUInt<2>(v); 338}]>; 339 340def u1ImmPred : PatLeaf<(i1 imm), [{ 341 int64_t v = (int64_t)N->getSExtValue(); 342 return isUInt<1>(v); 343}]>; 344 345def u1ImmPred32 : PatLeaf<(i32 imm), [{ 346 int64_t v = (int64_t)N->getSExtValue(); 347 return isUInt<1>(v); 348}]>; 349 350def m5BImmPred : PatLeaf<(i32 imm), [{ 351 // m5BImmPred predicate - True if the (char) number is in range -1 .. -31 352 // and will fit in a 5 bit field when made positive, for use in memops. 353 // this is specific to the zero extending of a negative by CombineInstr 354 int8_t v = (int8_t)N->getSExtValue(); 355 return (-31 <= v && v <= -1); 356}]>; 357 358def m5HImmPred : PatLeaf<(i32 imm), [{ 359 // m5HImmPred predicate - True if the (short) number is in range -1 .. -31 360 // and will fit in a 5 bit field when made positive, for use in memops. 361 // this is specific to the zero extending of a negative by CombineInstr 362 int16_t v = (int16_t)N->getSExtValue(); 363 return (-31 <= v && v <= -1); 364}]>; 365 366def m5ImmPred : PatLeaf<(i32 imm), [{ 367 // m5ImmPred predicate - True if the number is in range -1 .. -31 368 // and will fit in a 5 bit field when made positive, for use in memops. 369 int64_t v = (int64_t)N->getSExtValue(); 370 return (-31 <= v && v <= -1); 371}]>; 372 373//InN means negative integers in [-(2^N - 1), 0] 374def n8ImmPred : PatLeaf<(i32 imm), [{ 375 // n8ImmPred predicate - True if the immediate fits in a 8-bit signed 376 // field. 377 int64_t v = (int64_t)N->getSExtValue(); 378 return (-255 <= v && v <= 0); 379}]>; 380 381def nOneImmPred : PatLeaf<(i32 imm), [{ 382 // nOneImmPred predicate - True if the immediate is -1. 383 int64_t v = (int64_t)N->getSExtValue(); 384 return (-1 == v); 385}]>; 386 387def Set5ImmPred : PatLeaf<(i32 imm), [{ 388 // Set5ImmPred predicate - True if the number is in the series of values. 389 // [ 2^0, 2^1, ... 2^31 ] 390 // For use in setbit immediate. 391 uint32_t v = (int32_t)N->getSExtValue(); 392 // Constrain to 32 bits, and then check for single bit. 393 return ImmIsSingleBit(v); 394}]>; 395 396def Clr5ImmPred : PatLeaf<(i32 imm), [{ 397 // Clr5ImmPred predicate - True if the number is in the series of 398 // bit negated values. 399 // [ 2^0, 2^1, ... 2^31 ] 400 // For use in clrbit immediate. 401 // Note: we are bit NOTing the value. 402 uint32_t v = ~ (int32_t)N->getSExtValue(); 403 // Constrain to 32 bits, and then check for single bit. 404 return ImmIsSingleBit(v); 405}]>; 406 407def SetClr5ImmPred : PatLeaf<(i32 imm), [{ 408 // True if the immediate is in range 0..31. 409 int32_t v = (int32_t)N->getSExtValue(); 410 return (v >= 0 && v <= 31); 411}]>; 412 413def Set4ImmPred : PatLeaf<(i32 imm), [{ 414 // Set4ImmPred predicate - True if the number is in the series of values: 415 // [ 2^0, 2^1, ... 2^15 ]. 416 // For use in setbit immediate. 417 uint16_t v = (int16_t)N->getSExtValue(); 418 // Constrain to 16 bits, and then check for single bit. 419 return ImmIsSingleBit(v); 420}]>; 421 422def Clr4ImmPred : PatLeaf<(i32 imm), [{ 423 // Clr4ImmPred predicate - True if the number is in the series of 424 // bit negated values: 425 // [ 2^0, 2^1, ... 2^15 ]. 426 // For use in setbit and clrbit immediate. 427 uint16_t v = ~ (int16_t)N->getSExtValue(); 428 // Constrain to 16 bits, and then check for single bit. 429 return ImmIsSingleBit(v); 430}]>; 431 432def SetClr4ImmPred : PatLeaf<(i32 imm), [{ 433 // True if the immediate is in the range 0..15. 434 int16_t v = (int16_t)N->getSExtValue(); 435 return (v >= 0 && v <= 15); 436}]>; 437 438def Set3ImmPred : PatLeaf<(i32 imm), [{ 439 // True if the number is in the series of values: [ 2^0, 2^1, ... 2^7 ]. 440 // For use in setbit immediate. 441 uint8_t v = (int8_t)N->getSExtValue(); 442 // Constrain to 8 bits, and then check for single bit. 443 return ImmIsSingleBit(v); 444}]>; 445 446def Clr3ImmPred : PatLeaf<(i32 imm), [{ 447 // True if the number is in the series of bit negated values: [ 2^0, 2^1, ... 2^7 ]. 448 // For use in setbit and clrbit immediate. 449 uint8_t v = ~ (int8_t)N->getSExtValue(); 450 // Constrain to 8 bits, and then check for single bit. 451 return ImmIsSingleBit(v); 452}]>; 453 454def SetClr3ImmPred : PatLeaf<(i32 imm), [{ 455 // True if the immediate is in the range 0..7. 456 int8_t v = (int8_t)N->getSExtValue(); 457 return (v >= 0 && v <= 7); 458}]>; 459 460 461// Extendable immediate operands. 462def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; } 463def s16ExtOperand : AsmOperandClass { let Name = "s16Ext"; } 464def s12ExtOperand : AsmOperandClass { let Name = "s12Ext"; } 465def s10ExtOperand : AsmOperandClass { let Name = "s10Ext"; } 466def s9ExtOperand : AsmOperandClass { let Name = "s9Ext"; } 467def s8ExtOperand : AsmOperandClass { let Name = "s8Ext"; } 468def s7ExtOperand : AsmOperandClass { let Name = "s7Ext"; } 469def s6ExtOperand : AsmOperandClass { let Name = "s6Ext"; } 470def s11_0ExtOperand : AsmOperandClass { let Name = "s11_0Ext"; } 471def s11_1ExtOperand : AsmOperandClass { let Name = "s11_1Ext"; } 472def s11_2ExtOperand : AsmOperandClass { let Name = "s11_2Ext"; } 473def s11_3ExtOperand : AsmOperandClass { let Name = "s11_3Ext"; } 474def u6ExtOperand : AsmOperandClass { let Name = "u6Ext"; } 475def u7ExtOperand : AsmOperandClass { let Name = "u7Ext"; } 476def u8ExtOperand : AsmOperandClass { let Name = "u8Ext"; } 477def u9ExtOperand : AsmOperandClass { let Name = "u9Ext"; } 478def u10ExtOperand : AsmOperandClass { let Name = "u10Ext"; } 479def u6_0ExtOperand : AsmOperandClass { let Name = "u6_0Ext"; } 480def u6_1ExtOperand : AsmOperandClass { let Name = "u6_1Ext"; } 481def u6_2ExtOperand : AsmOperandClass { let Name = "u6_2Ext"; } 482def u6_3ExtOperand : AsmOperandClass { let Name = "u6_3Ext"; } 483def u32MustExtOperand : AsmOperandClass { let Name = "u32MustExt"; } 484 485 486 487let OperandType = "OPERAND_IMMEDIATE", PrintMethod = "printExtOperand", 488 DecoderMethod = "unsignedImmDecoder" in { 489 def f32Ext : Operand<f32> { let ParserMatchClass = f32ExtOperand; } 490 def s16Ext : Operand<i32> { let ParserMatchClass = s16ExtOperand; 491 let DecoderMethod = "s16ImmDecoder"; } 492 def s12Ext : Operand<i32> { let ParserMatchClass = s12ExtOperand; 493 let DecoderMethod = "s12ImmDecoder"; } 494 def s11_0Ext : Operand<i32> { let ParserMatchClass = s11_0ExtOperand; 495 let DecoderMethod = "s11_0ImmDecoder"; } 496 def s11_1Ext : Operand<i32> { let ParserMatchClass = s11_1ExtOperand; 497 let DecoderMethod = "s11_1ImmDecoder"; } 498 def s11_2Ext : Operand<i32> { let ParserMatchClass = s11_2ExtOperand; 499 let DecoderMethod = "s11_2ImmDecoder"; } 500 def s11_3Ext : Operand<i32> { let ParserMatchClass = s11_3ExtOperand; 501 let DecoderMethod = "s11_3ImmDecoder"; } 502 def s10Ext : Operand<i32> { let ParserMatchClass = s10ExtOperand; 503 let DecoderMethod = "s10ImmDecoder"; } 504 def s9Ext : Operand<i32> { let ParserMatchClass = s9ExtOperand; 505 let DecoderMethod = "s90ImmDecoder"; } 506 def s8Ext : Operand<i32> { let ParserMatchClass = s8ExtOperand; 507 let DecoderMethod = "s8ImmDecoder"; } 508 def s7Ext : Operand<i32> { let ParserMatchClass = s7ExtOperand; } 509 def s6Ext : Operand<i32> { let ParserMatchClass = s6ExtOperand; 510 let DecoderMethod = "s6_0ImmDecoder"; } 511 def u6Ext : Operand<i32> { let ParserMatchClass = u6ExtOperand; } 512 def u7Ext : Operand<i32> { let ParserMatchClass = u7ExtOperand; } 513 def u8Ext : Operand<i32> { let ParserMatchClass = u8ExtOperand; } 514 def u9Ext : Operand<i32> { let ParserMatchClass = u9ExtOperand; } 515 def u10Ext : Operand<i32> { let ParserMatchClass = u10ExtOperand; } 516 def u6_0Ext : Operand<i32> { let ParserMatchClass = u6_0ExtOperand; } 517 def u6_1Ext : Operand<i32> { let ParserMatchClass = u6_1ExtOperand; } 518 def u6_2Ext : Operand<i32> { let ParserMatchClass = u6_2ExtOperand; } 519 def u6_3Ext : Operand<i32> { let ParserMatchClass = u6_3ExtOperand; } 520 def u32MustExt : Operand<i32> { let ParserMatchClass = u32MustExtOperand; } 521} 522 523 524def s4_7ImmPred : PatLeaf<(i32 imm), [{ 525 int64_t v = (int64_t)N->getSExtValue(); 526 if (HST->hasV60TOps()) 527 // Return true if the immediate can fit in a 10-bit sign extended field and 528 // is 128-byte aligned. 529 return isShiftedInt<4,7>(v); 530 return false; 531}]>; 532 533def s3_7ImmPred : PatLeaf<(i32 imm), [{ 534 int64_t v = (int64_t)N->getSExtValue(); 535 if (HST->hasV60TOps()) 536 // Return true if the immediate can fit in a 9-bit sign extended field and 537 // is 128-byte aligned. 538 return isShiftedInt<3,7>(v); 539 return false; 540}]>; 541 542def s4_6ImmPred : PatLeaf<(i32 imm), [{ 543 int64_t v = (int64_t)N->getSExtValue(); 544 if (HST->hasV60TOps()) 545 // Return true if the immediate can fit in a 10-bit sign extended field and 546 // is 64-byte aligned. 547 return isShiftedInt<4,6>(v); 548 return false; 549}]>; 550 551def s3_6ImmPred : PatLeaf<(i32 imm), [{ 552 int64_t v = (int64_t)N->getSExtValue(); 553 if (HST->hasV60TOps()) 554 // Return true if the immediate can fit in a 9-bit sign extended field and 555 // is 64-byte aligned. 556 return isShiftedInt<3,6>(v); 557 return false; 558}]>; 559 560 561// This complex pattern exists only to create a machine instruction operand 562// of type "frame index". There doesn't seem to be a way to do that directly 563// in the patterns. 564def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; 565 566// These complex patterns are not strictly necessary, since global address 567// folding will happen during DAG combining. For distinguishing between GA 568// and GP, pat frags with HexagonCONST32 and HexagonCONST32_GP can be used. 569def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>; 570def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>; 571 572// Address operands. 573 574let PrintMethod = "printGlobalOperand" in { 575 def globaladdress : Operand<i32>; 576 def globaladdressExt : Operand<i32>; 577} 578 579let PrintMethod = "printJumpTable" in 580def jumptablebase : Operand<i32>; 581 582def brtarget : Operand<OtherVT> { 583 let DecoderMethod = "brtargetDecoder"; 584 let PrintMethod = "printBrtarget"; 585} 586def brtargetExt : Operand<OtherVT> { 587 let DecoderMethod = "brtargetDecoder"; 588 let PrintMethod = "printBrtarget"; 589} 590def calltarget : Operand<i32> { 591 let DecoderMethod = "brtargetDecoder"; 592 let PrintMethod = "printBrtarget"; 593} 594 595def bblabel : Operand<i32>; 596def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">; 597 598// Return true if for a 32 to 64-bit sign-extended load. 599def is_sext_i32 : PatLeaf<(i64 DoubleRegs:$src1), [{ 600 LoadSDNode *LD = dyn_cast<LoadSDNode>(N); 601 if (!LD) 602 return false; 603 return LD->getExtensionType() == ISD::SEXTLOAD && 604 LD->getMemoryVT().getScalarType() == MVT::i32; 605}]>; 606