1//===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Class definitions 12//===----------------------------------------------------------------------===// 13 14class ImmediateAsmOperand<string name> 15 : AsmOperandClass { 16 let Name = name; 17 let RenderMethod = "addImmOperands"; 18} 19class ImmediateTLSAsmOperand<string name> 20 : AsmOperandClass { 21 let Name = name; 22 let RenderMethod = "addImmTLSOperands"; 23} 24 25// Constructs both a DAG pattern and instruction operand for an immediate 26// of type VT. PRED returns true if a node is acceptable and XFORM returns 27// the operand value associated with the node. ASMOP is the name of the 28// associated asm operand, and also forms the basis of the asm print method. 29class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop> 30 : PatLeaf<(vt imm), pred, xform>, Operand<vt> { 31 let PrintMethod = "print"##asmop##"Operand"; 32 let DecoderMethod = "decode"##asmop##"Operand"; 33 let ParserMatchClass = !cast<AsmOperandClass>(asmop); 34} 35 36// Constructs an asm operand for a PC-relative address. SIZE says how 37// many bits there are. 38class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> { 39 let PredicateMethod = "isImm"; 40 let ParserMethod = "parsePCRel"##size; 41} 42class PCRelTLSAsmOperand<string size> 43 : ImmediateTLSAsmOperand<"PCRelTLS"##size> { 44 let PredicateMethod = "isImmTLS"; 45 let ParserMethod = "parsePCRelTLS"##size; 46} 47 48// Constructs an operand for a PC-relative address with address type VT. 49// ASMOP is the associated asm operand. 50class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> { 51 let PrintMethod = "printPCRelOperand"; 52 let ParserMatchClass = asmop; 53} 54class PCRelTLSOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> { 55 let PrintMethod = "printPCRelTLSOperand"; 56 let ParserMatchClass = asmop; 57} 58 59// Constructs both a DAG pattern and instruction operand for a PC-relative 60// address with address size VT. SELF is the name of the operand and 61// ASMOP is the associated asm operand. 62class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop> 63 : ComplexPattern<vt, 1, "selectPCRelAddress", 64 [z_pcrel_wrapper, z_pcrel_offset]>, 65 PCRelOperand<vt, asmop> { 66 let MIOperandInfo = (ops !cast<Operand>(self)); 67} 68 69// Constructs an AsmOperandClass for addressing mode FORMAT, treating the 70// registers as having BITSIZE bits and displacements as having DISPSIZE bits. 71// LENGTH is "LenN" for addresses with an N-bit length field, otherwise it 72// is "". 73class AddressAsmOperand<string format, string bitsize, string dispsize, 74 string length = ""> 75 : AsmOperandClass { 76 let Name = format##bitsize##"Disp"##dispsize##length; 77 let ParserMethod = "parse"##format##bitsize; 78 let RenderMethod = "add"##format##"Operands"; 79} 80 81// Constructs an instruction operand for an addressing mode. FORMAT, 82// BITSIZE, DISPSIZE and LENGTH are the parameters to an associated 83// AddressAsmOperand. OPERANDS is a list of individual operands 84// (base register, displacement, etc.). 85class AddressOperand<string bitsize, string dispsize, string length, 86 string format, dag operands> 87 : Operand<!cast<ValueType>("i"##bitsize)> { 88 let PrintMethod = "print"##format##"Operand"; 89 let EncoderMethod = "get"##format##dispsize##length##"Encoding"; 90 let DecoderMethod = 91 "decode"##format##bitsize##"Disp"##dispsize##length##"Operand"; 92 let MIOperandInfo = operands; 93 let ParserMatchClass = 94 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length); 95} 96 97// Constructs both a DAG pattern and instruction operand for an addressing mode. 98// FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated 99// AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands 100// (base register, displacement, etc.). SELTYPE is the type of the memory 101// operand for selection purposes; sometimes we want different selection 102// choices for the same underlying addressing mode. SUFFIX is similarly 103// a suffix appended to the displacement for selection purposes; 104// e.g. we want to reject small 20-bit displacements if a 12-bit form 105// also exists, but we want to accept them otherwise. 106class AddressingMode<string seltype, string bitsize, string dispsize, 107 string suffix, string length, int numops, string format, 108 dag operands> 109 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops, 110 "select"##seltype##dispsize##suffix##length, 111 [add, sub, or, frameindex, z_adjdynalloc]>, 112 AddressOperand<bitsize, dispsize, length, format, operands>; 113 114// An addressing mode with a base and displacement but no index. 115class BDMode<string type, string bitsize, string dispsize, string suffix> 116 : AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr", 117 (ops !cast<RegisterOperand>("ADDR"##bitsize), 118 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>; 119 120// An addressing mode with a base, displacement and index. 121class BDXMode<string type, string bitsize, string dispsize, string suffix> 122 : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr", 123 (ops !cast<RegisterOperand>("ADDR"##bitsize), 124 !cast<Immediate>("disp"##dispsize##"imm"##bitsize), 125 !cast<RegisterOperand>("ADDR"##bitsize))>; 126 127// A BDMode paired with an immediate length operand of LENSIZE bits. 128class BDLMode<string type, string bitsize, string dispsize, string suffix, 129 string lensize> 130 : AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3, 131 "BDLAddr", 132 (ops !cast<RegisterOperand>("ADDR"##bitsize), 133 !cast<Immediate>("disp"##dispsize##"imm"##bitsize), 134 !cast<Immediate>("imm"##bitsize))>; 135 136// An addressing mode with a base, displacement and a vector index. 137class BDVMode<string bitsize, string dispsize> 138 : AddressOperand<bitsize, dispsize, "", "BDVAddr", 139 (ops !cast<RegisterOperand>("ADDR"##bitsize), 140 !cast<Immediate>("disp"##dispsize##"imm"##bitsize), 141 !cast<RegisterOperand>("VR128"))>; 142 143//===----------------------------------------------------------------------===// 144// Extracting immediate operands from nodes 145// These all create MVT::i64 nodes to ensure the value is not sign-extended 146// when converted from an SDNode to a MachineOperand later on. 147//===----------------------------------------------------------------------===// 148 149// Bits 0-15 (counting from the lsb). 150def LL16 : SDNodeXForm<imm, [{ 151 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL; 152 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 153}]>; 154 155// Bits 16-31 (counting from the lsb). 156def LH16 : SDNodeXForm<imm, [{ 157 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16; 158 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 159}]>; 160 161// Bits 32-47 (counting from the lsb). 162def HL16 : SDNodeXForm<imm, [{ 163 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32; 164 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 165}]>; 166 167// Bits 48-63 (counting from the lsb). 168def HH16 : SDNodeXForm<imm, [{ 169 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48; 170 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 171}]>; 172 173// Low 32 bits. 174def LF32 : SDNodeXForm<imm, [{ 175 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL; 176 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 177}]>; 178 179// High 32 bits. 180def HF32 : SDNodeXForm<imm, [{ 181 uint64_t Value = N->getZExtValue() >> 32; 182 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 183}]>; 184 185// Truncate an immediate to a 8-bit signed quantity. 186def SIMM8 : SDNodeXForm<imm, [{ 187 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N), 188 MVT::i64); 189}]>; 190 191// Truncate an immediate to a 8-bit unsigned quantity. 192def UIMM8 : SDNodeXForm<imm, [{ 193 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), SDLoc(N), 194 MVT::i64); 195}]>; 196 197// Truncate an immediate to a 8-bit unsigned quantity and mask off low bit. 198def UIMM8EVEN : SDNodeXForm<imm, [{ 199 return CurDAG->getTargetConstant(N->getZExtValue() & 0xfe, SDLoc(N), 200 MVT::i64); 201}]>; 202 203// Truncate an immediate to a 12-bit unsigned quantity. 204def UIMM12 : SDNodeXForm<imm, [{ 205 return CurDAG->getTargetConstant(N->getZExtValue() & 0xfff, SDLoc(N), 206 MVT::i64); 207}]>; 208 209// Truncate an immediate to a 16-bit signed quantity. 210def SIMM16 : SDNodeXForm<imm, [{ 211 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N), 212 MVT::i64); 213}]>; 214 215// Truncate an immediate to a 16-bit unsigned quantity. 216def UIMM16 : SDNodeXForm<imm, [{ 217 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), SDLoc(N), 218 MVT::i64); 219}]>; 220 221// Truncate an immediate to a 32-bit signed quantity. 222def SIMM32 : SDNodeXForm<imm, [{ 223 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), SDLoc(N), 224 MVT::i64); 225}]>; 226 227// Truncate an immediate to a 32-bit unsigned quantity. 228def UIMM32 : SDNodeXForm<imm, [{ 229 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N), 230 MVT::i64); 231}]>; 232 233// Negate and then truncate an immediate to a 32-bit unsigned quantity. 234def NEGIMM32 : SDNodeXForm<imm, [{ 235 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N), 236 MVT::i64); 237}]>; 238 239//===----------------------------------------------------------------------===// 240// Immediate asm operands. 241//===----------------------------------------------------------------------===// 242 243def U1Imm : ImmediateAsmOperand<"U1Imm">; 244def U2Imm : ImmediateAsmOperand<"U2Imm">; 245def U3Imm : ImmediateAsmOperand<"U3Imm">; 246def U4Imm : ImmediateAsmOperand<"U4Imm">; 247def U6Imm : ImmediateAsmOperand<"U6Imm">; 248def S8Imm : ImmediateAsmOperand<"S8Imm">; 249def U8Imm : ImmediateAsmOperand<"U8Imm">; 250def U12Imm : ImmediateAsmOperand<"U12Imm">; 251def S16Imm : ImmediateAsmOperand<"S16Imm">; 252def U16Imm : ImmediateAsmOperand<"U16Imm">; 253def S32Imm : ImmediateAsmOperand<"S32Imm">; 254def U32Imm : ImmediateAsmOperand<"U32Imm">; 255 256//===----------------------------------------------------------------------===// 257// i32 immediates 258//===----------------------------------------------------------------------===// 259 260// Immediates for the lower and upper 16 bits of an i32, with the other 261// bits of the i32 being zero. 262def imm32ll16 : Immediate<i32, [{ 263 return SystemZ::isImmLL(N->getZExtValue()); 264}], LL16, "U16Imm">; 265 266def imm32lh16 : Immediate<i32, [{ 267 return SystemZ::isImmLH(N->getZExtValue()); 268}], LH16, "U16Imm">; 269 270// Immediates for the lower and upper 16 bits of an i32, with the other 271// bits of the i32 being one. 272def imm32ll16c : Immediate<i32, [{ 273 return SystemZ::isImmLL(uint32_t(~N->getZExtValue())); 274}], LL16, "U16Imm">; 275 276def imm32lh16c : Immediate<i32, [{ 277 return SystemZ::isImmLH(uint32_t(~N->getZExtValue())); 278}], LH16, "U16Imm">; 279 280// Short immediates 281def imm32zx1 : Immediate<i32, [{ 282 return isUInt<1>(N->getZExtValue()); 283}], NOOP_SDNodeXForm, "U1Imm">; 284 285def imm32zx2 : Immediate<i32, [{ 286 return isUInt<2>(N->getZExtValue()); 287}], NOOP_SDNodeXForm, "U2Imm">; 288 289def imm32zx3 : Immediate<i32, [{ 290 return isUInt<3>(N->getZExtValue()); 291}], NOOP_SDNodeXForm, "U3Imm">; 292 293def imm32zx4 : Immediate<i32, [{ 294 return isUInt<4>(N->getZExtValue()); 295}], NOOP_SDNodeXForm, "U4Imm">; 296 297// Note: this enforces an even value during code generation only. 298// When used from the assembler, any 4-bit value is allowed. 299def imm32zx4even : Immediate<i32, [{ 300 return isUInt<4>(N->getZExtValue()); 301}], UIMM8EVEN, "U4Imm">; 302 303def imm32zx6 : Immediate<i32, [{ 304 return isUInt<6>(N->getZExtValue()); 305}], NOOP_SDNodeXForm, "U6Imm">; 306 307def imm32sx8 : Immediate<i32, [{ 308 return isInt<8>(N->getSExtValue()); 309}], SIMM8, "S8Imm">; 310 311def imm32zx8 : Immediate<i32, [{ 312 return isUInt<8>(N->getZExtValue()); 313}], UIMM8, "U8Imm">; 314 315def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">; 316 317def imm32zx12 : Immediate<i32, [{ 318 return isUInt<12>(N->getZExtValue()); 319}], UIMM12, "U12Imm">; 320 321def imm32sx16 : Immediate<i32, [{ 322 return isInt<16>(N->getSExtValue()); 323}], SIMM16, "S16Imm">; 324 325def imm32zx16 : Immediate<i32, [{ 326 return isUInt<16>(N->getZExtValue()); 327}], UIMM16, "U16Imm">; 328 329def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">; 330 331// Full 32-bit immediates. we need both signed and unsigned versions 332// because the assembler is picky. E.g. AFI requires signed operands 333// while NILF requires unsigned ones. 334def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">; 335def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">; 336 337def imm32 : ImmLeaf<i32, [{}]>; 338 339//===----------------------------------------------------------------------===// 340// 64-bit immediates 341//===----------------------------------------------------------------------===// 342 343// Immediates for 16-bit chunks of an i64, with the other bits of the 344// i32 being zero. 345def imm64ll16 : Immediate<i64, [{ 346 return SystemZ::isImmLL(N->getZExtValue()); 347}], LL16, "U16Imm">; 348 349def imm64lh16 : Immediate<i64, [{ 350 return SystemZ::isImmLH(N->getZExtValue()); 351}], LH16, "U16Imm">; 352 353def imm64hl16 : Immediate<i64, [{ 354 return SystemZ::isImmHL(N->getZExtValue()); 355}], HL16, "U16Imm">; 356 357def imm64hh16 : Immediate<i64, [{ 358 return SystemZ::isImmHH(N->getZExtValue()); 359}], HH16, "U16Imm">; 360 361// Immediates for 16-bit chunks of an i64, with the other bits of the 362// i32 being one. 363def imm64ll16c : Immediate<i64, [{ 364 return SystemZ::isImmLL(uint64_t(~N->getZExtValue())); 365}], LL16, "U16Imm">; 366 367def imm64lh16c : Immediate<i64, [{ 368 return SystemZ::isImmLH(uint64_t(~N->getZExtValue())); 369}], LH16, "U16Imm">; 370 371def imm64hl16c : Immediate<i64, [{ 372 return SystemZ::isImmHL(uint64_t(~N->getZExtValue())); 373}], HL16, "U16Imm">; 374 375def imm64hh16c : Immediate<i64, [{ 376 return SystemZ::isImmHH(uint64_t(~N->getZExtValue())); 377}], HH16, "U16Imm">; 378 379// Immediates for the lower and upper 32 bits of an i64, with the other 380// bits of the i32 being zero. 381def imm64lf32 : Immediate<i64, [{ 382 return SystemZ::isImmLF(N->getZExtValue()); 383}], LF32, "U32Imm">; 384 385def imm64hf32 : Immediate<i64, [{ 386 return SystemZ::isImmHF(N->getZExtValue()); 387}], HF32, "U32Imm">; 388 389// Immediates for the lower and upper 32 bits of an i64, with the other 390// bits of the i32 being one. 391def imm64lf32c : Immediate<i64, [{ 392 return SystemZ::isImmLF(uint64_t(~N->getZExtValue())); 393}], LF32, "U32Imm">; 394 395def imm64hf32c : Immediate<i64, [{ 396 return SystemZ::isImmHF(uint64_t(~N->getZExtValue())); 397}], HF32, "U32Imm">; 398 399// Short immediates. 400def imm64sx8 : Immediate<i64, [{ 401 return isInt<8>(N->getSExtValue()); 402}], SIMM8, "S8Imm">; 403 404def imm64zx8 : Immediate<i64, [{ 405 return isUInt<8>(N->getSExtValue()); 406}], UIMM8, "U8Imm">; 407 408def imm64sx16 : Immediate<i64, [{ 409 return isInt<16>(N->getSExtValue()); 410}], SIMM16, "S16Imm">; 411 412def imm64zx16 : Immediate<i64, [{ 413 return isUInt<16>(N->getZExtValue()); 414}], UIMM16, "U16Imm">; 415 416def imm64sx32 : Immediate<i64, [{ 417 return isInt<32>(N->getSExtValue()); 418}], SIMM32, "S32Imm">; 419 420def imm64zx32 : Immediate<i64, [{ 421 return isUInt<32>(N->getZExtValue()); 422}], UIMM32, "U32Imm">; 423 424def imm64zx32n : Immediate<i64, [{ 425 return isUInt<32>(-N->getSExtValue()); 426}], NEGIMM32, "U32Imm">; 427 428def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>; 429 430//===----------------------------------------------------------------------===// 431// Floating-point immediates 432//===----------------------------------------------------------------------===// 433 434// Floating-point zero. 435def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 436 437// Floating point negative zero. 438def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; 439 440//===----------------------------------------------------------------------===// 441// Symbolic address operands 442//===----------------------------------------------------------------------===// 443 444// PC-relative asm operands. 445def PCRel16 : PCRelAsmOperand<"16">; 446def PCRel32 : PCRelAsmOperand<"32">; 447def PCRelTLS16 : PCRelTLSAsmOperand<"16">; 448def PCRelTLS32 : PCRelTLSAsmOperand<"32">; 449 450// PC-relative offsets of a basic block. The offset is sign-extended 451// and multiplied by 2. 452def brtarget16 : PCRelOperand<OtherVT, PCRel16> { 453 let EncoderMethod = "getPC16DBLEncoding"; 454 let DecoderMethod = "decodePC16DBLBranchOperand"; 455} 456def brtarget32 : PCRelOperand<OtherVT, PCRel32> { 457 let EncoderMethod = "getPC32DBLEncoding"; 458 let DecoderMethod = "decodePC32DBLBranchOperand"; 459} 460 461// Variants of brtarget16/32 with an optional additional TLS symbol. 462// These are used to annotate calls to __tls_get_offset. 463def tlssym : Operand<i64> { } 464def brtarget16tls : PCRelTLSOperand<OtherVT, PCRelTLS16> { 465 let MIOperandInfo = (ops brtarget16:$func, tlssym:$sym); 466 let EncoderMethod = "getPC16DBLTLSEncoding"; 467 let DecoderMethod = "decodePC16DBLBranchOperand"; 468} 469def brtarget32tls : PCRelTLSOperand<OtherVT, PCRelTLS32> { 470 let MIOperandInfo = (ops brtarget32:$func, tlssym:$sym); 471 let EncoderMethod = "getPC32DBLTLSEncoding"; 472 let DecoderMethod = "decodePC32DBLBranchOperand"; 473} 474 475// A PC-relative offset of a global value. The offset is sign-extended 476// and multiplied by 2. 477def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> { 478 let EncoderMethod = "getPC32DBLEncoding"; 479 let DecoderMethod = "decodePC32DBLOperand"; 480} 481 482//===----------------------------------------------------------------------===// 483// Addressing modes 484//===----------------------------------------------------------------------===// 485 486// 12-bit displacement operands. 487def disp12imm32 : Operand<i32>; 488def disp12imm64 : Operand<i64>; 489 490// 20-bit displacement operands. 491def disp20imm32 : Operand<i32>; 492def disp20imm64 : Operand<i64>; 493 494def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">; 495def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">; 496def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">; 497def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">; 498def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">; 499def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">; 500def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">; 501def BDVAddr64Disp12 : AddressAsmOperand<"BDVAddr", "64", "12">; 502 503// DAG patterns and operands for addressing modes. Each mode has 504// the form <type><range><group>[<len>] where: 505// 506// <type> is one of: 507// shift : base + displacement (32-bit) 508// bdaddr : base + displacement 509// mviaddr : like bdaddr, but reject cases with a natural index 510// bdxaddr : base + displacement + index 511// laaddr : like bdxaddr, but used for Load Address operations 512// dynalloc : base + displacement + index + ADJDYNALLOC 513// bdladdr : base + displacement with a length field 514// bdvaddr : base + displacement with a vector index 515// 516// <range> is one of: 517// 12 : the displacement is an unsigned 12-bit value 518// 20 : the displacement is a signed 20-bit value 519// 520// <group> is one of: 521// pair : used when there is an equivalent instruction with the opposite 522// range value (12 or 20) 523// only : used when there is no equivalent instruction with the opposite 524// range value 525// 526// <len> is one of: 527// 528// <empty> : there is no length field 529// len8 : the length field is 8 bits, with a range of [1, 0x100]. 530def shift12only : BDMode <"BDAddr", "32", "12", "Only">; 531def shift20only : BDMode <"BDAddr", "32", "20", "Only">; 532def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">; 533def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">; 534def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">; 535def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">; 536def mviaddr12pair : BDMode <"MVIAddr", "64", "12", "Pair">; 537def mviaddr20pair : BDMode <"MVIAddr", "64", "20", "Pair">; 538def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">; 539def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">; 540def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">; 541def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">; 542def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">; 543def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">; 544def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">; 545def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">; 546def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">; 547def bdvaddr12only : BDVMode< "64", "12">; 548 549//===----------------------------------------------------------------------===// 550// Miscellaneous 551//===----------------------------------------------------------------------===// 552 553// Access registers. At present we just use them for accessing the thread 554// pointer, so we don't expose them as register to LLVM. 555def AccessReg : AsmOperandClass { 556 let Name = "AccessReg"; 557 let ParserMethod = "parseAccessReg"; 558} 559def access_reg : Immediate<i32, [{ return N->getZExtValue() < 16; }], 560 NOOP_SDNodeXForm, "AccessReg"> { 561 let ParserMatchClass = AccessReg; 562} 563 564// A 4-bit condition-code mask. 565def cond4 : PatLeaf<(i32 imm), [{ return (N->getZExtValue() < 16); }]>, 566 Operand<i32> { 567 let PrintMethod = "printCond4Operand"; 568} 569