1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file contains the WebAssembly implementation of the
12 /// TargetInstrInfo class.
13 ///
14 //===----------------------------------------------------------------------===//
15
16 #include "WebAssemblyInstrInfo.h"
17 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
18 #include "WebAssemblyMachineFunctionInfo.h"
19 #include "WebAssemblySubtarget.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 using namespace llvm;
25
26 #define DEBUG_TYPE "wasm-instr-info"
27
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "WebAssemblyGenInstrInfo.inc"
30
WebAssemblyInstrInfo(const WebAssemblySubtarget & STI)31 WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
32 : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
33 WebAssembly::ADJCALLSTACKUP),
34 RI(STI.getTargetTriple()) {}
35
isReallyTriviallyReMaterializable(const MachineInstr & MI,AliasAnalysis * AA) const36 bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
37 const MachineInstr &MI, AliasAnalysis *AA) const {
38 switch (MI.getOpcode()) {
39 case WebAssembly::CONST_I32:
40 case WebAssembly::CONST_I64:
41 case WebAssembly::CONST_F32:
42 case WebAssembly::CONST_F64:
43 // isReallyTriviallyReMaterializableGeneric misses these because of the
44 // ARGUMENTS implicit def, so we manualy override it here.
45 return true;
46 default:
47 return false;
48 }
49 }
50
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const51 void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator I,
53 const DebugLoc &DL, unsigned DestReg,
54 unsigned SrcReg, bool KillSrc) const {
55 // This method is called by post-RA expansion, which expects only pregs to
56 // exist. However we need to handle both here.
57 auto &MRI = MBB.getParent()->getRegInfo();
58 const TargetRegisterClass *RC =
59 TargetRegisterInfo::isVirtualRegister(DestReg)
60 ? MRI.getRegClass(DestReg)
61 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
62
63 unsigned CopyLocalOpcode;
64 if (RC == &WebAssembly::I32RegClass)
65 CopyLocalOpcode = WebAssembly::COPY_LOCAL_I32;
66 else if (RC == &WebAssembly::I64RegClass)
67 CopyLocalOpcode = WebAssembly::COPY_LOCAL_I64;
68 else if (RC == &WebAssembly::F32RegClass)
69 CopyLocalOpcode = WebAssembly::COPY_LOCAL_F32;
70 else if (RC == &WebAssembly::F64RegClass)
71 CopyLocalOpcode = WebAssembly::COPY_LOCAL_F64;
72 else
73 llvm_unreachable("Unexpected register class");
74
75 BuildMI(MBB, I, DL, get(CopyLocalOpcode), DestReg)
76 .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
77 }
78
79 MachineInstr *
commuteInstructionImpl(MachineInstr & MI,bool NewMI,unsigned OpIdx1,unsigned OpIdx2) const80 WebAssemblyInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
81 unsigned OpIdx1,
82 unsigned OpIdx2) const {
83 // If the operands are stackified, we can't reorder them.
84 WebAssemblyFunctionInfo &MFI =
85 *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
86 if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
87 MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
88 return nullptr;
89
90 // Otherwise use the default implementation.
91 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
92 }
93
94 // Branch analysis.
analyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool) const95 bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
96 MachineBasicBlock *&TBB,
97 MachineBasicBlock *&FBB,
98 SmallVectorImpl<MachineOperand> &Cond,
99 bool /*AllowModify*/) const {
100 bool HaveCond = false;
101 for (MachineInstr &MI : MBB.terminators()) {
102 switch (MI.getOpcode()) {
103 default:
104 // Unhandled instruction; bail out.
105 return true;
106 case WebAssembly::BR_IF:
107 if (HaveCond)
108 return true;
109 // If we're running after CFGStackify, we can't optimize further.
110 if (!MI.getOperand(0).isMBB())
111 return true;
112 Cond.push_back(MachineOperand::CreateImm(true));
113 Cond.push_back(MI.getOperand(1));
114 TBB = MI.getOperand(0).getMBB();
115 HaveCond = true;
116 break;
117 case WebAssembly::BR_UNLESS:
118 if (HaveCond)
119 return true;
120 // If we're running after CFGStackify, we can't optimize further.
121 if (!MI.getOperand(0).isMBB())
122 return true;
123 Cond.push_back(MachineOperand::CreateImm(false));
124 Cond.push_back(MI.getOperand(1));
125 TBB = MI.getOperand(0).getMBB();
126 HaveCond = true;
127 break;
128 case WebAssembly::BR:
129 // If we're running after CFGStackify, we can't optimize further.
130 if (!MI.getOperand(0).isMBB())
131 return true;
132 if (!HaveCond)
133 TBB = MI.getOperand(0).getMBB();
134 else
135 FBB = MI.getOperand(0).getMBB();
136 break;
137 }
138 if (MI.isBarrier())
139 break;
140 }
141
142 return false;
143 }
144
RemoveBranch(MachineBasicBlock & MBB) const145 unsigned WebAssemblyInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
146 MachineBasicBlock::instr_iterator I = MBB.instr_end();
147 unsigned Count = 0;
148
149 while (I != MBB.instr_begin()) {
150 --I;
151 if (I->isDebugValue())
152 continue;
153 if (!I->isTerminator())
154 break;
155 // Remove the branch.
156 I->eraseFromParent();
157 I = MBB.instr_end();
158 ++Count;
159 }
160
161 return Count;
162 }
163
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,const DebugLoc & DL) const164 unsigned WebAssemblyInstrInfo::InsertBranch(MachineBasicBlock &MBB,
165 MachineBasicBlock *TBB,
166 MachineBasicBlock *FBB,
167 ArrayRef<MachineOperand> Cond,
168 const DebugLoc &DL) const {
169 if (Cond.empty()) {
170 if (!TBB)
171 return 0;
172
173 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
174 return 1;
175 }
176
177 assert(Cond.size() == 2 && "Expected a flag and a successor block");
178
179 if (Cond[0].getImm()) {
180 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).addOperand(Cond[1]);
181 } else {
182 BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS))
183 .addMBB(TBB)
184 .addOperand(Cond[1]);
185 }
186 if (!FBB)
187 return 1;
188
189 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
190 return 2;
191 }
192
ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const193 bool WebAssemblyInstrInfo::ReverseBranchCondition(
194 SmallVectorImpl<MachineOperand> &Cond) const {
195 assert(Cond.size() == 2 && "Expected a flag and a successor block");
196 Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
197 return false;
198 }
199