1; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s 2; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4target triple = "amdgcn--" 5 6; CHECK-LABEL: {{^}}main: 7; 8; Test for compilation only. This generated an invalid machine instruction 9; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both 10; of which were in SGPRs. 11define amdgpu_vs float @main(i32 %v) { 12main_body: 13 %d1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 960) 14 %d2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 976) 15 br i1 undef, label %ENDIF56, label %IF57 16 17IF57: ; preds = %ENDIF 18 %v.1 = mul i32 %v, 2 19 br label %ENDIF56 20 21ENDIF56: ; preds = %IF57, %ENDIF 22 %v.2 = phi i32 [ %v, %main_body ], [ %v.1, %IF57 ] 23 %d1.i = bitcast float %d1 to i32 24 %cc1 = icmp eq i32 %d1.i, 0 25 br i1 %cc1, label %ENDIF59, label %IF60 26 27IF60: ; preds = %ENDIF56 28 %v.3 = mul i32 %v.2, 2 29 br label %ENDIF59 30 31ENDIF59: ; preds = %IF60, %ENDIF56 32 %v.4 = phi i32 [ %v.2, %ENDIF56 ], [ %v.3, %IF60 ] 33 %d2.i = bitcast float %d2 to i32 34 %cc2 = icmp eq i32 %d2.i, 0 35 br i1 %cc2, label %ENDIF62, label %IF63 36 37IF63: ; preds = %ENDIF59 38 unreachable 39 40ENDIF62: ; preds = %ENDIF59 41 %r = bitcast i32 %v.4 to float 42 ret float %r 43} 44 45; Function Attrs: nounwind readnone 46declare float @llvm.SI.load.const(<16 x i8>, i32) #0 47 48attributes #0 = { nounwind readnone } 49attributes #1 = { readnone } 50