1;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s 2 3; This test is for a bug in 4; DAGCombiner::reduceBuildVecConvertToConvertBuildVec() where 5; the wrong type was being passed to 6; TargetLowering::getOperationAction() when checking the legality of 7; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes. 8 9 10; CHECK: {{^}}sint: 11; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 12 13define void @sint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) { 14entry: 15 %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 16 %sint = load i32, i32 addrspace(1) * %in 17 %conv = sitofp i32 %sint to float 18 %0 = insertelement <4 x float> undef, float %conv, i32 0 19 %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer 20 store <4 x float> %splat, <4 x float> addrspace(1)* %out 21 ret void 22} 23 24;CHECK: {{^}}uint: 25;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 26 27define void @uint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) { 28entry: 29 %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 30 %uint = load i32, i32 addrspace(1) * %in 31 %conv = uitofp i32 %uint to float 32 %0 = insertelement <4 x float> undef, float %conv, i32 0 33 %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer 34 store <4 x float> %splat, <4 x float> addrspace(1)* %out 35 ret void 36} 37