1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM 2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM 3; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB 4 5@a = global i8 1, align 1 6@b = global i16 2, align 2 7 8define void @t1() nounwind uwtable ssp { 9; ARM: t1 10; ARM: ldrb 11; ARM-NOT: uxtb 12; ARM-NOT: and{{.*}}, #255 13; THUMB: t1 14; THUMB: ldrb 15; THUMB-NOT: uxtb 16; THUMB-NOT: and{{.*}}, #255 17 %1 = load i8, i8* @a, align 1 18 call void @foo1(i8 zeroext %1) 19 ret void 20} 21 22define void @t2() nounwind uwtable ssp { 23; ARM: t2 24; ARM: ldrh 25; ARM-NOT: uxth 26; THUMB: t2 27; THUMB: ldrh 28; THUMB-NOT: uxth 29 %1 = load i16, i16* @b, align 2 30 call void @foo2(i16 zeroext %1) 31 ret void 32} 33 34declare void @foo1(i8 zeroext) 35declare void @foo2(i16 zeroext) 36 37define i32 @t3() nounwind uwtable ssp { 38; ARM: t3 39; ARM: ldrb 40; ARM-NOT: uxtb 41; ARM-NOT: and{{.*}}, #255 42; THUMB: t3 43; THUMB: ldrb 44; THUMB-NOT: uxtb 45; THUMB-NOT: and{{.*}}, #255 46 %1 = load i8, i8* @a, align 1 47 %2 = zext i8 %1 to i32 48 ret i32 %2 49} 50 51define i32 @t4() nounwind uwtable ssp { 52; ARM: t4 53; ARM: ldrh 54; ARM-NOT: uxth 55; THUMB: t4 56; THUMB: ldrh 57; THUMB-NOT: uxth 58 %1 = load i16, i16* @b, align 2 59 %2 = zext i16 %1 to i32 60 ret i32 %2 61} 62 63define i32 @t5() nounwind uwtable ssp { 64; ARM: t5 65; ARM: ldrsh 66; ARM-NOT: sxth 67; THUMB: t5 68; THUMB: ldrsh 69; THUMB-NOT: sxth 70 %1 = load i16, i16* @b, align 2 71 %2 = sext i16 %1 to i32 72 ret i32 %2 73} 74 75define i32 @t6() nounwind uwtable ssp { 76; ARM: t6 77; ARM: ldrsb 78; ARM-NOT: sxtb 79; THUMB: t6 80; THUMB: ldrsb 81; THUMB-NOT: sxtb 82 %1 = load i8, i8* @a, align 2 83 %2 = sext i8 %1 to i32 84 ret i32 %2 85} 86