1; Positive test for inline register constraints 2; 3; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s 4; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s 5 6define i32 @main() nounwind { 7entry: 8 9; r with char 10;CHECK: #APP 11;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23 12;CHECK: #NO_APP 13 tail call i8 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i8 27, i8 23) nounwind 14 15; r with short 16;CHECK: #APP 17;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 13 18;CHECK: #NO_APP 19 tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i16 17, i16 13) nounwind 20 21; r with int 22;CHECK: #APP 23;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3 24;CHECK: #NO_APP 25 tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i32 7, i32 3) nounwind 26 27; Now c with 1024: make sure register $25 is picked 28; CHECK: #APP 29; CHECK: addiu $25, ${{[0-9]+}}, 1024 30; CHECK: #NO_APP 31 tail call i32 asm sideeffect "addiu $0, $1, $2", "=c,c,I"(i32 4194304, i32 1024) nounwind 32 33; Now l with 1024: make sure register lo is picked. We do this by checking the instruction 34; after the inline expression for a mflo to pull the value out of lo. 35; CHECK: #APP 36; CHECK: mtlo ${{[0-9]+}} 37; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}} 38; CHECK: #NO_APP 39; CHECK-NEXT: mflo ${{[0-9]+}} 40 %bosco = alloca i32, align 4 41 call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind 42 store volatile i32 %4, i32* %bosco, align 4 43 44 ret i32 0 45} 46