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1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN:    -check-prefixes=ALL,M2,M2-M3
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN:    -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
5; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
6; RUN:    -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
7; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
8; RUN:    -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
9; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
10; RUN:    -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
11; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
12; RUN:    -check-prefixes=ALL,SEL,SEL-32
13; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
14; RUN:    -check-prefixes=ALL,M3,M2-M3
15; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
16; RUN:    -check-prefixes=ALL,CMOV,CMOV-64
17; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
18; RUN:    -check-prefixes=ALL,CMOV,CMOV-64
19; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
20; RUN:    -check-prefixes=ALL,CMOV,CMOV-64
21; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
22; RUN:    -check-prefixes=ALL,CMOV,CMOV-64
23; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
24; RUN:    -check-prefixes=ALL,CMOV,CMOV-64
25; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
26; RUN:    -check-prefixes=ALL,SEL,SEL-64
27; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
28; RUN:    -check-prefixes=ALL,MM32R3
29; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
30; RUN:    -check-prefixes=ALL,MMR6,MM32R6
31
32define signext i1 @tst_select_i1_i1(i1 signext %s,
33                                    i1 signext %x, i1 signext %y) {
34entry:
35  ; ALL-LABEL: tst_select_i1_i1:
36
37  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
38  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
39  ; M2-M3:  nop
40  ; M2-M3:  move    $5, $6
41  ; M2-M3:  $[[BB0]]:
42  ; M2-M3:  jr      $ra
43  ; M2-M3:  move    $2, $5
44
45  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
46  ; CMOV:   movn    $6, $5, $[[T0]]
47  ; CMOV:   move    $2, $6
48
49  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
50  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
51  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
52  ; SEL:    or      $2, $[[T2]], $[[T1]]
53
54  ; MM32R3:   andi16  $[[T0:[0-9]+]], $4, 1
55  ; MM32R3:   movn    $[[T1:[0-9]+]], $5, $[[T0]]
56  ; MM32R3:   move    $2, $[[T1]]
57
58  ; MMR6:     andi16  $[[T0:[0-9]+]], $4, 1
59  ; MMR6:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
60  ; MMR6:     selnez  $[[T2:[0-9]+]], $5, $[[T0]]
61  ; MMR6:     or      $2, $[[T2]], $[[T1]]
62
63  %r = select i1 %s, i1 %x, i1 %y
64  ret i1 %r
65}
66
67define signext i8 @tst_select_i1_i8(i1 signext %s,
68                                    i8 signext %x, i8 signext %y) {
69entry:
70  ; ALL-LABEL: tst_select_i1_i8:
71
72  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
73  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
74  ; M2-M3:  nop
75  ; M2-M3:  move    $5, $6
76  ; M2-M3:  $[[BB0]]:
77  ; M2-M3:  jr      $ra
78  ; M2-M3:  move    $2, $5
79
80  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
81  ; CMOV:   movn    $6, $5, $[[T0]]
82  ; CMOV:   move    $2, $6
83
84  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
85  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
86  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
87  ; SEL:    or      $2, $[[T2]], $[[T1]]
88
89  ; MM32R3:   andi16  $[[T0:[0-9]+]], $4, 1
90  ; MM32R3:   movn    $[[T1:[0-9]+]], $5, $[[T0]]
91  ; MM32R3:   move    $2, $[[T1]]
92
93  ; MMR6:     andi16  $[[T0:[0-9]+]], $4, 1
94  ; MMR6:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
95  ; MMR6:     selnez  $[[T2:[0-9]+]], $5, $[[T0]]
96  ; MMR6:     or      $2, $[[T2]], $[[T1]]
97
98  %r = select i1 %s, i8 %x, i8 %y
99  ret i8 %r
100}
101
102define signext i32 @tst_select_i1_i32(i1 signext %s,
103                                      i32 signext %x, i32 signext %y) {
104entry:
105  ; ALL-LABEL: tst_select_i1_i32:
106
107  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
108  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
109  ; M2-M3:  nop
110  ; M2-M3:  move    $5, $6
111  ; M2-M3:  $[[BB0]]:
112  ; M2-M3:  jr      $ra
113  ; M2-M3:  move    $2, $5
114
115  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
116  ; CMOV:   movn    $6, $5, $[[T0]]
117  ; CMOV:   move    $2, $6
118
119  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
120  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
121  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
122  ; SEL:    or      $2, $[[T2]], $[[T1]]
123
124  ; MM32R3:     andi16  $[[T0:[0-9]+]], $4, 1
125  ; MM32R3:     movn    $[[T1:[0-9]+]], $5, $[[T0]]
126  ; MM32R3:     move    $2, $[[T1]]
127
128  ; MMR6:       andi16  $[[T0:[0-9]+]], $4, 1
129  ; MMR6:       seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
130  ; MMR6:       selnez  $[[T2:[0-9]+]], $5, $[[T0]]
131  ; MMR6:       or      $2, $[[T2]], $[[T1]]
132
133  %r = select i1 %s, i32 %x, i32 %y
134  ret i32 %r
135}
136
137define signext i64 @tst_select_i1_i64(i1 signext %s,
138                                      i64 signext %x, i64 signext %y) {
139entry:
140  ; ALL-LABEL: tst_select_i1_i64:
141
142  ; M2:     andi    $[[T0:[0-9]+]], $4, 1
143  ; M2:     bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
144  ; M2:     nop
145  ; M2:     lw      $[[T1:[0-9]+]], 16($sp)
146  ; M2:     $[[BB0]]:
147  ; FIXME: This branch is redundant
148  ; M2:     bnez    $[[T0]], $[[BB1:BB[0-9_]+]]
149  ; M2:     nop
150  ; M2:     lw      $[[T2:[0-9]+]], 20($sp)
151  ; M2:     $[[BB1]]:
152  ; M2:     move    $2, $[[T1]]
153  ; M2:     jr      $ra
154  ; M2:     move    $3, $[[T2]]
155
156  ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
157  ; CMOV-32:    lw      $2, 16($sp)
158  ; CMOV-32:    movn    $2, $6, $[[T0]]
159  ; CMOV-32:    lw      $3, 20($sp)
160  ; CMOV-32:    movn    $3, $7, $[[T0]]
161
162  ; SEL-32:     andi    $[[T0:[0-9]+]], $4, 1
163  ; SEL-32:     selnez  $[[T1:[0-9]+]], $6, $[[T0]]
164  ; SEL-32:     lw      $[[T2:[0-9]+]], 16($sp)
165  ; SEL-32:     seleqz  $[[T3:[0-9]+]], $[[T2]], $[[T0]]
166  ; SEL-32:     or      $2, $[[T1]], $[[T3]]
167  ; SEL-32:     selnez  $[[T4:[0-9]+]], $7, $[[T0]]
168  ; SEL-32:     lw      $[[T5:[0-9]+]], 20($sp)
169  ; SEL-32:     seleqz  $[[T6:[0-9]+]], $[[T5]], $[[T0]]
170  ; SEL-32:     or      $3, $[[T4]], $[[T6]]
171
172  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
173  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
174  ; M3:         nop
175  ; M3:         move    $5, $6
176  ; M3:         $[[BB0]]:
177  ; M3:         jr      $ra
178  ; M3:         move    $2, $5
179
180  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
181  ; CMOV-64:    movn    $6, $5, $[[T0]]
182  ; CMOV-64:    move    $2, $6
183
184  ; SEL-64:     andi    $[[T0:[0-9]+]], $4, 1
185  ; FIXME: This shift is redundant
186  ; SEL-64:     sll     $[[T0]], $[[T0]], 0
187  ; SEL-64:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
188  ; SEL-64:     selnez  $[[T0]], $5, $[[T0]]
189  ; SEL-64:     or      $2, $[[T0]], $[[T1]]
190
191  ; MM32R3:     andi16  $[[T0:[0-9]+]], $4, 1
192  ; MM32R3:     lw      $2, 16($sp)
193  ; MM32R3:     movn    $2, $6, $[[T0]]
194  ; MM32R3:     lw      $3, 20($sp)
195  ; MM32R3:     movn    $3, $7, $[[T0]]
196
197  ; MM32R6:     andi16  $[[T0:[0-9]+]], $4, 1
198  ; MM32R6:     lw      $[[T1:[0-9]+]], 16($sp)
199  ; MM32R6:     seleqz  $[[T2:[0-9]+]], $[[T1]], $[[T0]]
200  ; MM32R6:     selnez  $[[T3:[0-9]+]], $6, $[[T0]]
201  ; MM32R6:     or      $2, $[[T3]], $[[T2]]
202  ; MM32R6:     lw      $[[T4:[0-9]+]], 20($sp)
203  ; MM32R6:     seleqz  $[[T5:[0-9]+]], $[[T4]], $[[T0]]
204  ; MM32R6:     selnez  $[[T6:[0-9]+]], $7, $[[T0]]
205  ; MM32R6:     or      $3, $[[T6]], $[[T5]]
206
207  %r = select i1 %s, i64 %x, i64 %y
208  ret i64 %r
209}
210
211define i8* @tst_select_word_cst(i8* %a, i8* %b) {
212  ; ALL-LABEL: tst_select_word_cst:
213
214  ; M2:         addiu   $[[T0:[0-9]+]], $zero, -1
215  ; M2:         xor     $[[T1:[0-9]+]], $5, $[[T0]]
216  ; M2:         sltu    $[[T2:[0-9]+]], $zero, $[[T1]]
217  ; M2:         bnez    $[[T2]], $[[BB0:BB[0-9_]+]]
218  ; M2:         addiu   $2, $zero, 0
219  ; M2:         move    $2, $4
220  ; M2: $[[BB0]]:
221  ; M2:         jr      $ra
222
223  ; M3:         daddiu  $[[T0:[0-9]+]], $zero, -1
224  ; M3:         xor     $[[T1:[0-9]+]], $5, $[[T0]]
225  ; M3:         sltu    $[[T2:[0-9]+]], $zero, $[[T1]]
226  ; M3:         bnez    $[[T2]], $[[BB0:BB[0-9_]+]]
227  ; M3:         daddiu  $2, $zero, 0
228  ; M3:         move    $2, $4
229  ; M3: $[[BB0]]:
230  ; M3:         jr      $ra
231
232  ; CMOV-32:    addiu   $[[T0:[0-9]+]], $zero, -1
233  ; CMOV-32:    xor     $[[T1:[0-9]+]], $5, $[[T0]]
234  ; CMOV-32:    movn    $[[T2:[0-9]+]], $zero, $[[T1]]
235  ; CMOV-32:    jr      $ra
236  ; CMOV-32:    move    $2, $[[T2]]
237
238  ; SEL-32:     addiu   $[[T0:[0-9]+]], $zero, -1
239  ; SEL-32:     xor     $[[T1:[0-9]+]], $5, $[[T0]]
240  ; SEL-32:     sltu    $[[T2:[0-9]+]], $zero, $[[T1]]
241  ; SEL-32:     jr      $ra
242  ; SEL-32:     seleqz  $2, $4, $[[T2]]
243
244  ; CMOV-64:    daddiu  $[[T0:[0-9]+]], $zero, -1
245  ; CMOV-64:    xor     $[[T1:[0-9]+]], $5, $[[T0]]
246  ; CMOV-64:    movn    $[[T2:[0-9]+]], $zero, $[[T1]]
247  ; CMOV-64:    move    $2, $[[T2]]
248
249  ; SEL-64:     daddiu  $[[T0:[0-9]+]], $zero, -1
250  ; SEL-64:     xor     $[[T1:[0-9]+]], $5, $[[T0]]
251  ; SEL-64:     sltu    $[[T2:[0-9]+]], $zero, $[[T1]]
252  ; FIXME: This shift is redundant.
253  ; SEL-64:     sll     $[[T2]], $[[T2]], 0
254  ; SEL-64:     seleqz  $2, $4, $[[T2]]
255
256  ; MM32R3:     li16    $[[T0:[0-9]+]], -1
257  ; MM32R3:     xor     $[[T1:[0-9]+]], $5, $[[T0]]
258  ; MM32R3:     lui     $[[T2:[0-9]+]], 0
259  ; MM32R3:     movn    $[[T3:[0-9]+]], $[[T2]], $[[T1]]
260  ; MM32R3:     move    $2, $[[T3]]
261
262  ; MM32R6:     li16    $[[T0:[0-9]+]], -1
263  ; MM32R6:     xor     $[[T1:[0-9]+]], $5, $[[T0]]
264  ; MM32R6:     sltu    $[[T2:[0-9]+]], $zero, $[[T1]]
265  ; MM32R6:     seleqz  $2, $4, $[[T2]]
266
267  %cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
268  %r = select i1 %cmp, i8* %a, i8* null
269  ret i8* %r
270}
271