1; RUN: llc < %s -march=nvptx -mcpu=sm_20 -O2 | FileCheck %s 2 3; ************************************* 4; * Cases with no min/max 5 6define i32 @ab_eq_i32(i32 %a, i32 %b) { 7; LABEL: @ab_slt_i32 8; CHECK-NOT: min 9; CHECK-NOT: max 10 %cmp = icmp eq i32 %a, %b 11 %sel = select i1 %cmp, i32 %a, i32 %b 12 ret i32 %sel 13} 14 15define i64 @ba_ne_i64(i64 %a, i64 %b) { 16; LABEL: @ab_ne_i64 17; CHECK-NOT: min 18; CHECK-NOT: max 19 %cmp = icmp ne i64 %a, %b 20 %sel = select i1 %cmp, i64 %b, i64 %a 21 ret i64 %sel 22} 23 24; PTX does have e.g. max.s16, but at least as of Kepler (sm_3x) that 25; gets compiled to SASS that converts the 16 bit parameters to 32 bit 26; before using a 32 bit instruction. That is probably not a win and 27; NVCC 7.5 does not emit 16 bit min/max either, presumably for that 28; reason. 29define i16 @ab_ugt_i16(i16 %a, i16 %b) { 30; LABEL: @ab_ugt_i16 31; CHECK-NOT: min 32; CHECK-NOT: max 33 %cmp = icmp ugt i16 %a, %b 34 %sel = select i1 %cmp, i16 %a, i16 %b 35 ret i16 %sel 36} 37 38 39; ************************************* 40; * All variations with i32 41 42; *** ab, unsigned, i32 43define i32 @ab_ugt_i32(i32 %a, i32 %b) { 44; LABEL: @ab_ugt_i32 45; CHECK: max.u32 46 %cmp = icmp ugt i32 %a, %b 47 %sel = select i1 %cmp, i32 %a, i32 %b 48 ret i32 %sel 49} 50 51define i32 @ab_uge_i32(i32 %a, i32 %b) { 52; LABEL: @ab_uge_i32 53; CHECK: max.u32 54 %cmp = icmp uge i32 %a, %b 55 %sel = select i1 %cmp, i32 %a, i32 %b 56 ret i32 %sel 57} 58 59define i32 @ab_ult_i32(i32 %a, i32 %b) { 60; LABEL: @ab_ult_i32 61; CHECK: min.u32 62 %cmp = icmp ult i32 %a, %b 63 %sel = select i1 %cmp, i32 %a, i32 %b 64 ret i32 %sel 65} 66 67define i32 @ab_ule_i32(i32 %a, i32 %b) { 68; LABEL: @ab_ule_i32 69; CHECK: min.u32 70 %cmp = icmp ule i32 %a, %b 71 %sel = select i1 %cmp, i32 %a, i32 %b 72 ret i32 %sel 73} 74 75; *** ab, signed, i32 76define i32 @ab_sgt_i32(i32 %a, i32 %b) { 77; LABEL: @ab_ugt_i32 78; CHECK: max.s32 79 %cmp = icmp sgt i32 %a, %b 80 %sel = select i1 %cmp, i32 %a, i32 %b 81 ret i32 %sel 82} 83 84define i32 @ab_sge_i32(i32 %a, i32 %b) { 85; LABEL: @ab_sge_i32 86; CHECK: max.s32 87 %cmp = icmp sge i32 %a, %b 88 %sel = select i1 %cmp, i32 %a, i32 %b 89 ret i32 %sel 90} 91 92define i32 @ab_slt_i32(i32 %a, i32 %b) { 93; LABEL: @ab_slt_i32 94; CHECK: min.s32 95 %cmp = icmp slt i32 %a, %b 96 %sel = select i1 %cmp, i32 %a, i32 %b 97 ret i32 %sel 98} 99 100define i32 @ab_sle_i32(i32 %a, i32 %b) { 101; LABEL: @ab_sle_i32 102; CHECK: min.s32 103 %cmp = icmp sle i32 %a, %b 104 %sel = select i1 %cmp, i32 %a, i32 %b 105 ret i32 %sel 106} 107 108; *** ba, unsigned, i32 109define i32 @ba_ugt_i32(i32 %a, i32 %b) { 110; LABEL: @ba_ugt_i32 111; CHECK: min.u32 112 %cmp = icmp ugt i32 %a, %b 113 %sel = select i1 %cmp, i32 %b, i32 %a 114 ret i32 %sel 115} 116 117define i32 @ba_uge_i32(i32 %a, i32 %b) { 118; LABEL: @ba_uge_i32 119; CHECK: min.u32 120 %cmp = icmp uge i32 %a, %b 121 %sel = select i1 %cmp, i32 %b, i32 %a 122 ret i32 %sel 123} 124 125define i32 @ba_ult_i32(i32 %a, i32 %b) { 126; LABEL: @ba_ult_i32 127; CHECK: max.u32 128 %cmp = icmp ult i32 %a, %b 129 %sel = select i1 %cmp, i32 %b, i32 %a 130 ret i32 %sel 131} 132 133define i32 @ba_ule_i32(i32 %a, i32 %b) { 134; LABEL: @ba_ule_i32 135; CHECK: max.u32 136 %cmp = icmp ule i32 %a, %b 137 %sel = select i1 %cmp, i32 %b, i32 %a 138 ret i32 %sel 139} 140 141; *** ba, signed, i32 142define i32 @ba_sgt_i32(i32 %a, i32 %b) { 143; LBAEL: @ba_ugt_i32 144; CHECK: min.s32 145 %cmp = icmp sgt i32 %a, %b 146 %sel = select i1 %cmp, i32 %b, i32 %a 147 ret i32 %sel 148} 149 150define i32 @ba_sge_i32(i32 %a, i32 %b) { 151; LABEL: @ba_sge_i32 152; CHECK: min.s32 153 %cmp = icmp sge i32 %a, %b 154 %sel = select i1 %cmp, i32 %b, i32 %a 155 ret i32 %sel 156} 157 158define i32 @ba_slt_i32(i32 %a, i32 %b) { 159; LABEL: @ba_slt_i32 160; CHECK: max.s32 161 %cmp = icmp slt i32 %a, %b 162 %sel = select i1 %cmp, i32 %b, i32 %a 163 ret i32 %sel 164} 165 166define i32 @ba_sle_i32(i32 %a, i32 %b) { 167; LABEL: @ba_sle_i32 168; CHECK: max.s32 169 %cmp = icmp sle i32 %a, %b 170 %sel = select i1 %cmp, i32 %b, i32 %a 171 ret i32 %sel 172} 173 174; ************************************* 175; * All variations with i64 176 177; *** ab, unsigned, i64 178define i64 @ab_ugt_i64(i64 %a, i64 %b) { 179; LABEL: @ab_ugt_i64 180; CHECK: max.u64 181 %cmp = icmp ugt i64 %a, %b 182 %sel = select i1 %cmp, i64 %a, i64 %b 183 ret i64 %sel 184} 185 186define i64 @ab_uge_i64(i64 %a, i64 %b) { 187; LABEL: @ab_uge_i64 188; CHECK: max.u64 189 %cmp = icmp uge i64 %a, %b 190 %sel = select i1 %cmp, i64 %a, i64 %b 191 ret i64 %sel 192} 193 194define i64 @ab_ult_i64(i64 %a, i64 %b) { 195; LABEL: @ab_ult_i64 196; CHECK: min.u64 197 %cmp = icmp ult i64 %a, %b 198 %sel = select i1 %cmp, i64 %a, i64 %b 199 ret i64 %sel 200} 201 202define i64 @ab_ule_i64(i64 %a, i64 %b) { 203; LABEL: @ab_ule_i64 204; CHECK: min.u64 205 %cmp = icmp ule i64 %a, %b 206 %sel = select i1 %cmp, i64 %a, i64 %b 207 ret i64 %sel 208} 209 210; *** ab, signed, i64 211define i64 @ab_sgt_i64(i64 %a, i64 %b) { 212; LABEL: @ab_ugt_i64 213; CHECK: max.s64 214 %cmp = icmp sgt i64 %a, %b 215 %sel = select i1 %cmp, i64 %a, i64 %b 216 ret i64 %sel 217} 218 219define i64 @ab_sge_i64(i64 %a, i64 %b) { 220; LABEL: @ab_sge_i64 221; CHECK: max.s64 222 %cmp = icmp sge i64 %a, %b 223 %sel = select i1 %cmp, i64 %a, i64 %b 224 ret i64 %sel 225} 226 227define i64 @ab_slt_i64(i64 %a, i64 %b) { 228; LABEL: @ab_slt_i64 229; CHECK: min.s64 230 %cmp = icmp slt i64 %a, %b 231 %sel = select i1 %cmp, i64 %a, i64 %b 232 ret i64 %sel 233} 234 235define i64 @ab_sle_i64(i64 %a, i64 %b) { 236; LABEL: @ab_sle_i64 237; CHECK: min.s64 238 %cmp = icmp sle i64 %a, %b 239 %sel = select i1 %cmp, i64 %a, i64 %b 240 ret i64 %sel 241} 242 243; *** ba, unsigned, i64 244define i64 @ba_ugt_i64(i64 %a, i64 %b) { 245; LABEL: @ba_ugt_i64 246; CHECK: min.u64 247 %cmp = icmp ugt i64 %a, %b 248 %sel = select i1 %cmp, i64 %b, i64 %a 249 ret i64 %sel 250} 251 252define i64 @ba_uge_i64(i64 %a, i64 %b) { 253; LABEL: @ba_uge_i64 254; CHECK: min.u64 255 %cmp = icmp uge i64 %a, %b 256 %sel = select i1 %cmp, i64 %b, i64 %a 257 ret i64 %sel 258} 259 260define i64 @ba_ult_i64(i64 %a, i64 %b) { 261; LABEL: @ba_ult_i64 262; CHECK: max.u64 263 %cmp = icmp ult i64 %a, %b 264 %sel = select i1 %cmp, i64 %b, i64 %a 265 ret i64 %sel 266} 267 268define i64 @ba_ule_i64(i64 %a, i64 %b) { 269; LABEL: @ba_ule_i64 270; CHECK: max.u64 271 %cmp = icmp ule i64 %a, %b 272 %sel = select i1 %cmp, i64 %b, i64 %a 273 ret i64 %sel 274} 275 276; *** ba, signed, i64 277define i64 @ba_sgt_i64(i64 %a, i64 %b) { 278; LBAEL: @ba_ugt_i64 279; CHECK: min.s64 280 %cmp = icmp sgt i64 %a, %b 281 %sel = select i1 %cmp, i64 %b, i64 %a 282 ret i64 %sel 283} 284 285define i64 @ba_sge_i64(i64 %a, i64 %b) { 286; LABEL: @ba_sge_i64 287; CHECK: min.s64 288 %cmp = icmp sge i64 %a, %b 289 %sel = select i1 %cmp, i64 %b, i64 %a 290 ret i64 %sel 291} 292 293define i64 @ba_slt_i64(i64 %a, i64 %b) { 294; LABEL: @ba_slt_i64 295; CHECK: max.s64 296 %cmp = icmp slt i64 %a, %b 297 %sel = select i1 %cmp, i64 %b, i64 %a 298 ret i64 %sel 299} 300 301define i64 @ba_sle_i64(i64 %a, i64 %b) { 302; LABEL: @ba_sle_i64 303; CHECK: max.s64 304 %cmp = icmp sle i64 %a, %b 305 %sel = select i1 %cmp, i64 %b, i64 %a 306 ret i64 %sel 307} 308