1; Test 32-bit comparisons in which the second operand is zero-extended 2; from a PC-relative i16. 3; 4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 5 6@g = global i16 1 7@h = global i16 1, align 1, section "foo" 8 9; Check unsigned comparison. 10define i32 @f1(i32 %src1) { 11; CHECK-LABEL: f1: 12; CHECK: clhrl %r2, g 13; CHECK-NEXT: jl 14; CHECK: br %r14 15entry: 16 %val = load i16 , i16 *@g 17 %src2 = zext i16 %val to i32 18 %cond = icmp ult i32 %src1, %src2 19 br i1 %cond, label %exit, label %mulb 20mulb: 21 %mul = mul i32 %src1, %src1 22 br label %exit 23exit: 24 %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ] 25 %res = add i32 %tmp, 1 26 ret i32 %res 27} 28 29; Check signed comparison. 30define i32 @f2(i32 %src1) { 31; CHECK-LABEL: f2: 32; CHECK-NOT: clhrl 33; CHECK: br %r14 34entry: 35 %val = load i16 , i16 *@g 36 %src2 = zext i16 %val to i32 37 %cond = icmp slt i32 %src1, %src2 38 br i1 %cond, label %exit, label %mulb 39mulb: 40 %mul = mul i32 %src1, %src1 41 br label %exit 42exit: 43 %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ] 44 %res = add i32 %tmp, 1 45 ret i32 %res 46} 47 48; Check equality. 49define i32 @f3(i32 %src1) { 50; CHECK-LABEL: f3: 51; CHECK: clhrl %r2, g 52; CHECK-NEXT: je 53; CHECK: br %r14 54entry: 55 %val = load i16 , i16 *@g 56 %src2 = zext i16 %val to i32 57 %cond = icmp eq i32 %src1, %src2 58 br i1 %cond, label %exit, label %mulb 59mulb: 60 %mul = mul i32 %src1, %src1 61 br label %exit 62exit: 63 %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ] 64 %res = add i32 %tmp, 1 65 ret i32 %res 66} 67 68; Check inequality. 69define i32 @f4(i32 %src1) { 70; CHECK-LABEL: f4: 71; CHECK: clhrl %r2, g 72; CHECK-NEXT: jlh 73; CHECK: br %r14 74entry: 75 %val = load i16 , i16 *@g 76 %src2 = zext i16 %val to i32 77 %cond = icmp ne i32 %src1, %src2 78 br i1 %cond, label %exit, label %mulb 79mulb: 80 %mul = mul i32 %src1, %src1 81 br label %exit 82exit: 83 %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ] 84 %res = add i32 %tmp, 1 85 ret i32 %res 86} 87 88; Repeat f1 with an unaligned address. 89define i32 @f5(i32 %src1) { 90; CHECK-LABEL: f5: 91; CHECK: lgrl [[REG:%r[0-5]]], h@GOT 92; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]]) 93; CHECK: clrjl %r2, [[VAL]], 94; CHECK: br %r14 95entry: 96 %val = load i16 , i16 *@h, align 1 97 %src2 = zext i16 %val to i32 98 %cond = icmp ult i32 %src1, %src2 99 br i1 %cond, label %exit, label %mulb 100mulb: 101 %mul = mul i32 %src1, %src1 102 br label %exit 103exit: 104 %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ] 105 %res = add i32 %tmp, 1 106 ret i32 %res 107} 108 109; Check the comparison can be reversed if that allows CLHRL to be used. 110define i32 @f6(i32 %src2) { 111; CHECK-LABEL: f6: 112; CHECK: clhrl %r2, g 113; CHECK-NEXT: jh {{\.L.*}} 114; CHECK: br %r14 115entry: 116 %val = load i16 , i16 *@g 117 %src1 = zext i16 %val to i32 118 %cond = icmp ult i32 %src1, %src2 119 br i1 %cond, label %exit, label %mulb 120mulb: 121 %mul = mul i32 %src2, %src2 122 br label %exit 123exit: 124 %tmp = phi i32 [ %src2, %entry ], [ %mul, %mulb ] 125 %res = add i32 %tmp, 1 126 ret i32 %res 127} 128