1 /*
2 * Copyright © 2016 Red Hat
3 *
4 * based on anv driver:
5 * Copyright © 2016 Intel Corporation
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27 #include "radv_meta.h"
28 #include "nir/nir_builder.h"
29 #include "vk_format.h"
30
31 enum blit2d_dst_type {
32 /* We can bind this destination as a "normal" render target and render
33 * to it just like you would anywhere else.
34 */
35 BLIT2D_DST_TYPE_NORMAL,
36
37 /* The destination has a 3-channel RGB format. Since we can't render to
38 * non-power-of-two textures, we have to bind it as a red texture and
39 * select the correct component for the given red pixel in the shader.
40 */
41 BLIT2D_DST_TYPE_RGB,
42
43 BLIT2D_NUM_DST_TYPES,
44 };
45
46
47 enum blit2d_src_type {
48 BLIT2D_SRC_TYPE_IMAGE,
49 BLIT2D_SRC_TYPE_BUFFER,
50 BLIT2D_NUM_SRC_TYPES,
51 };
52
53 static void
create_iview(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * surf,VkImageUsageFlags usage,struct radv_image_view * iview,VkFormat depth_format)54 create_iview(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_meta_blit2d_surf *surf,
56 VkImageUsageFlags usage,
57 struct radv_image_view *iview, VkFormat depth_format)
58 {
59 VkFormat format;
60
61 if (depth_format)
62 format = depth_format;
63 else
64 format = surf->format;
65
66 radv_image_view_init(iview, cmd_buffer->device,
67 &(VkImageViewCreateInfo) {
68 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
69 .image = radv_image_to_handle(surf->image),
70 .viewType = VK_IMAGE_VIEW_TYPE_2D,
71 .format = format,
72 .subresourceRange = {
73 .aspectMask = surf->aspect_mask,
74 .baseMipLevel = surf->level,
75 .levelCount = 1,
76 .baseArrayLayer = surf->layer,
77 .layerCount = 1
78 },
79 }, cmd_buffer, usage);
80 }
81
82 static void
create_bview(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_buffer * src,struct radv_buffer_view * bview,VkFormat depth_format)83 create_bview(struct radv_cmd_buffer *cmd_buffer,
84 struct radv_meta_blit2d_buffer *src,
85 struct radv_buffer_view *bview, VkFormat depth_format)
86 {
87 VkFormat format;
88
89 if (depth_format)
90 format = depth_format;
91 else
92 format = src->format;
93 radv_buffer_view_init(bview, cmd_buffer->device,
94 &(VkBufferViewCreateInfo) {
95 .sType = VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO,
96 .flags = 0,
97 .buffer = radv_buffer_to_handle(src->buffer),
98 .format = format,
99 .offset = src->offset,
100 .range = VK_WHOLE_SIZE,
101 }, cmd_buffer);
102
103 }
104
105 struct blit2d_src_temps {
106 struct radv_image_view iview;
107
108 VkDescriptorSet set;
109 struct radv_buffer_view bview;
110 };
111
112 static void
blit2d_bind_src(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * src_img,struct radv_meta_blit2d_buffer * src_buf,struct blit2d_src_temps * tmp,enum blit2d_src_type src_type,VkFormat depth_format)113 blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
114 struct radv_meta_blit2d_surf *src_img,
115 struct radv_meta_blit2d_buffer *src_buf,
116 struct blit2d_src_temps *tmp,
117 enum blit2d_src_type src_type, VkFormat depth_format)
118 {
119 struct radv_device *device = cmd_buffer->device;
120 VkDevice vk_device = radv_device_to_handle(cmd_buffer->device);
121
122 if (src_type == BLIT2D_SRC_TYPE_BUFFER) {
123 create_bview(cmd_buffer, src_buf, &tmp->bview, depth_format);
124
125 radv_temp_descriptor_set_create(cmd_buffer->device, cmd_buffer,
126 device->meta_state.blit2d.ds_layouts[src_type],
127 &tmp->set);
128
129 radv_UpdateDescriptorSets(vk_device,
130 1, /* writeCount */
131 (VkWriteDescriptorSet[]) {
132 {
133 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
134 .dstSet = tmp->set,
135 .dstBinding = 0,
136 .dstArrayElement = 0,
137 .descriptorCount = 1,
138 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
139 .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->bview) }
140 }
141 }, 0, NULL);
142
143 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
144 device->meta_state.blit2d.p_layouts[src_type],
145 VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4,
146 &src_buf->pitch);
147 } else {
148 create_iview(cmd_buffer, src_img, VK_IMAGE_USAGE_SAMPLED_BIT, &tmp->iview,
149 depth_format);
150
151 radv_temp_descriptor_set_create(cmd_buffer->device, cmd_buffer,
152 device->meta_state.blit2d.ds_layouts[src_type],
153 &tmp->set);
154
155 radv_UpdateDescriptorSets(vk_device,
156 1, /* writeCount */
157 (VkWriteDescriptorSet[]) {
158 {
159 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
160 .dstSet = tmp->set,
161 .dstBinding = 0,
162 .dstArrayElement = 0,
163 .descriptorCount = 1,
164 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
165 .pImageInfo = (VkDescriptorImageInfo[]) {
166 {
167 .sampler = VK_NULL_HANDLE,
168 .imageView = radv_image_view_to_handle(&tmp->iview),
169 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
170 },
171 }
172 }
173 }, 0, NULL);
174
175 }
176
177 radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
178 VK_PIPELINE_BIND_POINT_GRAPHICS,
179 device->meta_state.blit2d.p_layouts[src_type], 0, 1,
180 &tmp->set, 0, NULL);
181 }
182
183 static void
blit2d_unbind_src(struct radv_cmd_buffer * cmd_buffer,struct blit2d_src_temps * tmp,enum blit2d_src_type src_type)184 blit2d_unbind_src(struct radv_cmd_buffer *cmd_buffer,
185 struct blit2d_src_temps *tmp,
186 enum blit2d_src_type src_type)
187 {
188 radv_temp_descriptor_set_destroy(cmd_buffer->device, tmp->set);
189 }
190
191 struct blit2d_dst_temps {
192 VkImage image;
193 struct radv_image_view iview;
194 VkFramebuffer fb;
195 };
196
197 static void
blit2d_bind_dst(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * dst,uint32_t width,uint32_t height,VkFormat depth_format,struct blit2d_dst_temps * tmp)198 blit2d_bind_dst(struct radv_cmd_buffer *cmd_buffer,
199 struct radv_meta_blit2d_surf *dst,
200 uint32_t width,
201 uint32_t height,
202 VkFormat depth_format,
203 struct blit2d_dst_temps *tmp)
204 {
205 VkImageUsageFlagBits bits;
206
207 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT)
208 bits = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
209 else
210 bits = VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT;
211
212 create_iview(cmd_buffer, dst, bits,
213 &tmp->iview, depth_format);
214
215 radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device),
216 &(VkFramebufferCreateInfo) {
217 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
218 .attachmentCount = 1,
219 .pAttachments = (VkImageView[]) {
220 radv_image_view_to_handle(&tmp->iview),
221 },
222 .width = width,
223 .height = height,
224 .layers = 1
225 }, &cmd_buffer->pool->alloc, &tmp->fb);
226 }
227
228 static void
blit2d_unbind_dst(struct radv_cmd_buffer * cmd_buffer,struct blit2d_dst_temps * tmp)229 blit2d_unbind_dst(struct radv_cmd_buffer *cmd_buffer,
230 struct blit2d_dst_temps *tmp)
231 {
232 VkDevice vk_device = radv_device_to_handle(cmd_buffer->device);
233 radv_DestroyFramebuffer(vk_device, tmp->fb, &cmd_buffer->pool->alloc);
234 }
235
236 static void
bind_pipeline(struct radv_cmd_buffer * cmd_buffer,enum blit2d_src_type src_type,unsigned fs_key)237 bind_pipeline(struct radv_cmd_buffer *cmd_buffer,
238 enum blit2d_src_type src_type, unsigned fs_key)
239 {
240 VkPipeline pipeline =
241 cmd_buffer->device->meta_state.blit2d.pipelines[src_type][fs_key];
242
243 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
244 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
245 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
246 }
247 }
248
249 static void
bind_depth_pipeline(struct radv_cmd_buffer * cmd_buffer,enum blit2d_src_type src_type)250 bind_depth_pipeline(struct radv_cmd_buffer *cmd_buffer,
251 enum blit2d_src_type src_type)
252 {
253 VkPipeline pipeline =
254 cmd_buffer->device->meta_state.blit2d.depth_only_pipeline[src_type];
255
256 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
257 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
258 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
259 }
260 }
261
262 static void
bind_stencil_pipeline(struct radv_cmd_buffer * cmd_buffer,enum blit2d_src_type src_type)263 bind_stencil_pipeline(struct radv_cmd_buffer *cmd_buffer,
264 enum blit2d_src_type src_type)
265 {
266 VkPipeline pipeline =
267 cmd_buffer->device->meta_state.blit2d.stencil_only_pipeline[src_type];
268
269 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
270 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
271 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
272 }
273 }
274
275 static void
radv_meta_blit2d_normal_dst(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * src_img,struct radv_meta_blit2d_buffer * src_buf,struct radv_meta_blit2d_surf * dst,unsigned num_rects,struct radv_meta_blit2d_rect * rects,enum blit2d_src_type src_type)276 radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
277 struct radv_meta_blit2d_surf *src_img,
278 struct radv_meta_blit2d_buffer *src_buf,
279 struct radv_meta_blit2d_surf *dst,
280 unsigned num_rects,
281 struct radv_meta_blit2d_rect *rects, enum blit2d_src_type src_type)
282 {
283 struct radv_device *device = cmd_buffer->device;
284
285 for (unsigned r = 0; r < num_rects; ++r) {
286 VkFormat depth_format = 0;
287 if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
288 depth_format = vk_format_stencil_only(dst->image->vk_format);
289 else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
290 depth_format = vk_format_depth_only(dst->image->vk_format);
291 struct blit2d_src_temps src_temps;
292 blit2d_bind_src(cmd_buffer, src_img, src_buf, &src_temps, src_type, depth_format);
293
294 uint32_t offset = 0;
295 struct blit2d_dst_temps dst_temps;
296 blit2d_bind_dst(cmd_buffer, dst, rects[r].dst_x + rects[r].width,
297 rects[r].dst_y + rects[r].height, depth_format, &dst_temps);
298
299 struct blit_vb_data {
300 float pos[2];
301 float tex_coord[2];
302 } vb_data[3];
303
304 unsigned vb_size = 3 * sizeof(*vb_data);
305
306 vb_data[0] = (struct blit_vb_data) {
307 .pos = {
308 rects[r].dst_x,
309 rects[r].dst_y,
310 },
311 .tex_coord = {
312 rects[r].src_x,
313 rects[r].src_y,
314 },
315 };
316
317 vb_data[1] = (struct blit_vb_data) {
318 .pos = {
319 rects[r].dst_x,
320 rects[r].dst_y + rects[r].height,
321 },
322 .tex_coord = {
323 rects[r].src_x,
324 rects[r].src_y + rects[r].height,
325 },
326 };
327
328 vb_data[2] = (struct blit_vb_data) {
329 .pos = {
330 rects[r].dst_x + rects[r].width,
331 rects[r].dst_y,
332 },
333 .tex_coord = {
334 rects[r].src_x + rects[r].width,
335 rects[r].src_y,
336 },
337 };
338
339
340 radv_cmd_buffer_upload_data(cmd_buffer, vb_size, 16, vb_data, &offset);
341
342 struct radv_buffer vertex_buffer = {
343 .device = device,
344 .size = vb_size,
345 .bo = cmd_buffer->upload.upload_bo,
346 .offset = offset,
347 };
348
349 radv_CmdBindVertexBuffers(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
350 (VkBuffer[]) {
351 radv_buffer_to_handle(&vertex_buffer),
352 },
353 (VkDeviceSize[]) {
354 0,
355 });
356
357
358 if (dst->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
359 unsigned fs_key = radv_format_meta_fs_key(dst_temps.iview.vk_format);
360
361 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
362 &(VkRenderPassBeginInfo) {
363 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
364 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
365 .framebuffer = dst_temps.fb,
366 .renderArea = {
367 .offset = { rects[r].dst_x, rects[r].dst_y, },
368 .extent = { rects[r].width, rects[r].height },
369 },
370 .clearValueCount = 0,
371 .pClearValues = NULL,
372 }, VK_SUBPASS_CONTENTS_INLINE);
373
374
375 bind_pipeline(cmd_buffer, src_type, fs_key);
376 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
377 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
378 &(VkRenderPassBeginInfo) {
379 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
380 .renderPass = device->meta_state.blit2d.depth_only_rp,
381 .framebuffer = dst_temps.fb,
382 .renderArea = {
383 .offset = { rects[r].dst_x, rects[r].dst_y, },
384 .extent = { rects[r].width, rects[r].height },
385 },
386 .clearValueCount = 0,
387 .pClearValues = NULL,
388 }, VK_SUBPASS_CONTENTS_INLINE);
389
390
391 bind_depth_pipeline(cmd_buffer, src_type);
392
393 } else if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
394 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
395 &(VkRenderPassBeginInfo) {
396 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
397 .renderPass = device->meta_state.blit2d.stencil_only_rp,
398 .framebuffer = dst_temps.fb,
399 .renderArea = {
400 .offset = { rects[r].dst_x, rects[r].dst_y, },
401 .extent = { rects[r].width, rects[r].height },
402 },
403 .clearValueCount = 0,
404 .pClearValues = NULL,
405 }, VK_SUBPASS_CONTENTS_INLINE);
406
407
408 bind_stencil_pipeline(cmd_buffer, src_type);
409 }
410
411 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
412 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
413
414 /* At the point where we emit the draw call, all data from the
415 * descriptor sets, etc. has been used. We are free to delete it.
416 */
417 blit2d_unbind_src(cmd_buffer, &src_temps, src_type);
418 blit2d_unbind_dst(cmd_buffer, &dst_temps);
419 }
420 }
421
422 void
radv_meta_blit2d(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * src_img,struct radv_meta_blit2d_buffer * src_buf,struct radv_meta_blit2d_surf * dst,unsigned num_rects,struct radv_meta_blit2d_rect * rects)423 radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
424 struct radv_meta_blit2d_surf *src_img,
425 struct radv_meta_blit2d_buffer *src_buf,
426 struct radv_meta_blit2d_surf *dst,
427 unsigned num_rects,
428 struct radv_meta_blit2d_rect *rects)
429 {
430 enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
431 BLIT2D_SRC_TYPE_IMAGE;
432 radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
433 num_rects, rects, src_type);
434 }
435
436 static nir_shader *
build_nir_vertex_shader(void)437 build_nir_vertex_shader(void)
438 {
439 const struct glsl_type *vec4 = glsl_vec4_type();
440 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
441 nir_builder b;
442
443 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
444 b.shader->info->name = ralloc_strdup(b.shader, "meta_blit_vs");
445
446 nir_variable *pos_in = nir_variable_create(b.shader, nir_var_shader_in,
447 vec4, "a_pos");
448 pos_in->data.location = VERT_ATTRIB_GENERIC0;
449 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
450 vec4, "gl_Position");
451 pos_out->data.location = VARYING_SLOT_POS;
452 nir_copy_var(&b, pos_out, pos_in);
453
454 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
455 vec2, "a_tex_pos");
456 tex_pos_in->data.location = VERT_ATTRIB_GENERIC1;
457 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
458 vec2, "v_tex_pos");
459 tex_pos_out->data.location = VARYING_SLOT_VAR0;
460 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
461 nir_copy_var(&b, tex_pos_out, tex_pos_in);
462
463 return b.shader;
464 }
465
466 typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
467 struct radv_device *,
468 nir_ssa_def *);
469
470 static nir_ssa_def *
build_nir_texel_fetch(struct nir_builder * b,struct radv_device * device,nir_ssa_def * tex_pos)471 build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
472 nir_ssa_def *tex_pos)
473 {
474 const struct glsl_type *sampler_type =
475 glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_UINT);
476 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
477 sampler_type, "s_tex");
478 sampler->data.descriptor_set = 0;
479 sampler->data.binding = 0;
480
481 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
482 tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
483 tex->op = nir_texop_txf;
484 tex->src[0].src_type = nir_tex_src_coord;
485 tex->src[0].src = nir_src_for_ssa(tex_pos);
486 tex->src[1].src_type = nir_tex_src_lod;
487 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
488 tex->dest_type = nir_type_uint;
489 tex->is_array = false;
490 tex->coord_components = 2;
491 tex->texture = nir_deref_var_create(tex, sampler);
492 tex->sampler = NULL;
493
494 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
495 nir_builder_instr_insert(b, &tex->instr);
496
497 return &tex->dest.ssa;
498 }
499
500
501 static nir_ssa_def *
build_nir_buffer_fetch(struct nir_builder * b,struct radv_device * device,nir_ssa_def * tex_pos)502 build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
503 nir_ssa_def *tex_pos)
504 {
505 const struct glsl_type *sampler_type =
506 glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
507 nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
508 sampler_type, "s_tex");
509 sampler->data.descriptor_set = 0;
510 sampler->data.binding = 0;
511
512 nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
513 width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
514 width->num_components = 1;
515 nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
516 nir_builder_instr_insert(b, &width->instr);
517
518 nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
519 nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
520 pos_y = nir_imul(b, pos_y, &width->dest.ssa);
521 pos_x = nir_iadd(b, pos_x, pos_y);
522 //pos_x = nir_iadd(b, pos_x, nir_imm_int(b, 100000));
523
524 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);
525 tex->sampler_dim = GLSL_SAMPLER_DIM_BUF;
526 tex->op = nir_texop_txf;
527 tex->src[0].src_type = nir_tex_src_coord;
528 tex->src[0].src = nir_src_for_ssa(pos_x);
529 tex->dest_type = nir_type_uint;
530 tex->is_array = false;
531 tex->coord_components = 1;
532 tex->texture = nir_deref_var_create(tex, sampler);
533 tex->sampler = NULL;
534
535 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
536 nir_builder_instr_insert(b, &tex->instr);
537
538 return &tex->dest.ssa;
539 }
540
541 static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
542 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
543 .vertexBindingDescriptionCount = 1,
544 .pVertexBindingDescriptions = (VkVertexInputBindingDescription[]) {
545 {
546 .binding = 0,
547 .stride = 4 * sizeof(float),
548 .inputRate = VK_VERTEX_INPUT_RATE_VERTEX
549 },
550 },
551 .vertexAttributeDescriptionCount = 2,
552 .pVertexAttributeDescriptions = (VkVertexInputAttributeDescription[]) {
553 {
554 /* Position */
555 .location = 0,
556 .binding = 0,
557 .format = VK_FORMAT_R32G32_SFLOAT,
558 .offset = 0
559 },
560 {
561 /* Texture Coordinate */
562 .location = 1,
563 .binding = 0,
564 .format = VK_FORMAT_R32G32_SFLOAT,
565 .offset = 8
566 },
567 },
568 };
569
570 static nir_shader *
build_nir_copy_fragment_shader(struct radv_device * device,texel_fetch_build_func txf_func,const char * name)571 build_nir_copy_fragment_shader(struct radv_device *device,
572 texel_fetch_build_func txf_func, const char* name)
573 {
574 const struct glsl_type *vec4 = glsl_vec4_type();
575 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
576 nir_builder b;
577
578 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
579 b.shader->info->name = ralloc_strdup(b.shader, name);
580
581 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
582 vec2, "v_tex_pos");
583 tex_pos_in->data.location = VARYING_SLOT_VAR0;
584
585 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
586 vec4, "f_color");
587 color_out->data.location = FRAG_RESULT_DATA0;
588
589 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
590 unsigned swiz[4] = { 0, 1 };
591 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
592
593 nir_ssa_def *color = txf_func(&b, device, tex_pos);
594 nir_store_var(&b, color_out, color, 0xf);
595
596 return b.shader;
597 }
598
599 static nir_shader *
build_nir_copy_fragment_shader_depth(struct radv_device * device,texel_fetch_build_func txf_func,const char * name)600 build_nir_copy_fragment_shader_depth(struct radv_device *device,
601 texel_fetch_build_func txf_func, const char* name)
602 {
603 const struct glsl_type *vec4 = glsl_vec4_type();
604 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
605 nir_builder b;
606
607 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
608 b.shader->info->name = ralloc_strdup(b.shader, name);
609
610 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
611 vec2, "v_tex_pos");
612 tex_pos_in->data.location = VARYING_SLOT_VAR0;
613
614 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
615 vec4, "f_color");
616 color_out->data.location = FRAG_RESULT_DEPTH;
617
618 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
619 unsigned swiz[4] = { 0, 1 };
620 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
621
622 nir_ssa_def *color = txf_func(&b, device, tex_pos);
623 nir_store_var(&b, color_out, color, 0x1);
624
625 return b.shader;
626 }
627
628 static nir_shader *
build_nir_copy_fragment_shader_stencil(struct radv_device * device,texel_fetch_build_func txf_func,const char * name)629 build_nir_copy_fragment_shader_stencil(struct radv_device *device,
630 texel_fetch_build_func txf_func, const char* name)
631 {
632 const struct glsl_type *vec4 = glsl_vec4_type();
633 const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
634 nir_builder b;
635
636 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
637 b.shader->info->name = ralloc_strdup(b.shader, name);
638
639 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
640 vec2, "v_tex_pos");
641 tex_pos_in->data.location = VARYING_SLOT_VAR0;
642
643 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
644 vec4, "f_color");
645 color_out->data.location = FRAG_RESULT_STENCIL;
646
647 nir_ssa_def *pos_int = nir_f2i(&b, nir_load_var(&b, tex_pos_in));
648 unsigned swiz[4] = { 0, 1 };
649 nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
650
651 nir_ssa_def *color = txf_func(&b, device, tex_pos);
652 nir_store_var(&b, color_out, color, 0x1);
653
654 return b.shader;
655 }
656
657 void
radv_device_finish_meta_blit2d_state(struct radv_device * device)658 radv_device_finish_meta_blit2d_state(struct radv_device *device)
659 {
660 for(unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
661 if (device->meta_state.blit2d.render_passes[j]) {
662 radv_DestroyRenderPass(radv_device_to_handle(device),
663 device->meta_state.blit2d.render_passes[j],
664 &device->meta_state.alloc);
665 }
666 }
667
668 radv_DestroyRenderPass(radv_device_to_handle(device),
669 device->meta_state.blit2d.depth_only_rp,
670 &device->meta_state.alloc);
671 radv_DestroyRenderPass(radv_device_to_handle(device),
672 device->meta_state.blit2d.stencil_only_rp,
673 &device->meta_state.alloc);
674
675 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
676 if (device->meta_state.blit2d.p_layouts[src]) {
677 radv_DestroyPipelineLayout(radv_device_to_handle(device),
678 device->meta_state.blit2d.p_layouts[src],
679 &device->meta_state.alloc);
680 }
681
682 if (device->meta_state.blit2d.ds_layouts[src]) {
683 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
684 device->meta_state.blit2d.ds_layouts[src],
685 &device->meta_state.alloc);
686 }
687
688 for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
689 if (device->meta_state.blit2d.pipelines[src][j]) {
690 radv_DestroyPipeline(radv_device_to_handle(device),
691 device->meta_state.blit2d.pipelines[src][j],
692 &device->meta_state.alloc);
693 }
694 }
695
696 radv_DestroyPipeline(radv_device_to_handle(device),
697 device->meta_state.blit2d.depth_only_pipeline[src],
698 &device->meta_state.alloc);
699 radv_DestroyPipeline(radv_device_to_handle(device),
700 device->meta_state.blit2d.stencil_only_pipeline[src],
701 &device->meta_state.alloc);
702 }
703 }
704
705 static VkResult
blit2d_init_color_pipeline(struct radv_device * device,enum blit2d_src_type src_type,VkFormat format)706 blit2d_init_color_pipeline(struct radv_device *device,
707 enum blit2d_src_type src_type,
708 VkFormat format)
709 {
710 VkResult result;
711 unsigned fs_key = radv_format_meta_fs_key(format);
712 const char *name;
713
714 texel_fetch_build_func src_func;
715 switch(src_type) {
716 case BLIT2D_SRC_TYPE_IMAGE:
717 src_func = build_nir_texel_fetch;
718 name = "meta_blit2d_image_fs";
719 break;
720 case BLIT2D_SRC_TYPE_BUFFER:
721 src_func = build_nir_buffer_fetch;
722 name = "meta_blit2d_buffer_fs";
723 break;
724 default:
725 unreachable("unknown blit src type\n");
726 break;
727 }
728
729 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
730 struct radv_shader_module fs = { .nir = NULL };
731
732
733 fs.nir = build_nir_copy_fragment_shader(device, src_func, name);
734 vi_create_info = &normal_vi_create_info;
735
736 struct radv_shader_module vs = {
737 .nir = build_nir_vertex_shader(),
738 };
739
740 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
741 {
742 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
743 .stage = VK_SHADER_STAGE_VERTEX_BIT,
744 .module = radv_shader_module_to_handle(&vs),
745 .pName = "main",
746 .pSpecializationInfo = NULL
747 }, {
748 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
749 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
750 .module = radv_shader_module_to_handle(&fs),
751 .pName = "main",
752 .pSpecializationInfo = NULL
753 },
754 };
755
756 if (!device->meta_state.blit2d.render_passes[fs_key]) {
757 result = radv_CreateRenderPass(radv_device_to_handle(device),
758 &(VkRenderPassCreateInfo) {
759 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
760 .attachmentCount = 1,
761 .pAttachments = &(VkAttachmentDescription) {
762 .format = format,
763 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
764 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
765 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
766 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
767 },
768 .subpassCount = 1,
769 .pSubpasses = &(VkSubpassDescription) {
770 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
771 .inputAttachmentCount = 0,
772 .colorAttachmentCount = 1,
773 .pColorAttachments = &(VkAttachmentReference) {
774 .attachment = 0,
775 .layout = VK_IMAGE_LAYOUT_GENERAL,
776 },
777 .pResolveAttachments = NULL,
778 .pDepthStencilAttachment = &(VkAttachmentReference) {
779 .attachment = VK_ATTACHMENT_UNUSED,
780 .layout = VK_IMAGE_LAYOUT_GENERAL,
781 },
782 .preserveAttachmentCount = 1,
783 .pPreserveAttachments = (uint32_t[]) { 0 },
784 },
785 .dependencyCount = 0,
786 }, &device->meta_state.alloc, &device->meta_state.blit2d.render_passes[fs_key]);
787 }
788
789 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
790 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
791 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
792 .pStages = pipeline_shader_stages,
793 .pVertexInputState = vi_create_info,
794 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
795 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
796 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
797 .primitiveRestartEnable = false,
798 },
799 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
800 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
801 .viewportCount = 0,
802 .scissorCount = 0,
803 },
804 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
805 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
806 .rasterizerDiscardEnable = false,
807 .polygonMode = VK_POLYGON_MODE_FILL,
808 .cullMode = VK_CULL_MODE_NONE,
809 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
810 },
811 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
812 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
813 .rasterizationSamples = 1,
814 .sampleShadingEnable = false,
815 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
816 },
817 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
818 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
819 .attachmentCount = 1,
820 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
821 { .colorWriteMask =
822 VK_COLOR_COMPONENT_A_BIT |
823 VK_COLOR_COMPONENT_R_BIT |
824 VK_COLOR_COMPONENT_G_BIT |
825 VK_COLOR_COMPONENT_B_BIT },
826 }
827 },
828 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
829 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
830 .dynamicStateCount = 7,
831 .pDynamicStates = (VkDynamicState[]) {
832 VK_DYNAMIC_STATE_LINE_WIDTH,
833 VK_DYNAMIC_STATE_DEPTH_BIAS,
834 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
835 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
836 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
837 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
838 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
839 },
840 },
841 .flags = 0,
842 .layout = device->meta_state.blit2d.p_layouts[src_type],
843 .renderPass = device->meta_state.blit2d.render_passes[fs_key],
844 .subpass = 0,
845 };
846
847 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
848 .use_rectlist = true
849 };
850
851 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
852 radv_pipeline_cache_to_handle(&device->meta_state.cache),
853 &vk_pipeline_info, &radv_pipeline_info,
854 &device->meta_state.alloc,
855 &device->meta_state.blit2d.pipelines[src_type][fs_key]);
856
857
858 ralloc_free(vs.nir);
859 ralloc_free(fs.nir);
860
861 return result;
862 }
863
864 static VkResult
blit2d_init_depth_only_pipeline(struct radv_device * device,enum blit2d_src_type src_type)865 blit2d_init_depth_only_pipeline(struct radv_device *device,
866 enum blit2d_src_type src_type)
867 {
868 VkResult result;
869 const char *name;
870
871 texel_fetch_build_func src_func;
872 switch(src_type) {
873 case BLIT2D_SRC_TYPE_IMAGE:
874 src_func = build_nir_texel_fetch;
875 name = "meta_blit2d_depth_image_fs";
876 break;
877 case BLIT2D_SRC_TYPE_BUFFER:
878 src_func = build_nir_buffer_fetch;
879 name = "meta_blit2d_depth_buffer_fs";
880 break;
881 default:
882 unreachable("unknown blit src type\n");
883 break;
884 }
885
886 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
887 struct radv_shader_module fs = { .nir = NULL };
888
889 fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name);
890 vi_create_info = &normal_vi_create_info;
891
892 struct radv_shader_module vs = {
893 .nir = build_nir_vertex_shader(),
894 };
895
896 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
897 {
898 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
899 .stage = VK_SHADER_STAGE_VERTEX_BIT,
900 .module = radv_shader_module_to_handle(&vs),
901 .pName = "main",
902 .pSpecializationInfo = NULL
903 }, {
904 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
905 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
906 .module = radv_shader_module_to_handle(&fs),
907 .pName = "main",
908 .pSpecializationInfo = NULL
909 },
910 };
911
912 if (!device->meta_state.blit2d.depth_only_rp) {
913 result = radv_CreateRenderPass(radv_device_to_handle(device),
914 &(VkRenderPassCreateInfo) {
915 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
916 .attachmentCount = 1,
917 .pAttachments = &(VkAttachmentDescription) {
918 .format = 0,
919 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
920 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
921 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
922 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
923 },
924 .subpassCount = 1,
925 .pSubpasses = &(VkSubpassDescription) {
926 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
927 .inputAttachmentCount = 0,
928 .colorAttachmentCount = 0,
929 .pColorAttachments = NULL,
930 .pResolveAttachments = NULL,
931 .pDepthStencilAttachment = &(VkAttachmentReference) {
932 .attachment = 0,
933 .layout = VK_IMAGE_LAYOUT_GENERAL,
934 },
935 .preserveAttachmentCount = 1,
936 .pPreserveAttachments = (uint32_t[]) { 0 },
937 },
938 .dependencyCount = 0,
939 }, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp);
940 }
941
942 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
943 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
944 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
945 .pStages = pipeline_shader_stages,
946 .pVertexInputState = vi_create_info,
947 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
948 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
949 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
950 .primitiveRestartEnable = false,
951 },
952 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
953 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
954 .viewportCount = 0,
955 .scissorCount = 0,
956 },
957 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
958 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
959 .rasterizerDiscardEnable = false,
960 .polygonMode = VK_POLYGON_MODE_FILL,
961 .cullMode = VK_CULL_MODE_NONE,
962 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
963 },
964 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
965 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
966 .rasterizationSamples = 1,
967 .sampleShadingEnable = false,
968 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
969 },
970 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
971 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
972 .attachmentCount = 0,
973 .pAttachments = NULL,
974 },
975 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
976 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
977 .depthTestEnable = true,
978 .depthWriteEnable = true,
979 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
980 },
981 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
982 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
983 .dynamicStateCount = 7,
984 .pDynamicStates = (VkDynamicState[]) {
985 VK_DYNAMIC_STATE_LINE_WIDTH,
986 VK_DYNAMIC_STATE_DEPTH_BIAS,
987 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
988 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
989 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
990 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
991 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
992 },
993 },
994 .flags = 0,
995 .layout = device->meta_state.blit2d.p_layouts[src_type],
996 .renderPass = device->meta_state.blit2d.depth_only_rp,
997 .subpass = 0,
998 };
999
1000 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1001 .use_rectlist = true
1002 };
1003
1004 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1005 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1006 &vk_pipeline_info, &radv_pipeline_info,
1007 &device->meta_state.alloc,
1008 &device->meta_state.blit2d.depth_only_pipeline[src_type]);
1009
1010
1011 ralloc_free(vs.nir);
1012 ralloc_free(fs.nir);
1013
1014 return result;
1015 }
1016
1017 static VkResult
blit2d_init_stencil_only_pipeline(struct radv_device * device,enum blit2d_src_type src_type)1018 blit2d_init_stencil_only_pipeline(struct radv_device *device,
1019 enum blit2d_src_type src_type)
1020 {
1021 VkResult result;
1022 const char *name;
1023
1024 texel_fetch_build_func src_func;
1025 switch(src_type) {
1026 case BLIT2D_SRC_TYPE_IMAGE:
1027 src_func = build_nir_texel_fetch;
1028 name = "meta_blit2d_stencil_image_fs";
1029 break;
1030 case BLIT2D_SRC_TYPE_BUFFER:
1031 src_func = build_nir_buffer_fetch;
1032 name = "meta_blit2d_stencil_buffer_fs";
1033 break;
1034 default:
1035 unreachable("unknown blit src type\n");
1036 break;
1037 }
1038
1039 const VkPipelineVertexInputStateCreateInfo *vi_create_info;
1040 struct radv_shader_module fs = { .nir = NULL };
1041
1042 fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name);
1043 vi_create_info = &normal_vi_create_info;
1044
1045 struct radv_shader_module vs = {
1046 .nir = build_nir_vertex_shader(),
1047 };
1048
1049 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1050 {
1051 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1052 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1053 .module = radv_shader_module_to_handle(&vs),
1054 .pName = "main",
1055 .pSpecializationInfo = NULL
1056 }, {
1057 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1058 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1059 .module = radv_shader_module_to_handle(&fs),
1060 .pName = "main",
1061 .pSpecializationInfo = NULL
1062 },
1063 };
1064
1065 if (!device->meta_state.blit2d.stencil_only_rp) {
1066 result = radv_CreateRenderPass(radv_device_to_handle(device),
1067 &(VkRenderPassCreateInfo) {
1068 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1069 .attachmentCount = 1,
1070 .pAttachments = &(VkAttachmentDescription) {
1071 .format = 0,
1072 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1073 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1074 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1075 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1076 },
1077 .subpassCount = 1,
1078 .pSubpasses = &(VkSubpassDescription) {
1079 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1080 .inputAttachmentCount = 0,
1081 .colorAttachmentCount = 0,
1082 .pColorAttachments = NULL,
1083 .pResolveAttachments = NULL,
1084 .pDepthStencilAttachment = &(VkAttachmentReference) {
1085 .attachment = 0,
1086 .layout = VK_IMAGE_LAYOUT_GENERAL,
1087 },
1088 .preserveAttachmentCount = 1,
1089 .pPreserveAttachments = (uint32_t[]) { 0 },
1090 },
1091 .dependencyCount = 0,
1092 }, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp);
1093 }
1094
1095 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1096 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1097 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1098 .pStages = pipeline_shader_stages,
1099 .pVertexInputState = vi_create_info,
1100 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1101 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1102 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1103 .primitiveRestartEnable = false,
1104 },
1105 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1106 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1107 .viewportCount = 0,
1108 .scissorCount = 0,
1109 },
1110 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1111 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1112 .rasterizerDiscardEnable = false,
1113 .polygonMode = VK_POLYGON_MODE_FILL,
1114 .cullMode = VK_CULL_MODE_NONE,
1115 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1116 },
1117 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1118 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1119 .rasterizationSamples = 1,
1120 .sampleShadingEnable = false,
1121 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1122 },
1123 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1124 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1125 .attachmentCount = 0,
1126 .pAttachments = NULL,
1127 },
1128 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1129 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1130 .depthTestEnable = false,
1131 .depthWriteEnable = false,
1132 .stencilTestEnable = true,
1133 .front = {
1134 .failOp = VK_STENCIL_OP_REPLACE,
1135 .passOp = VK_STENCIL_OP_REPLACE,
1136 .depthFailOp = VK_STENCIL_OP_REPLACE,
1137 .compareOp = VK_COMPARE_OP_ALWAYS,
1138 .compareMask = 0xff,
1139 .writeMask = 0xff,
1140 .reference = 0
1141 },
1142 .back = {
1143 .failOp = VK_STENCIL_OP_REPLACE,
1144 .passOp = VK_STENCIL_OP_REPLACE,
1145 .depthFailOp = VK_STENCIL_OP_REPLACE,
1146 .compareOp = VK_COMPARE_OP_ALWAYS,
1147 .compareMask = 0xff,
1148 .writeMask = 0xff,
1149 .reference = 0
1150 },
1151 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1152 },
1153 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1154 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1155 .dynamicStateCount = 4,
1156 .pDynamicStates = (VkDynamicState[]) {
1157 VK_DYNAMIC_STATE_LINE_WIDTH,
1158 VK_DYNAMIC_STATE_DEPTH_BIAS,
1159 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1160 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1161 },
1162 },
1163 .flags = 0,
1164 .layout = device->meta_state.blit2d.p_layouts[src_type],
1165 .renderPass = device->meta_state.blit2d.stencil_only_rp,
1166 .subpass = 0,
1167 };
1168
1169 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1170 .use_rectlist = true
1171 };
1172
1173 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1174 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1175 &vk_pipeline_info, &radv_pipeline_info,
1176 &device->meta_state.alloc,
1177 &device->meta_state.blit2d.stencil_only_pipeline[src_type]);
1178
1179
1180 ralloc_free(vs.nir);
1181 ralloc_free(fs.nir);
1182
1183 return result;
1184 }
1185
1186 static VkFormat pipeline_formats[] = {
1187 VK_FORMAT_R8G8B8A8_UNORM,
1188 VK_FORMAT_R8G8B8A8_UINT,
1189 VK_FORMAT_R8G8B8A8_SINT,
1190 VK_FORMAT_R16G16B16A16_UNORM,
1191 VK_FORMAT_R16G16B16A16_SNORM,
1192 VK_FORMAT_R16G16B16A16_UINT,
1193 VK_FORMAT_R16G16B16A16_SINT,
1194 VK_FORMAT_R32_SFLOAT,
1195 VK_FORMAT_R32G32_SFLOAT,
1196 VK_FORMAT_R32G32B32A32_SFLOAT
1197 };
1198
1199 VkResult
radv_device_init_meta_blit2d_state(struct radv_device * device)1200 radv_device_init_meta_blit2d_state(struct radv_device *device)
1201 {
1202 VkResult result;
1203
1204 zero(device->meta_state.blit2d);
1205
1206 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1207 &(VkDescriptorSetLayoutCreateInfo) {
1208 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1209 .bindingCount = 1,
1210 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1211 {
1212 .binding = 0,
1213 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
1214 .descriptorCount = 1,
1215 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1216 .pImmutableSamplers = NULL
1217 },
1218 }
1219 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1220 if (result != VK_SUCCESS)
1221 goto fail;
1222
1223 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1224 &(VkPipelineLayoutCreateInfo) {
1225 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1226 .setLayoutCount = 1,
1227 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE],
1228 },
1229 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_IMAGE]);
1230 if (result != VK_SUCCESS)
1231 goto fail;
1232
1233 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1234 &(VkDescriptorSetLayoutCreateInfo) {
1235 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1236 .bindingCount = 1,
1237 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1238 {
1239 .binding = 0,
1240 .descriptorType = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
1241 .descriptorCount = 1,
1242 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1243 .pImmutableSamplers = NULL
1244 },
1245 }
1246 }, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1247 if (result != VK_SUCCESS)
1248 goto fail;
1249
1250 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4};
1251 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1252 &(VkPipelineLayoutCreateInfo) {
1253 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1254 .setLayoutCount = 1,
1255 .pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_BUFFER],
1256 .pushConstantRangeCount = 1,
1257 .pPushConstantRanges = &push_constant_range,
1258 },
1259 &device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_BUFFER]);
1260 if (result != VK_SUCCESS)
1261 goto fail;
1262
1263 for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
1264 for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
1265 result = blit2d_init_color_pipeline(device, src, pipeline_formats[j]);
1266 if (result != VK_SUCCESS)
1267 goto fail;
1268 }
1269
1270 result = blit2d_init_depth_only_pipeline(device, src);
1271 if (result != VK_SUCCESS)
1272 goto fail;
1273
1274 result = blit2d_init_stencil_only_pipeline(device, src);
1275 if (result != VK_SUCCESS)
1276 goto fail;
1277 }
1278
1279 return VK_SUCCESS;
1280
1281 fail:
1282 radv_device_finish_meta_blit2d_state(device);
1283 return result;
1284 }
1285