1 //===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the CriticalAntiDepBreaker class, which
11 // implements register anti-dependence breaking along a blocks
12 // critical path during post-RA scheduler.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #define DEBUG_TYPE "post-RA-sched"
17 #include "CriticalAntiDepBreaker.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26
27 using namespace llvm;
28
29 CriticalAntiDepBreaker::
CriticalAntiDepBreaker(MachineFunction & MFi,const RegisterClassInfo & RCI)30 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) :
31 AntiDepBreaker(), MF(MFi),
32 MRI(MF.getRegInfo()),
33 TII(MF.getTarget().getInstrInfo()),
34 TRI(MF.getTarget().getRegisterInfo()),
35 RegClassInfo(RCI),
36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)),
37 KillIndices(TRI->getNumRegs(), 0),
38 DefIndices(TRI->getNumRegs(), 0) {}
39
~CriticalAntiDepBreaker()40 CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
41 }
42
StartBlock(MachineBasicBlock * BB)43 void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
44 const unsigned BBSize = BB->size();
45 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
46 // Clear out the register class data.
47 Classes[i] = static_cast<const TargetRegisterClass *>(0);
48
49 // Initialize the indices to indicate that no registers are live.
50 KillIndices[i] = ~0u;
51 DefIndices[i] = BBSize;
52 }
53
54 // Clear "do not change" set.
55 KeepRegs.clear();
56
57 bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
58
59 // Determine the live-out physregs for this block.
60 if (IsReturnBlock) {
61 // In a return block, examine the function live-out regs.
62 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
63 E = MRI.liveout_end(); I != E; ++I) {
64 unsigned Reg = *I;
65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
66 KillIndices[Reg] = BB->size();
67 DefIndices[Reg] = ~0u;
68
69 // Repeat, for all aliases.
70 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
71 unsigned AliasReg = *Alias;
72 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
73 KillIndices[AliasReg] = BB->size();
74 DefIndices[AliasReg] = ~0u;
75 }
76 }
77 }
78
79 // In a non-return block, examine the live-in regs of all successors.
80 // Note a return block can have successors if the return instruction is
81 // predicated.
82 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
83 SE = BB->succ_end(); SI != SE; ++SI)
84 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
85 E = (*SI)->livein_end(); I != E; ++I) {
86 unsigned Reg = *I;
87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
88 KillIndices[Reg] = BB->size();
89 DefIndices[Reg] = ~0u;
90
91 // Repeat, for all aliases.
92 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
93 unsigned AliasReg = *Alias;
94 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
95 KillIndices[AliasReg] = BB->size();
96 DefIndices[AliasReg] = ~0u;
97 }
98 }
99
100 // Mark live-out callee-saved registers. In a return block this is
101 // all callee-saved registers. In non-return this is any
102 // callee-saved register that is not saved in the prolog.
103 const MachineFrameInfo *MFI = MF.getFrameInfo();
104 BitVector Pristine = MFI->getPristineRegs(BB);
105 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
106 unsigned Reg = *I;
107 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
108 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
109 KillIndices[Reg] = BB->size();
110 DefIndices[Reg] = ~0u;
111
112 // Repeat, for all aliases.
113 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
114 unsigned AliasReg = *Alias;
115 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
116 KillIndices[AliasReg] = BB->size();
117 DefIndices[AliasReg] = ~0u;
118 }
119 }
120 }
121
FinishBlock()122 void CriticalAntiDepBreaker::FinishBlock() {
123 RegRefs.clear();
124 KeepRegs.clear();
125 }
126
Observe(MachineInstr * MI,unsigned Count,unsigned InsertPosIndex)127 void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
128 unsigned InsertPosIndex) {
129 if (MI->isDebugValue())
130 return;
131 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
132
133 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
134 if (KillIndices[Reg] != ~0u) {
135 // If Reg is currently live, then mark that it can't be renamed as
136 // we don't know the extent of its live-range anymore (now that it
137 // has been scheduled).
138 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
139 KillIndices[Reg] = Count;
140 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
141 // Any register which was defined within the previous scheduling region
142 // may have been rescheduled and its lifetime may overlap with registers
143 // in ways not reflected in our current liveness state. For each such
144 // register, adjust the liveness state to be conservatively correct.
145 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
146
147 // Move the def index to the end of the previous region, to reflect
148 // that the def could theoretically have been scheduled at the end.
149 DefIndices[Reg] = InsertPosIndex;
150 }
151 }
152
153 PrescanInstruction(MI);
154 ScanInstruction(MI, Count);
155 }
156
157 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
158 /// critical path.
CriticalPathStep(const SUnit * SU)159 static const SDep *CriticalPathStep(const SUnit *SU) {
160 const SDep *Next = 0;
161 unsigned NextDepth = 0;
162 // Find the predecessor edge with the greatest depth.
163 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
164 P != PE; ++P) {
165 const SUnit *PredSU = P->getSUnit();
166 unsigned PredLatency = P->getLatency();
167 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
168 // In the case of a latency tie, prefer an anti-dependency edge over
169 // other types of edges.
170 if (NextDepth < PredTotalLatency ||
171 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
172 NextDepth = PredTotalLatency;
173 Next = &*P;
174 }
175 }
176 return Next;
177 }
178
PrescanInstruction(MachineInstr * MI)179 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
180 // It's not safe to change register allocation for source operands of
181 // that have special allocation requirements. Also assume all registers
182 // used in a call must not be changed (ABI).
183 // FIXME: The issue with predicated instruction is more complex. We are being
184 // conservative here because the kill markers cannot be trusted after
185 // if-conversion:
186 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
187 // ...
188 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
189 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
190 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
191 //
192 // The first R6 kill is not really a kill since it's killed by a predicated
193 // instruction which may not be executed. The second R6 def may or may not
194 // re-define R6 so it's not safe to change it since the last R6 use cannot be
195 // changed.
196 bool Special = MI->getDesc().isCall() ||
197 MI->getDesc().hasExtraSrcRegAllocReq() ||
198 TII->isPredicated(MI);
199
200 // Scan the register operands for this instruction and update
201 // Classes and RegRefs.
202 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
203 MachineOperand &MO = MI->getOperand(i);
204 if (!MO.isReg()) continue;
205 unsigned Reg = MO.getReg();
206 if (Reg == 0) continue;
207 const TargetRegisterClass *NewRC = 0;
208
209 if (i < MI->getDesc().getNumOperands())
210 NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
211
212 // For now, only allow the register to be changed if its register
213 // class is consistent across all uses.
214 if (!Classes[Reg] && NewRC)
215 Classes[Reg] = NewRC;
216 else if (!NewRC || Classes[Reg] != NewRC)
217 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
218
219 // Now check for aliases.
220 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
221 // If an alias of the reg is used during the live range, give up.
222 // Note that this allows us to skip checking if AntiDepReg
223 // overlaps with any of the aliases, among other things.
224 unsigned AliasReg = *Alias;
225 if (Classes[AliasReg]) {
226 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
227 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
228 }
229 }
230
231 // If we're still willing to consider this register, note the reference.
232 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
233 RegRefs.insert(std::make_pair(Reg, &MO));
234
235 if (MO.isUse() && Special) {
236 if (KeepRegs.insert(Reg)) {
237 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
238 *Subreg; ++Subreg)
239 KeepRegs.insert(*Subreg);
240 }
241 }
242 }
243 }
244
ScanInstruction(MachineInstr * MI,unsigned Count)245 void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
246 unsigned Count) {
247 // Update liveness.
248 // Proceding upwards, registers that are defed but not used in this
249 // instruction are now dead.
250
251 if (!TII->isPredicated(MI)) {
252 // Predicated defs are modeled as read + write, i.e. similar to two
253 // address updates.
254 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
255 MachineOperand &MO = MI->getOperand(i);
256 if (!MO.isReg()) continue;
257 unsigned Reg = MO.getReg();
258 if (Reg == 0) continue;
259 if (!MO.isDef()) continue;
260 // Ignore two-addr defs.
261 if (MI->isRegTiedToUseOperand(i)) continue;
262
263 DefIndices[Reg] = Count;
264 KillIndices[Reg] = ~0u;
265 assert(((KillIndices[Reg] == ~0u) !=
266 (DefIndices[Reg] == ~0u)) &&
267 "Kill and Def maps aren't consistent for Reg!");
268 KeepRegs.erase(Reg);
269 Classes[Reg] = 0;
270 RegRefs.erase(Reg);
271 // Repeat, for all subregs.
272 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
273 *Subreg; ++Subreg) {
274 unsigned SubregReg = *Subreg;
275 DefIndices[SubregReg] = Count;
276 KillIndices[SubregReg] = ~0u;
277 KeepRegs.erase(SubregReg);
278 Classes[SubregReg] = 0;
279 RegRefs.erase(SubregReg);
280 }
281 // Conservatively mark super-registers as unusable.
282 for (const unsigned *Super = TRI->getSuperRegisters(Reg);
283 *Super; ++Super) {
284 unsigned SuperReg = *Super;
285 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
286 }
287 }
288 }
289 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
290 MachineOperand &MO = MI->getOperand(i);
291 if (!MO.isReg()) continue;
292 unsigned Reg = MO.getReg();
293 if (Reg == 0) continue;
294 if (!MO.isUse()) continue;
295
296 const TargetRegisterClass *NewRC = 0;
297 if (i < MI->getDesc().getNumOperands())
298 NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
299
300 // For now, only allow the register to be changed if its register
301 // class is consistent across all uses.
302 if (!Classes[Reg] && NewRC)
303 Classes[Reg] = NewRC;
304 else if (!NewRC || Classes[Reg] != NewRC)
305 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
306
307 RegRefs.insert(std::make_pair(Reg, &MO));
308
309 // It wasn't previously live but now it is, this is a kill.
310 if (KillIndices[Reg] == ~0u) {
311 KillIndices[Reg] = Count;
312 DefIndices[Reg] = ~0u;
313 assert(((KillIndices[Reg] == ~0u) !=
314 (DefIndices[Reg] == ~0u)) &&
315 "Kill and Def maps aren't consistent for Reg!");
316 }
317 // Repeat, for all aliases.
318 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
319 unsigned AliasReg = *Alias;
320 if (KillIndices[AliasReg] == ~0u) {
321 KillIndices[AliasReg] = Count;
322 DefIndices[AliasReg] = ~0u;
323 }
324 }
325 }
326 }
327
328 // Check all machine operands that reference the antidependent register and must
329 // be replaced by NewReg. Return true if any of their parent instructions may
330 // clobber the new register.
331 //
332 // Note: AntiDepReg may be referenced by a two-address instruction such that
333 // it's use operand is tied to a def operand. We guard against the case in which
334 // the two-address instruction also defines NewReg, as may happen with
335 // pre/postincrement loads. In this case, both the use and def operands are in
336 // RegRefs because the def is inserted by PrescanInstruction and not erased
337 // during ScanInstruction. So checking for an instructions with definitions of
338 // both NewReg and AntiDepReg covers it.
339 bool
isNewRegClobberedByRefs(RegRefIter RegRefBegin,RegRefIter RegRefEnd,unsigned NewReg)340 CriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin,
341 RegRefIter RegRefEnd,
342 unsigned NewReg)
343 {
344 for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) {
345 MachineOperand *RefOper = I->second;
346
347 // Don't allow the instruction defining AntiDepReg to earlyclobber its
348 // operands, in case they may be assigned to NewReg. In this case antidep
349 // breaking must fail, but it's too rare to bother optimizing.
350 if (RefOper->isDef() && RefOper->isEarlyClobber())
351 return true;
352
353 // Handle cases in which this instructions defines NewReg.
354 MachineInstr *MI = RefOper->getParent();
355 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
356 const MachineOperand &CheckOper = MI->getOperand(i);
357
358 if (!CheckOper.isReg() || !CheckOper.isDef() ||
359 CheckOper.getReg() != NewReg)
360 continue;
361
362 // Don't allow the instruction to define NewReg and AntiDepReg.
363 // When AntiDepReg is renamed it will be an illegal op.
364 if (RefOper->isDef())
365 return true;
366
367 // Don't allow an instruction using AntiDepReg to be earlyclobbered by
368 // NewReg
369 if (CheckOper.isEarlyClobber())
370 return true;
371
372 // Don't allow inline asm to define NewReg at all. Who know what it's
373 // doing with it.
374 if (MI->isInlineAsm())
375 return true;
376 }
377 }
378 return false;
379 }
380
381 unsigned
findSuitableFreeRegister(RegRefIter RegRefBegin,RegRefIter RegRefEnd,unsigned AntiDepReg,unsigned LastNewReg,const TargetRegisterClass * RC)382 CriticalAntiDepBreaker::findSuitableFreeRegister(RegRefIter RegRefBegin,
383 RegRefIter RegRefEnd,
384 unsigned AntiDepReg,
385 unsigned LastNewReg,
386 const TargetRegisterClass *RC)
387 {
388 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
389 for (unsigned i = 0; i != Order.size(); ++i) {
390 unsigned NewReg = Order[i];
391 // Don't replace a register with itself.
392 if (NewReg == AntiDepReg) continue;
393 // Don't replace a register with one that was recently used to repair
394 // an anti-dependence with this AntiDepReg, because that would
395 // re-introduce that anti-dependence.
396 if (NewReg == LastNewReg) continue;
397 // If any instructions that define AntiDepReg also define the NewReg, it's
398 // not suitable. For example, Instruction with multiple definitions can
399 // result in this condition.
400 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
401 // If NewReg is dead and NewReg's most recent def is not before
402 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
403 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))
404 && "Kill and Def maps aren't consistent for AntiDepReg!");
405 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
406 && "Kill and Def maps aren't consistent for NewReg!");
407 if (KillIndices[NewReg] != ~0u ||
408 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
409 KillIndices[AntiDepReg] > DefIndices[NewReg])
410 continue;
411 return NewReg;
412 }
413
414 // No registers are free and available!
415 return 0;
416 }
417
418 unsigned CriticalAntiDepBreaker::
BreakAntiDependencies(const std::vector<SUnit> & SUnits,MachineBasicBlock::iterator Begin,MachineBasicBlock::iterator End,unsigned InsertPosIndex,DbgValueVector & DbgValues)419 BreakAntiDependencies(const std::vector<SUnit>& SUnits,
420 MachineBasicBlock::iterator Begin,
421 MachineBasicBlock::iterator End,
422 unsigned InsertPosIndex,
423 DbgValueVector &DbgValues) {
424 // The code below assumes that there is at least one instruction,
425 // so just duck out immediately if the block is empty.
426 if (SUnits.empty()) return 0;
427
428 // Keep a map of the MachineInstr*'s back to the SUnit representing them.
429 // This is used for updating debug information.
430 DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
431
432 // Find the node at the bottom of the critical path.
433 const SUnit *Max = 0;
434 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
435 const SUnit *SU = &SUnits[i];
436 MISUnitMap[SU->getInstr()] = SU;
437 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
438 Max = SU;
439 }
440
441 #ifndef NDEBUG
442 {
443 DEBUG(dbgs() << "Critical path has total latency "
444 << (Max->getDepth() + Max->Latency) << "\n");
445 DEBUG(dbgs() << "Available regs:");
446 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
447 if (KillIndices[Reg] == ~0u)
448 DEBUG(dbgs() << " " << TRI->getName(Reg));
449 }
450 DEBUG(dbgs() << '\n');
451 }
452 #endif
453
454 // Track progress along the critical path through the SUnit graph as we walk
455 // the instructions.
456 const SUnit *CriticalPathSU = Max;
457 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
458
459 // Consider this pattern:
460 // A = ...
461 // ... = A
462 // A = ...
463 // ... = A
464 // A = ...
465 // ... = A
466 // A = ...
467 // ... = A
468 // There are three anti-dependencies here, and without special care,
469 // we'd break all of them using the same register:
470 // A = ...
471 // ... = A
472 // B = ...
473 // ... = B
474 // B = ...
475 // ... = B
476 // B = ...
477 // ... = B
478 // because at each anti-dependence, B is the first register that
479 // isn't A which is free. This re-introduces anti-dependencies
480 // at all but one of the original anti-dependencies that we were
481 // trying to break. To avoid this, keep track of the most recent
482 // register that each register was replaced with, avoid
483 // using it to repair an anti-dependence on the same register.
484 // This lets us produce this:
485 // A = ...
486 // ... = A
487 // B = ...
488 // ... = B
489 // C = ...
490 // ... = C
491 // B = ...
492 // ... = B
493 // This still has an anti-dependence on B, but at least it isn't on the
494 // original critical path.
495 //
496 // TODO: If we tracked more than one register here, we could potentially
497 // fix that remaining critical edge too. This is a little more involved,
498 // because unlike the most recent register, less recent registers should
499 // still be considered, though only if no other registers are available.
500 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
501
502 // Attempt to break anti-dependence edges on the critical path. Walk the
503 // instructions from the bottom up, tracking information about liveness
504 // as we go to help determine which registers are available.
505 unsigned Broken = 0;
506 unsigned Count = InsertPosIndex - 1;
507 for (MachineBasicBlock::iterator I = End, E = Begin;
508 I != E; --Count) {
509 MachineInstr *MI = --I;
510 if (MI->isDebugValue())
511 continue;
512
513 // Check if this instruction has a dependence on the critical path that
514 // is an anti-dependence that we may be able to break. If it is, set
515 // AntiDepReg to the non-zero register associated with the anti-dependence.
516 //
517 // We limit our attention to the critical path as a heuristic to avoid
518 // breaking anti-dependence edges that aren't going to significantly
519 // impact the overall schedule. There are a limited number of registers
520 // and we want to save them for the important edges.
521 //
522 // TODO: Instructions with multiple defs could have multiple
523 // anti-dependencies. The current code here only knows how to break one
524 // edge per instruction. Note that we'd have to be able to break all of
525 // the anti-dependencies in an instruction in order to be effective.
526 unsigned AntiDepReg = 0;
527 if (MI == CriticalPathMI) {
528 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
529 const SUnit *NextSU = Edge->getSUnit();
530
531 // Only consider anti-dependence edges.
532 if (Edge->getKind() == SDep::Anti) {
533 AntiDepReg = Edge->getReg();
534 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
535 if (!RegClassInfo.isAllocatable(AntiDepReg))
536 // Don't break anti-dependencies on non-allocatable registers.
537 AntiDepReg = 0;
538 else if (KeepRegs.count(AntiDepReg))
539 // Don't break anti-dependencies if an use down below requires
540 // this exact register.
541 AntiDepReg = 0;
542 else {
543 // If the SUnit has other dependencies on the SUnit that it
544 // anti-depends on, don't bother breaking the anti-dependency
545 // since those edges would prevent such units from being
546 // scheduled past each other regardless.
547 //
548 // Also, if there are dependencies on other SUnits with the
549 // same register as the anti-dependency, don't attempt to
550 // break it.
551 for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(),
552 PE = CriticalPathSU->Preds.end(); P != PE; ++P)
553 if (P->getSUnit() == NextSU ?
554 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
555 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
556 AntiDepReg = 0;
557 break;
558 }
559 }
560 }
561 CriticalPathSU = NextSU;
562 CriticalPathMI = CriticalPathSU->getInstr();
563 } else {
564 // We've reached the end of the critical path.
565 CriticalPathSU = 0;
566 CriticalPathMI = 0;
567 }
568 }
569
570 PrescanInstruction(MI);
571
572 // If MI's defs have a special allocation requirement, don't allow
573 // any def registers to be changed. Also assume all registers
574 // defined in a call must not be changed (ABI).
575 if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() ||
576 TII->isPredicated(MI))
577 // If this instruction's defs have special allocation requirement, don't
578 // break this anti-dependency.
579 AntiDepReg = 0;
580 else if (AntiDepReg) {
581 // If this instruction has a use of AntiDepReg, breaking it
582 // is invalid.
583 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
584 MachineOperand &MO = MI->getOperand(i);
585 if (!MO.isReg()) continue;
586 unsigned Reg = MO.getReg();
587 if (Reg == 0) continue;
588 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
589 AntiDepReg = 0;
590 break;
591 }
592 }
593 }
594
595 // Determine AntiDepReg's register class, if it is live and is
596 // consistently used within a single class.
597 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
598 assert((AntiDepReg == 0 || RC != NULL) &&
599 "Register should be live if it's causing an anti-dependence!");
600 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
601 AntiDepReg = 0;
602
603 // Look for a suitable register to use to break the anti-depenence.
604 //
605 // TODO: Instead of picking the first free register, consider which might
606 // be the best.
607 if (AntiDepReg != 0) {
608 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
609 std::multimap<unsigned, MachineOperand *>::iterator>
610 Range = RegRefs.equal_range(AntiDepReg);
611 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
612 AntiDepReg,
613 LastNewReg[AntiDepReg],
614 RC)) {
615 DEBUG(dbgs() << "Breaking anti-dependence edge on "
616 << TRI->getName(AntiDepReg)
617 << " with " << RegRefs.count(AntiDepReg) << " references"
618 << " using " << TRI->getName(NewReg) << "!\n");
619
620 // Update the references to the old register to refer to the new
621 // register.
622 for (std::multimap<unsigned, MachineOperand *>::iterator
623 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
624 Q->second->setReg(NewReg);
625 // If the SU for the instruction being updated has debug information
626 // related to the anti-dependency register, make sure to update that
627 // as well.
628 const SUnit *SU = MISUnitMap[Q->second->getParent()];
629 if (!SU) continue;
630 for (DbgValueVector::iterator DVI = DbgValues.begin(),
631 DVE = DbgValues.end(); DVI != DVE; ++DVI)
632 if (DVI->second == Q->second->getParent())
633 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
634 }
635
636 // We just went back in time and modified history; the
637 // liveness information for the anti-dependence reg is now
638 // inconsistent. Set the state as if it were dead.
639 Classes[NewReg] = Classes[AntiDepReg];
640 DefIndices[NewReg] = DefIndices[AntiDepReg];
641 KillIndices[NewReg] = KillIndices[AntiDepReg];
642 assert(((KillIndices[NewReg] == ~0u) !=
643 (DefIndices[NewReg] == ~0u)) &&
644 "Kill and Def maps aren't consistent for NewReg!");
645
646 Classes[AntiDepReg] = 0;
647 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
648 KillIndices[AntiDepReg] = ~0u;
649 assert(((KillIndices[AntiDepReg] == ~0u) !=
650 (DefIndices[AntiDepReg] == ~0u)) &&
651 "Kill and Def maps aren't consistent for AntiDepReg!");
652
653 RegRefs.erase(AntiDepReg);
654 LastNewReg[AntiDepReg] = NewReg;
655 ++Broken;
656 }
657 }
658
659 ScanInstruction(MI, Count);
660 }
661
662 return Broken;
663 }
664