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1//===- PPCRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13let Namespace = "PPC" in {
14def sub_lt : SubRegIndex;
15def sub_gt : SubRegIndex;
16def sub_eq : SubRegIndex;
17def sub_un : SubRegIndex;
18def sub_32 : SubRegIndex;
19}
20
21
22class PPCReg<string n> : Register<n> {
23  let Namespace = "PPC";
24}
25
26// We identify all our registers with a 5-bit ID, for consistency's sake.
27
28// GPR - One of the 32 32-bit general-purpose registers
29class GPR<bits<5> num, string n> : PPCReg<n> {
30  field bits<5> Num = num;
31}
32
33// GP8 - One of the 32 64-bit general-purpose registers
34class GP8<GPR SubReg, string n> : PPCReg<n> {
35  field bits<5> Num = SubReg.Num;
36  let SubRegs = [SubReg];
37  let SubRegIndices = [sub_32];
38}
39
40// SPR - One of the 32-bit special-purpose registers
41class SPR<bits<10> num, string n> : PPCReg<n> {
42  field bits<10> Num = num;
43}
44
45// FPR - One of the 32 64-bit floating-point registers
46class FPR<bits<5> num, string n> : PPCReg<n> {
47  field bits<5> Num = num;
48}
49
50// VR - One of the 32 128-bit vector registers
51class VR<bits<5> num, string n> : PPCReg<n> {
52  field bits<5> Num = num;
53}
54
55// CR - One of the 8 4-bit condition registers
56class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
57  field bits<3> Num = num;
58  let SubRegs = subregs;
59}
60
61// CRBIT - One of the 32 1-bit condition register fields
62class CRBIT<bits<5> num, string n> : PPCReg<n> {
63  field bits<5> Num = num;
64}
65
66
67// General-purpose registers
68def R0  : GPR< 0,  "r0">, DwarfRegNum<[-2, 0]>;
69def R1  : GPR< 1,  "r1">, DwarfRegNum<[-2, 1]>;
70def R2  : GPR< 2,  "r2">, DwarfRegNum<[-2, 2]>;
71def R3  : GPR< 3,  "r3">, DwarfRegNum<[-2, 3]>;
72def R4  : GPR< 4,  "r4">, DwarfRegNum<[-2, 4]>;
73def R5  : GPR< 5,  "r5">, DwarfRegNum<[-2, 5]>;
74def R6  : GPR< 6,  "r6">, DwarfRegNum<[-2, 6]>;
75def R7  : GPR< 7,  "r7">, DwarfRegNum<[-2, 7]>;
76def R8  : GPR< 8,  "r8">, DwarfRegNum<[-2, 8]>;
77def R9  : GPR< 9,  "r9">, DwarfRegNum<[-2, 9]>;
78def R10 : GPR<10, "r10">, DwarfRegNum<[-2, 10]>;
79def R11 : GPR<11, "r11">, DwarfRegNum<[-2, 11]>;
80def R12 : GPR<12, "r12">, DwarfRegNum<[-2, 12]>;
81def R13 : GPR<13, "r13">, DwarfRegNum<[-2, 13]>;
82def R14 : GPR<14, "r14">, DwarfRegNum<[-2, 14]>;
83def R15 : GPR<15, "r15">, DwarfRegNum<[-2, 15]>;
84def R16 : GPR<16, "r16">, DwarfRegNum<[-2, 16]>;
85def R17 : GPR<17, "r17">, DwarfRegNum<[-2, 17]>;
86def R18 : GPR<18, "r18">, DwarfRegNum<[-2, 18]>;
87def R19 : GPR<19, "r19">, DwarfRegNum<[-2, 19]>;
88def R20 : GPR<20, "r20">, DwarfRegNum<[-2, 20]>;
89def R21 : GPR<21, "r21">, DwarfRegNum<[-2, 21]>;
90def R22 : GPR<22, "r22">, DwarfRegNum<[-2, 22]>;
91def R23 : GPR<23, "r23">, DwarfRegNum<[-2, 23]>;
92def R24 : GPR<24, "r24">, DwarfRegNum<[-2, 24]>;
93def R25 : GPR<25, "r25">, DwarfRegNum<[-2, 25]>;
94def R26 : GPR<26, "r26">, DwarfRegNum<[-2, 26]>;
95def R27 : GPR<27, "r27">, DwarfRegNum<[-2, 27]>;
96def R28 : GPR<28, "r28">, DwarfRegNum<[-2, 28]>;
97def R29 : GPR<29, "r29">, DwarfRegNum<[-2, 29]>;
98def R30 : GPR<30, "r30">, DwarfRegNum<[-2, 30]>;
99def R31 : GPR<31, "r31">, DwarfRegNum<[-2, 31]>;
100
101// 64-bit General-purpose registers
102def X0  : GP8< R0,  "r0">, DwarfRegNum<[0, -2]>;
103def X1  : GP8< R1,  "r1">, DwarfRegNum<[1, -2]>;
104def X2  : GP8< R2,  "r2">, DwarfRegNum<[2, -2]>;
105def X3  : GP8< R3,  "r3">, DwarfRegNum<[3, -2]>;
106def X4  : GP8< R4,  "r4">, DwarfRegNum<[4, -2]>;
107def X5  : GP8< R5,  "r5">, DwarfRegNum<[5, -2]>;
108def X6  : GP8< R6,  "r6">, DwarfRegNum<[6, -2]>;
109def X7  : GP8< R7,  "r7">, DwarfRegNum<[7, -2]>;
110def X8  : GP8< R8,  "r8">, DwarfRegNum<[8, -2]>;
111def X9  : GP8< R9,  "r9">, DwarfRegNum<[9, -2]>;
112def X10 : GP8<R10, "r10">, DwarfRegNum<[10, -2]>;
113def X11 : GP8<R11, "r11">, DwarfRegNum<[11, -2]>;
114def X12 : GP8<R12, "r12">, DwarfRegNum<[12, -2]>;
115def X13 : GP8<R13, "r13">, DwarfRegNum<[13, -2]>;
116def X14 : GP8<R14, "r14">, DwarfRegNum<[14, -2]>;
117def X15 : GP8<R15, "r15">, DwarfRegNum<[15, -2]>;
118def X16 : GP8<R16, "r16">, DwarfRegNum<[16, -2]>;
119def X17 : GP8<R17, "r17">, DwarfRegNum<[17, -2]>;
120def X18 : GP8<R18, "r18">, DwarfRegNum<[18, -2]>;
121def X19 : GP8<R19, "r19">, DwarfRegNum<[19, -2]>;
122def X20 : GP8<R20, "r20">, DwarfRegNum<[20, -2]>;
123def X21 : GP8<R21, "r21">, DwarfRegNum<[21, -2]>;
124def X22 : GP8<R22, "r22">, DwarfRegNum<[22, -2]>;
125def X23 : GP8<R23, "r23">, DwarfRegNum<[23, -2]>;
126def X24 : GP8<R24, "r24">, DwarfRegNum<[24, -2]>;
127def X25 : GP8<R25, "r25">, DwarfRegNum<[25, -2]>;
128def X26 : GP8<R26, "r26">, DwarfRegNum<[26, -2]>;
129def X27 : GP8<R27, "r27">, DwarfRegNum<[27, -2]>;
130def X28 : GP8<R28, "r28">, DwarfRegNum<[28, -2]>;
131def X29 : GP8<R29, "r29">, DwarfRegNum<[29, -2]>;
132def X30 : GP8<R30, "r30">, DwarfRegNum<[30, -2]>;
133def X31 : GP8<R31, "r31">, DwarfRegNum<[31, -2]>;
134
135// Floating-point registers
136def F0  : FPR< 0,  "f0">, DwarfRegNum<[32, 32]>;
137def F1  : FPR< 1,  "f1">, DwarfRegNum<[33, 33]>;
138def F2  : FPR< 2,  "f2">, DwarfRegNum<[34, 34]>;
139def F3  : FPR< 3,  "f3">, DwarfRegNum<[35, 35]>;
140def F4  : FPR< 4,  "f4">, DwarfRegNum<[36, 36]>;
141def F5  : FPR< 5,  "f5">, DwarfRegNum<[37, 37]>;
142def F6  : FPR< 6,  "f6">, DwarfRegNum<[38, 38]>;
143def F7  : FPR< 7,  "f7">, DwarfRegNum<[39, 39]>;
144def F8  : FPR< 8,  "f8">, DwarfRegNum<[40, 40]>;
145def F9  : FPR< 9,  "f9">, DwarfRegNum<[41, 41]>;
146def F10 : FPR<10, "f10">, DwarfRegNum<[42, 42]>;
147def F11 : FPR<11, "f11">, DwarfRegNum<[43, 43]>;
148def F12 : FPR<12, "f12">, DwarfRegNum<[44, 44]>;
149def F13 : FPR<13, "f13">, DwarfRegNum<[45, 45]>;
150def F14 : FPR<14, "f14">, DwarfRegNum<[46, 46]>;
151def F15 : FPR<15, "f15">, DwarfRegNum<[47, 47]>;
152def F16 : FPR<16, "f16">, DwarfRegNum<[48, 48]>;
153def F17 : FPR<17, "f17">, DwarfRegNum<[49, 49]>;
154def F18 : FPR<18, "f18">, DwarfRegNum<[50, 50]>;
155def F19 : FPR<19, "f19">, DwarfRegNum<[51, 51]>;
156def F20 : FPR<20, "f20">, DwarfRegNum<[52, 52]>;
157def F21 : FPR<21, "f21">, DwarfRegNum<[53, 53]>;
158def F22 : FPR<22, "f22">, DwarfRegNum<[54, 54]>;
159def F23 : FPR<23, "f23">, DwarfRegNum<[55, 55]>;
160def F24 : FPR<24, "f24">, DwarfRegNum<[56, 56]>;
161def F25 : FPR<25, "f25">, DwarfRegNum<[57, 57]>;
162def F26 : FPR<26, "f26">, DwarfRegNum<[58, 58]>;
163def F27 : FPR<27, "f27">, DwarfRegNum<[59, 59]>;
164def F28 : FPR<28, "f28">, DwarfRegNum<[60, 60]>;
165def F29 : FPR<29, "f29">, DwarfRegNum<[61, 61]>;
166def F30 : FPR<30, "f30">, DwarfRegNum<[62, 62]>;
167def F31 : FPR<31, "f31">, DwarfRegNum<[63, 63]>;
168
169// Vector registers
170def V0  : VR< 0,  "v0">, DwarfRegNum<[77, 77]>;
171def V1  : VR< 1,  "v1">, DwarfRegNum<[78, 78]>;
172def V2  : VR< 2,  "v2">, DwarfRegNum<[79, 79]>;
173def V3  : VR< 3,  "v3">, DwarfRegNum<[80, 80]>;
174def V4  : VR< 4,  "v4">, DwarfRegNum<[81, 81]>;
175def V5  : VR< 5,  "v5">, DwarfRegNum<[82, 82]>;
176def V6  : VR< 6,  "v6">, DwarfRegNum<[83, 83]>;
177def V7  : VR< 7,  "v7">, DwarfRegNum<[84, 84]>;
178def V8  : VR< 8,  "v8">, DwarfRegNum<[85, 85]>;
179def V9  : VR< 9,  "v9">, DwarfRegNum<[86, 86]>;
180def V10 : VR<10, "v10">, DwarfRegNum<[87, 87]>;
181def V11 : VR<11, "v11">, DwarfRegNum<[88, 88]>;
182def V12 : VR<12, "v12">, DwarfRegNum<[89, 89]>;
183def V13 : VR<13, "v13">, DwarfRegNum<[90, 90]>;
184def V14 : VR<14, "v14">, DwarfRegNum<[91, 91]>;
185def V15 : VR<15, "v15">, DwarfRegNum<[92, 92]>;
186def V16 : VR<16, "v16">, DwarfRegNum<[93, 93]>;
187def V17 : VR<17, "v17">, DwarfRegNum<[94, 94]>;
188def V18 : VR<18, "v18">, DwarfRegNum<[95, 95]>;
189def V19 : VR<19, "v19">, DwarfRegNum<[96, 96]>;
190def V20 : VR<20, "v20">, DwarfRegNum<[97, 97]>;
191def V21 : VR<21, "v21">, DwarfRegNum<[98, 98]>;
192def V22 : VR<22, "v22">, DwarfRegNum<[99, 99]>;
193def V23 : VR<23, "v23">, DwarfRegNum<[100, 100]>;
194def V24 : VR<24, "v24">, DwarfRegNum<[101, 101]>;
195def V25 : VR<25, "v25">, DwarfRegNum<[102, 102]>;
196def V26 : VR<26, "v26">, DwarfRegNum<[103, 103]>;
197def V27 : VR<27, "v27">, DwarfRegNum<[104, 104]>;
198def V28 : VR<28, "v28">, DwarfRegNum<[105, 105]>;
199def V29 : VR<29, "v29">, DwarfRegNum<[106, 106]>;
200def V30 : VR<30, "v30">, DwarfRegNum<[107, 107]>;
201def V31 : VR<31, "v31">, DwarfRegNum<[108, 108]>;
202
203// Condition register bits
204def CR0LT : CRBIT< 0, "0">;
205def CR0GT : CRBIT< 1, "1">;
206def CR0EQ : CRBIT< 2, "2">;
207def CR0UN : CRBIT< 3, "3">;
208def CR1LT : CRBIT< 4, "4">;
209def CR1GT : CRBIT< 5, "5">;
210def CR1EQ : CRBIT< 6, "6">;
211def CR1UN : CRBIT< 7, "7">;
212def CR2LT : CRBIT< 8, "8">;
213def CR2GT : CRBIT< 9, "9">;
214def CR2EQ : CRBIT<10, "10">;
215def CR2UN : CRBIT<11, "11">;
216def CR3LT : CRBIT<12, "12">;
217def CR3GT : CRBIT<13, "13">;
218def CR3EQ : CRBIT<14, "14">;
219def CR3UN : CRBIT<15, "15">;
220def CR4LT : CRBIT<16, "16">;
221def CR4GT : CRBIT<17, "17">;
222def CR4EQ : CRBIT<18, "18">;
223def CR4UN : CRBIT<19, "19">;
224def CR5LT : CRBIT<20, "20">;
225def CR5GT : CRBIT<21, "21">;
226def CR5EQ : CRBIT<22, "22">;
227def CR5UN : CRBIT<23, "23">;
228def CR6LT : CRBIT<24, "24">;
229def CR6GT : CRBIT<25, "25">;
230def CR6EQ : CRBIT<26, "26">;
231def CR6UN : CRBIT<27, "27">;
232def CR7LT : CRBIT<28, "28">;
233def CR7GT : CRBIT<29, "29">;
234def CR7EQ : CRBIT<30, "30">;
235def CR7UN : CRBIT<31, "31">;
236
237// Condition registers
238let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
239def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
240def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;
241def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>;
242def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>;
243def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
244def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>;
245def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;
246def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
247}
248
249// Link register
250def LR  : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
251//let Aliases = [LR] in
252def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
253
254// Count register
255def CTR  : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
256def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
257
258// VRsave register
259def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>;
260
261// Carry bit.  In the architecture this is really bit 0 of the XER register
262// (which really is SPR register 1);  this is the only bit interesting to a
263// compiler.
264def CARRY: SPR<1, "ca">;
265
266// FP rounding mode:  bits 30 and 31 of the FP status and control register
267// This is not allocated as a normal register; it appears only in
268// Uses and Defs.  The ABI says it needs to be preserved by a function,
269// but this is not achieved by saving and restoring it as with
270// most registers, it has to be done in code; to make this work all the
271// return and call instructions are described as Uses of RM, so instructions
272// that do nothing but change RM will not get deleted.
273// Also, in the architecture it is not really a SPR; 512 is arbitrary.
274def RM: SPR<512, "**ROUNDING MODE**">;
275
276/// Register classes
277// Allocate volatiles first
278// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
279def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
280                                                (sequence "R%u", 30, 13),
281                                                R31, R0, R1, LR)>;
282
283def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
284                                                (sequence "X%u", 30, 14),
285                                                X31, X13, X0, X1, LR8)>;
286
287// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
288// ABI the size of the Floating-point register save area is determined by the
289// allocated non-volatile register with the lowest register number, as FP
290// register N is spilled to offset 8 * (32 - N) below the back chain word of the
291// previous stack frame. By allocating non-volatiles in reverse order we make
292// sure that the Floating-point register save area is always as small as
293// possible because there aren't any unused spill slots.
294def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
295                                                (sequence "F%u", 31, 14))>;
296def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
297
298def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
299                         (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
300                             V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
301                             V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
302
303def CRBITRC : RegisterClass<"PPC", [i32], 32,
304  (add CR0LT, CR0GT, CR0EQ, CR0UN,
305       CR1LT, CR1GT, CR1EQ, CR1UN,
306       CR2LT, CR2GT, CR2EQ, CR2UN,
307       CR3LT, CR3GT, CR3EQ, CR3UN,
308       CR4LT, CR4GT, CR4EQ, CR4UN,
309       CR5LT, CR5GT, CR5EQ, CR5UN,
310       CR6LT, CR6GT, CR6EQ, CR6UN,
311       CR7LT, CR7GT, CR7EQ, CR7UN)>
312{
313  let CopyCost = -1;
314}
315
316def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
317                                                CR7, CR2, CR3, CR4)> {
318  let SubRegClasses = [(CRBITRC sub_lt, sub_gt, sub_eq, sub_un)];
319}
320
321def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)>;
322def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)>;
323def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
324def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
325  let CopyCost = -1;
326}
327