1; Show that we know how to translate asr. 2 3; NOTE: We use -O2 to get rid of memory stores. 4 5; REQUIRES: allow_dump 6 7; Compile using standalone assembler. 8; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 9; RUN: | FileCheck %s --check-prefix=ASM 10 11; Show bytes in assembled standalone code. 12; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ 13; RUN: --args -O2 | FileCheck %s --check-prefix=DIS 14 15; Compile using integrated assembler. 16; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \ 17; RUN: | FileCheck %s --check-prefix=IASM 18 19; Show bytes in assembled integrated code. 20; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ 21; RUN: --args -O2 | FileCheck %s --check-prefix=DIS 22 23define internal i32 @AshrAmt(i32 %a) { 24; ASM-LABEL:AshrAmt: 25; DIS-LABEL:00000000 <AshrAmt>: 26; IASM-LABEL:AshrAmt: 27 28entry: 29; ASM-NEXT:.LAshrAmt$entry: 30; IASM-NEXT:.LAshrAmt$entry: 31 32 %v = ashr i32 %a, 23 33 34; ASM-NEXT: asr r0, r0, #23 35; DIS-NEXT: 0: e1a00bc0 36; IASM-NOT: asr 37; IASM-NEXT: .byte 0xc0 38; IASM-NEXT: .byte 0xb 39; IASM-NEXT: .byte 0xa0 40; IASM-NEXT: .byte 0xe1 41 42 ret i32 %v 43} 44 45define internal i32 @AshrReg(i32 %a, i32 %b) { 46; ASM-LABEL:AshrReg: 47; DIS-LABEL:00000010 <AshrReg>: 48; IASM-LABEL:AshrReg: 49 50entry: 51; ASM-NEXT:.LAshrReg$entry: 52; IASM-NEXT:.LAshrReg$entry: 53 54 %v = ashr i32 %a, %b 55 56; ASM-NEXT: asr r0, r0, r1 57; DIS-NEXT: 10: e1a00150 58; IASM-NOT: asr 59; IASM-NEXT: .byte 0x50 60; IASM-NEXT: .byte 0x1 61; IASM-NEXT: .byte 0xa0 62; IASM-NEXT: .byte 0xe1 63 64 ret i32 %v 65} 66 67define internal <4 x i32> @AshrVeci32(<4 x i32> %a, <4 x i32> %b) { 68; ASM-LABEL:AshrVeci32: 69; DIS-LABEL:00000020 <AshrVeci32>: 70; IASM-LABEL:AshrVeci32: 71 72entry: 73 74 %v = ashr <4 x i32> %a, %b 75 76; ASM: vneg.s32 q1, q1 77; ASM-NEXT: vshl.s32 q0, q0, q1 78; DIS: 20: f3b923c2 79; DIS: 24: f2220440 80; IASM-NOT: vneg 81; IASM-NOT: vshl 82 83 ret <4 x i32> %v 84} 85 86define internal <8 x i16> @AshrVeci16(<8 x i16> %a, <8 x i16> %b) { 87; ASM-LABEL:AshrVeci16: 88 89entry: 90 91 %v = ashr <8 x i16> %a, %b 92 93; ASM: vneg.s16 q1, q1 94; ASM-NEXT: vshl.s16 q0, q0, q1 95; DIS: 30: f3b523c2 96; DIS: 34: f2120440 97; IASM-NOT: vneg 98; IASM-NOT: vshl 99 100 ret <8 x i16> %v 101} 102 103define internal <16 x i8> @AshrVeci8(<16 x i8> %a, <16 x i8> %b) { 104; ASM-LABEL:AshrVeci8: 105 106entry: 107 108 %v = ashr <16 x i8> %a, %b 109 110; ASM: vneg.s8 q1, q1 111; ASM-NEXT: vshl.s8 q0, q0, q1 112; DIS: 40: f3b123c2 113; DIS: 44: f2020440 114; IASM-NOT: vneg 115; IASM-NOT: vshl 116 117 ret <16 x i8> %v 118} 119