1; This file checks support for comparing vector values with the icmp 2; instruction. 3 4; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s 5; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s 6 7; RUN: %if --need=target_MIPS32 --need=allow_dump \ 8; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\ 9; RUN: -i %s --args -O2 \ 10; RUN: | %if --need=target_MIPS32 --need=allow_dump \ 11; RUN: --command FileCheck --check-prefix MIPS32 %s 12 13; Check that sext elimination occurs when the result of the comparison 14; instruction is already sign extended. Sign extension to 4 x i32 uses 15; the pslld instruction on x86. 16define internal <4 x i32> @test_sext_elimination(<4 x i32> %a, <4 x i32> %b) { 17entry: 18 %res.trunc = icmp eq <4 x i32> %a, %b 19 %res = sext <4 x i1> %res.trunc to <4 x i32> 20 ret <4 x i32> %res 21; CHECK-LABEL: test_sext_elimination 22; CHECK: pcmpeqd 23; CHECK-NOT: pslld 24 25; MIPS32-LABEL: test_sext_elimination 26; MIPS32: lw [[T0:.*]], 27; MIPS32: lw [[T1:.*]], 28; MIPS32: lw [[T2:.*]], 29; MIPS32: lw [[T3:.*]], 30; MIPS32: xor [[T4:.*]],a0,[[T0]] 31; MIPS32: sltiu [[T4]],[[T4]],1 32; MIPS32: xor [[T5:.*]],a1,[[T1]] 33; MIPS32: sltiu [[T5]],[[T5]],1 34; MIPS32: xor [[T6:.*]],a2,[[T2]] 35; MIPS32: sltiu [[T6]],[[T6]],1 36; MIPS32: xor [[T7:.*]],a3,[[T3]] 37; MIPS32: sltiu [[T7]],[[T7]],1 38; MIPS32: andi [[T4]],[[T4]],0x1 39; MIPS32: sll [[T4]],[[T4]],0x1f 40; MIPS32: sra [[T4]],[[T4]],0x1f 41; MIPS32: andi [[T5]],[[T5]],0x1 42; MIPS32: sll [[T5]],[[T5]],0x1f 43; MIPS32: sra [[T5]],[[T5]],0x1f 44; MIPS32: andi [[T6]],[[T6]],0x1 45; MIPS32: sll [[T6]],[[T6]],0x1f 46; MIPS32: sra [[T6]],[[T6]],0x1f 47; MIPS32: andi [[T7]],[[T7]],0x1 48; MIPS32: sll [[T7]],[[T7]],0x1f 49; MIPS32: sra [[T7]],[[T7]],0x1f 50; MIPS32: move v0,[[T4]] 51; MIPS32: move v1,[[T5]] 52; MIPS32: move a0,[[T6]] 53; MIPS32: move a1,[[T7]] 54} 55 56define internal <4 x i1> @test_icmp_v4i32_eq(<4 x i32> %a, <4 x i32> %b) { 57entry: 58 %res = icmp eq <4 x i32> %a, %b 59 ret <4 x i1> %res 60; CHECK-LABEL: test_icmp_v4i32_eq 61; CHECK: pcmpeqd 62 63; MIPS32-LABEL: test_icmp_v4i32_eq 64; MIPS32: lw [[T0:.*]], 65; MIPS32: lw [[T1:.*]], 66; MIPS32: lw [[T2:.*]], 67; MIPS32: lw [[T3:.*]], 68; MIPS32: xor [[T4:.*]],a0,[[T0]] 69; MIPS32: sltiu [[T4]],[[T4]],1 70; MIPS32: xor [[T5:.*]],a1,[[T1]] 71; MIPS32: sltiu [[T5]],[[T5]],1 72; MIPS32: xor [[T6:.*]],a2,[[T2]] 73; MIPS32: sltiu [[T6]],[[T6]],1 74; MIPS32: xor [[T7:.*]],a3,[[T3]] 75; MIPS32: sltiu [[T7]],[[T7]],1 76; MIPS32: move v0,[[T4]] 77; MIPS32: move v1,[[T5]] 78; MIPS32: move a0,[[T6]] 79; MIPS32: move a1,[[T7]] 80} 81 82define internal <4 x i1> @test_icmp_v4i32_ne(<4 x i32> %a, <4 x i32> %b) { 83entry: 84 %res = icmp ne <4 x i32> %a, %b 85 ret <4 x i1> %res 86; CHECK-LABEL: test_icmp_v4i32_ne 87; CHECK: pcmpeqd 88; CHECK: pxor 89 90; MIPS32-LABEL: test_icmp_v4i32_ne 91; MIPS32: lw [[T0:.*]], 92; MIPS32: lw [[T1:.*]], 93; MIPS32: lw [[T2:.*]], 94; MIPS32: lw [[T3:.*]], 95; MIPS32: xor [[T4:.*]],a0,[[T0]] 96; MIPS32: sltu [[T4]],zero,[[T4]] 97; MIPS32: xor [[T5:.*]],a1,[[T1]] 98; MIPS32: sltu [[T5]],zero,[[T5]] 99; MIPS32: xor [[T6:.*]],a2,[[T2]] 100; MIPS32: sltu [[T6]],zero,[[T6]] 101; MIPS32: xor [[T7:.*]],a3,[[T3]] 102; MIPS32: sltu [[T7]],zero,[[T7]] 103; MIPS32: move v0,[[T4]] 104; MIPS32: move v1,[[T5]] 105; MIPS32: move a0,[[T6]] 106; MIPS32: move a1,[[T7]] 107} 108 109define internal <4 x i1> @test_icmp_v4i32_sgt(<4 x i32> %a, <4 x i32> %b) { 110entry: 111 %res = icmp sgt <4 x i32> %a, %b 112 ret <4 x i1> %res 113; CHECK: pcmpgtd 114 115; MIPS32-LABEL: test_icmp_v4i32_sgt 116; MIPS32: lw [[T0:.*]], 117; MIPS32: lw [[T1:.*]], 118; MIPS32: lw [[T2:.*]], 119; MIPS32: lw [[T3:.*]], 120; MIPS32: slt v0,[[T0]],[[T4:.*]] 121; MIPS32: slt v1,[[T1]],[[T5:.*]] 122; MIPS32: slt [[T2]],[[T2]],[[T6:.*]] 123; MIPS32: slt [[T3]],[[T3]],[[T7:.*]] 124; MIPS32: move a0,[[T2]] 125; MIPS32: move a1,[[T3]] 126} 127 128define internal <4 x i1> @test_icmp_v4i32_sle(<4 x i32> %a, <4 x i32> %b) { 129entry: 130 %res = icmp sle <4 x i32> %a, %b 131 ret <4 x i1> %res 132; CHECK-LABEL: test_icmp_v4i32_sle 133; CHECK: pcmpgtd 134; CHECK: pxor 135 136; MIPS32-LABEL: test_icmp_v4i32_sle 137; MIPS32: lw [[T0:.*]], 138; MIPS32: lw [[T1:.*]], 139; MIPS32: lw [[T2:.*]], 140; MIPS32: lw [[T3:.*]], 141; MIPS32: slt [[T0]],[[T0]],[[T4:.*]] 142; MIPS32: xori v0,[[T0]],0x1 143; MIPS32: slt [[T1]],[[T1]],[[T5:.*]] 144; MIPS32: xori v1,[[T1]],0x1 145; MIPS32: slt [[T2]],[[T2]],[[T6:.*]] 146; MIPS32: xori [[T2]],[[T2]],0x1 147; MIPS32: slt [[T3]],[[T3]],[[T7:.*]] 148; MIPS32: xori [[T3]],[[T3]],0x1 149; MIPS32: move a0,[[T2]] 150; MIPS32: move a1,[[T3]] 151} 152 153define internal <4 x i1> @test_icmp_v4i32_slt(<4 x i32> %a, <4 x i32> %b) { 154entry: 155 %res = icmp slt <4 x i32> %a, %b 156 ret <4 x i1> %res 157; CHECK-LABEL: test_icmp_v4i32_slt 158; CHECK: pcmpgtd 159 160; MIPS32-LABEL: test_icmp_v4i32_slt 161; MIPS32: lw [[T0:.*]], 162; MIPS32: lw [[T1:.*]], 163; MIPS32: lw [[T2:.*]], 164; MIPS32: lw [[T3:.*]], 165; MIPS32: slt [[T4:.*]],a0,[[T0]] 166; MIPS32: slt [[T5:.*]],a1,[[T1]] 167; MIPS32: slt [[T6:.*]],a2,[[T2]] 168; MIPS32: slt [[T7:.*]],a3,[[T3]] 169; MIPS32: move v0,[[T4]] 170; MIPS32: move v1,[[T5]] 171; MIPS32: move a0,[[T6]] 172; MIPS32: move a1,[[T7]] 173} 174 175define internal <4 x i1> @test_icmp_v4i32_uge(<4 x i32> %a, <4 x i32> %b) { 176entry: 177 %res = icmp uge <4 x i32> %a, %b 178 ret <4 x i1> %res 179; CHECK-LABEL: test_icmp_v4i32_uge 180; CHECK: pxor 181; CHECK: pcmpgtd 182; CHECK: pxor 183 184; MIPS32-LABEL: test_icmp_v4i32_uge 185; MIPS32: lw [[T0:.*]], 186; MIPS32: lw [[T1:.*]], 187; MIPS32: lw [[T2:.*]], 188; MIPS32: lw [[T3:.*]], 189; MIPS32: sltu [[T4:.*]],a0,[[T0]] 190; MIPS32: xori [[T4]],[[T4]],0x1 191; MIPS32: sltu [[T5:.*]],a1,[[T1]] 192; MIPS32: xori [[T5]],[[T5]],0x1 193; MIPS32: sltu [[T6:.*]],a2,[[T2]] 194; MIPS32: xori [[T6]],[[T6]],0x1 195; MIPS32: sltu [[T7:.*]],a3,[[T3]] 196; MIPS32: xori [[T7]],[[T7]],0x1 197; MIPS32: move v0,[[T4]] 198; MIPS32: move v1,[[T5]] 199; MIPS32: move a0,[[T6]] 200; MIPS32: move a1,[[T7]] 201} 202 203define internal <4 x i1> @test_icmp_v4i32_ugt(<4 x i32> %a, <4 x i32> %b) { 204entry: 205 %res = icmp ugt <4 x i32> %a, %b 206 ret <4 x i1> %res 207; CHECK-LABEL: test_icmp_v4i32_ugt 208; CHECK: pxor 209; CHECK: pcmpgtd 210 211; MIPS32-LABEL: test_icmp_v4i32_ugt 212; MIPS32: lw [[T0:.*]], 213; MIPS32: lw [[T1:.*]], 214; MIPS32: lw [[T2:.*]], 215; MIPS32: lw [[T3:.*]], 216; MIPS32: sltu v0,[[T0]],[[T4:.*]] 217; MIPS32: sltu v1,[[T1]],[[T5:.*]] 218; MIPS32: sltu [[T2]],[[T2]],[[T6:.*]] 219; MIPS32: sltu [[T3]],[[T3]],[[T7:.*]] 220; MIPS32: move a0,[[T2]] 221; MIPS32: move a1,[[T3]] 222} 223 224define internal <4 x i1> @test_icmp_v4i32_ule(<4 x i32> %a, <4 x i32> %b) { 225entry: 226 %res = icmp ule <4 x i32> %a, %b 227 ret <4 x i1> %res 228; CHECK-LABEL: test_icmp_v4i32_ule 229; CHECK: pxor 230; CHECK: pcmpgtd 231; CHECK: pxor 232 233; MIPS32-LABEL: test_icmp_v4i32_ule 234; MIPS32: lw [[T0:.*]], 235; MIPS32: lw [[T1:.*]], 236; MIPS32: lw [[T2:.*]], 237; MIPS32: lw [[T3:.*]], 238; MIPS32: sltu [[T0]],[[T0]],[[T4:.*]] 239; MIPS32: xori v0,[[T0]],0x1 240; MIPS32: sltu [[T1]],[[T1]],[[T5:.*]] 241; MIPS32: xori v1,[[T1]],0x1 242; MIPS32: sltu [[T2]],[[T2]],[[T6:.*]] 243; MIPS32: xori [[T2]],[[T2]],0x1 244; MIPS32: sltu [[T3]],[[T3]],[[T7:.*]] 245; MIPS32: xori [[T3]],[[T3]],0x1 246; MIPS32: move a0,[[T2]] 247; MIPS32: move a1,[[T3]] 248} 249 250define internal <4 x i1> @test_icmp_v4i32_ult(<4 x i32> %a, <4 x i32> %b) { 251entry: 252 %res = icmp ult <4 x i32> %a, %b 253 ret <4 x i1> %res 254; CHECK-LABEL: test_icmp_v4i32_ult 255; CHECK: pxor 256; CHECK: pcmpgtd 257 258; MIPS32-LABEL: test_icmp_v4i32_ult 259; MIPS32: lw [[T0:.*]], 260; MIPS32: lw [[T1:.*]], 261; MIPS32: lw [[T2:.*]], 262; MIPS32: lw [[T3:.*]], 263; MIPS32: sltu [[T4:.*]],a0,[[T0]] 264; MIPS32: sltu [[T5:.*]],a1,[[T1]] 265; MIPS32: sltu [[T6:.*]],a2,[[T2]] 266; MIPS32: sltu [[T7:.*]],a3,[[T3]] 267; MIPS32: move v0,[[T4]] 268; MIPS32: move v1,[[T5]] 269; MIPS32: move a0,[[T6]] 270; MIPS32: move a1,[[T7]] 271} 272 273define internal <4 x i1> @test_icmp_v4i1_eq(<4 x i1> %a, <4 x i1> %b) { 274entry: 275 %res = icmp eq <4 x i1> %a, %b 276 ret <4 x i1> %res 277; CHECK-LABEL: test_icmp_v4i1_eq 278; CHECK: pcmpeqd 279 280; MIPS32-LABEL: test_icmp_v4i1_eq 281; MIPS32: lw [[T0:.*]], 282; MIPS32: lw [[T1:.*]], 283; MIPS32: lw [[T2:.*]], 284; MIPS32: lw [[T3:.*]], 285; MIPS32: andi [[T4:.*]],a0,0x1 286; MIPS32: andi [[T0]],[[T0]],0x1 287; MIPS32: sll [[T4]],[[T4]],0x1f 288; MIPS32: sll [[T0]],[[T0]],0x1f 289; MIPS32: xor [[T4]],[[T4]],[[T0]] 290; MIPS32: sltiu [[T4]],[[T4]],1 291; MIPS32: andi [[T5:.*]],a1,0x1 292; MIPS32: andi [[T1]],[[T1]],0x1 293; MIPS32: sll [[T5]],[[T5]],0x1f 294; MIPS32: sll [[T1]],[[T1]],0x1f 295; MIPS32: xor [[T5]],[[T5]],[[T1]] 296; MIPS32: sltiu [[T5]],[[T5]],1 297; MIPS32: andi [[T6:.*]],a2,0x1 298; MIPS32: andi [[T2]],[[T2]],0x1 299; MIPS32: sll [[T6]],[[T6]],0x1f 300; MIPS32: sll [[T2]],[[T2]],0x1f 301; MIPS32: xor [[T6]],[[T6]],[[T2]] 302; MIPS32: sltiu [[T6]],[[T6]],1 303; MIPS32: andi [[T7:.*]],a3,0x1 304; MIPS32: andi [[T3]],[[T3]],0x1 305; MIPS32: sll [[T7]],[[T7]],0x1f 306; MIPS32: sll [[T3]],[[T3]],0x1f 307; MIPS32: xor [[T7]],[[T7]],[[T3]] 308; MIPS32: sltiu [[T7]],[[T7]],1 309; MIPS32: move v0,[[T4]] 310; MIPS32: move v1,[[T5]] 311; MIPS32: move a0,[[T6]] 312; MIPS32: move a1,[[T7]] 313} 314 315define internal <4 x i1> @test_icmp_v4i1_ne(<4 x i1> %a, <4 x i1> %b) { 316entry: 317 %res = icmp ne <4 x i1> %a, %b 318 ret <4 x i1> %res 319; CHECK-LABEL: test_icmp_v4i1_ne 320; CHECK: pcmpeqd 321; CHECK: pxor 322 323; MIPS32-LABEL: test_icmp_v4i1_ne 324; MIPS32: lw [[T0:.*]], 325; MIPS32: lw [[T1:.*]], 326; MIPS32: lw [[T2:.*]], 327; MIPS32: lw [[T3:.*]], 328; MIPS32: andi [[T4:.*]],a0,0x1 329; MIPS32: andi [[T0]],[[T0]],0x1 330; MIPS32: sll [[T4]],[[T4]],0x1f 331; MIPS32: sll [[T0]],[[T0]],0x1f 332; MIPS32: xor [[T4]],[[T4]],[[T0]] 333; MIPS32: sltu [[T4]],zero,[[T4]] 334; MIPS32: andi [[T5:.*]],a1,0x1 335; MIPS32: andi [[T1]],[[T1]],0x1 336; MIPS32: sll [[T5]],[[T5]],0x1f 337; MIPS32: sll [[T1]],[[T1]],0x1f 338; MIPS32: xor [[T5]],[[T5]],[[T1]] 339; MIPS32: sltu [[T5]],zero,[[T5]] 340; MIPS32: andi [[T6:.*]],a2,0x1 341; MIPS32: andi [[T2]],[[T2]],0x1 342; MIPS32: sll [[T6]],[[T6]],0x1f 343; MIPS32: sll [[T2]],[[T2]],0x1f 344; MIPS32: xor [[T6]],[[T6]],[[T2]] 345; MIPS32: sltu [[T6]],zero,[[T6]] 346; MIPS32: andi [[T7:.*]],a3,0x1 347; MIPS32: andi [[T3]],[[T3]],0x1 348; MIPS32: sll [[T7]],[[T7]],0x1f 349; MIPS32: sll [[T3]],[[T3]],0x1f 350; MIPS32: xor [[T7]],[[T7]],[[T3]] 351; MIPS32: sltu [[T7]],zero,[[T7]] 352; MIPS32: move v0,[[T4]] 353; MIPS32: move v1,[[T5]] 354; MIPS32: move a0,[[T6]] 355; MIPS32: move a1,[[T7]] 356} 357 358define internal <4 x i1> @test_icmp_v4i1_sgt(<4 x i1> %a, <4 x i1> %b) { 359entry: 360 %res = icmp sgt <4 x i1> %a, %b 361 ret <4 x i1> %res 362; CHECK-LABEL: test_icmp_v4i1_sgt 363; CHECK: pcmpgtd 364 365; MIPS32-LABEL: test_icmp_v4i1_sgt 366; MIPS32: lw [[T0:.*]], 367; MIPS32: lw [[T1:.*]], 368; MIPS32: lw [[T2:.*]], 369; MIPS32: lw [[T3:.*]], 370; MIPS32: andi [[T4:.*]],a0,0x1 371; MIPS32: andi [[T0]],[[T0]],0x1 372; MIPS32: sll [[T4]],[[T4]],0x1f 373; MIPS32: sll [[T0]],[[T0]],0x1f 374; MIPS32: slt v0,[[T0]],[[T4]] 375; MIPS32: andi [[T5:.*]],a1,0x1 376; MIPS32: andi [[T1]],[[T1]],0x1 377; MIPS32: sll [[T5]],[[T5]],0x1f 378; MIPS32: sll [[T1]],[[T1]],0x1f 379; MIPS32: slt v1,[[T1]],[[T5]] 380; MIPS32: andi [[T6:.*]],a2,0x1 381; MIPS32: andi [[T2]],[[T2]],0x1 382; MIPS32: sll [[T6]],[[T6]],0x1f 383; MIPS32: sll [[T2]],[[T2]],0x1f 384; MIPS32: slt [[T2]],[[T2]],[[T6]] 385; MIPS32: andi [[T7:.*]],a3,0x1 386; MIPS32: andi [[T3]],[[T3]],0x1 387; MIPS32: sll [[T7]],[[T7]],0x1f 388; MIPS32: sll [[T3]],[[T3]],0x1f 389; MIPS32: slt [[T3]],[[T3]],[[T7]] 390; MIPS32: move a0,[[T2]] 391; MIPS32: move a1,[[T3]] 392} 393 394define internal <4 x i1> @test_icmp_v4i1_sle(<4 x i1> %a, <4 x i1> %b) { 395entry: 396 %res = icmp sle <4 x i1> %a, %b 397 ret <4 x i1> %res 398; CHECK-LABEL: test_icmp_v4i1_sle 399; CHECK: pcmpgtd 400; CHECK: pxor 401 402; MIPS32-LABEL: test_icmp_v4i1_sle 403; MIPS32: lw [[T0:.*]], 404; MIPS32: lw [[T1:.*]], 405; MIPS32: lw [[T2:.*]], 406; MIPS32: lw [[T3:.*]], 407; MIPS32: andi [[T4:.*]],a0,0x1 408; MIPS32: andi [[T0]],[[T0]],0x1 409; MIPS32: sll [[T4]],[[T4]],0x1f 410; MIPS32: sll [[T0]],[[T0]],0x1f 411; MIPS32: slt [[T0]],[[T0]],[[T4]] 412; MIPS32: xori v0,[[T0]],0x1 413; MIPS32: andi [[T5:.*]],a1,0x1 414; MIPS32: andi [[T1]],[[T1]],0x1 415; MIPS32: sll [[T5]],[[T5]],0x1f 416; MIPS32: sll [[T1]],[[T1]],0x1f 417; MIPS32: slt [[T1]],[[T1]],[[T5]] 418; MIPS32: xori v1,[[T1]],0x1 419; MIPS32: andi [[T6:.*]],a2,0x1 420; MIPS32: andi [[T2]],[[T2]],0x1 421; MIPS32: sll [[T6]],[[T6]],0x1f 422; MIPS32: sll [[T2]],[[T2]],0x1f 423; MIPS32: slt [[T2]],[[T2]],[[T6]] 424; MIPS32: xori [[T2]],[[T2]],0x1 425; MIPS32: andi [[T7:.*]],a3,0x1 426; MIPS32: andi [[T3]],[[T3]],0x1 427; MIPS32: sll [[T7]],[[T7]],0x1f 428; MIPS32: sll [[T3]],[[T3]],0x1f 429; MIPS32: slt [[T3]],[[T3]],[[T7]] 430; MIPS32: xori [[T3]],[[T3]],0x1 431; MIPS32: move a0,[[T2]] 432; MIPS32: move a1,[[T3]] 433} 434 435define internal <4 x i1> @test_icmp_v4i1_slt(<4 x i1> %a, <4 x i1> %b) { 436entry: 437 %res = icmp slt <4 x i1> %a, %b 438 ret <4 x i1> %res 439; CHECK-LABEL: test_icmp_v4i1_slt 440; CHECK: pcmpgtd 441 442; MIPS32-LABEL: test_icmp_v4i1_slt 443; MIPS32: lw [[T0:.*]], 444; MIPS32: lw [[T1:.*]], 445; MIPS32: lw [[T2:.*]], 446; MIPS32: lw [[T3:.*]], 447; MIPS32: andi [[T4:.*]],a0,0x1 448; MIPS32: andi [[T0]],[[T0]],0x1 449; MIPS32: sll [[T4]],[[T4]],0x1f 450; MIPS32: sll [[T0]],[[T0]],0x1f 451; MIPS32: slt [[T4]],[[T4]],[[T0]] 452; MIPS32: andi [[T5:.*]],a1,0x1 453; MIPS32: andi [[T1]],[[T1]],0x1 454; MIPS32: sll [[T5]],[[T5]],0x1f 455; MIPS32: sll [[T1]],[[T1]],0x1f 456; MIPS32: slt [[T5]],[[T5]],[[T1]] 457; MIPS32: andi [[T6:.*]],a2,0x1 458; MIPS32: andi [[T2]],[[T2]],0x1 459; MIPS32: sll [[T6]],[[T6]],0x1f 460; MIPS32: sll [[T2]],[[T2]],0x1f 461; MIPS32: slt [[T6]],[[T6]],[[T2]] 462; MIPS32: andi [[T7:.*]],a3,0x1 463; MIPS32: andi [[T3]],[[T3]],0x1 464; MIPS32: sll [[T7]],[[T7]],0x1f 465; MIPS32: sll [[T3]],[[T3]],0x1f 466; MIPS32: slt [[T7]],[[T7]],[[T3]] 467; MIPS32: move v0,[[T4]] 468; MIPS32: move v1,[[T5]] 469; MIPS32: move a0,[[T6]] 470; MIPS32: move a1,[[T7]] 471} 472 473define internal <4 x i1> @test_icmp_v4i1_uge(<4 x i1> %a, <4 x i1> %b) { 474entry: 475 %res = icmp uge <4 x i1> %a, %b 476 ret <4 x i1> %res 477; CHECK-LABEL: test_icmp_v4i1_uge 478; CHECK: pxor 479; CHECK: pcmpgtd 480; CHECK: pxor 481 482; MIPS32-LABEL: test_icmp_v4i1_uge 483; MIPS32: lw [[T0:.*]], 484; MIPS32: lw [[T1:.*]], 485; MIPS32: lw [[T2:.*]], 486; MIPS32: lw [[T3:.*]], 487; MIPS32: andi [[T4:.*]],a0,0x1 488; MIPS32: andi [[T0]],[[T0]],0x1 489; MIPS32: sll [[T4]],[[T4]],0x1f 490; MIPS32: sll [[T0]],[[T0]],0x1f 491; MIPS32: sltu [[T4]],[[T4]],[[T0]] 492; MIPS32: xori [[T4]],[[T4]],0x1 493; MIPS32: andi [[T5:.*]],a1,0x1 494; MIPS32: andi [[T1]],[[T1]],0x1 495; MIPS32: sll [[T5]],[[T5]],0x1f 496; MIPS32: sll [[T1]],[[T1]],0x1f 497; MIPS32: sltu [[T5]],[[T5]],[[T1]] 498; MIPS32: xori [[T5]],[[T5]],0x1 499; MIPS32: andi [[T6:.*]],a2,0x1 500; MIPS32: andi [[T2]],[[T2]],0x1 501; MIPS32: sll [[T6]],[[T6]],0x1f 502; MIPS32: sll [[T2]],[[T2]],0x1f 503; MIPS32: sltu [[T6]],[[T6]],[[T2]] 504; MIPS32: xori [[T6]],[[T6]],0x1 505; MIPS32: andi [[T7:.*]],a3,0x1 506; MIPS32: andi [[T3]],[[T3]],0x1 507; MIPS32: sll [[T7]],[[T7]],0x1f 508; MIPS32: sll [[T3]],[[T3]],0x1f 509; MIPS32: sltu [[T7]],[[T7]],[[T3]] 510; MIPS32: xori [[T7]],[[T7]],0x1 511; MIPS32: move v0,[[T4]] 512; MIPS32: move v1,[[T5]] 513; MIPS32: move a0,[[T6]] 514; MIPS32: move a1,[[T7]] 515} 516 517define internal <4 x i1> @test_icmp_v4i1_ugt(<4 x i1> %a, <4 x i1> %b) { 518entry: 519 %res = icmp ugt <4 x i1> %a, %b 520 ret <4 x i1> %res 521; CHECK-LABEL: test_icmp_v4i1_ugt 522; CHECK: pxor 523; CHECK: pcmpgtd 524 525; MIPS32-LABEL: test_icmp_v4i1_ugt 526; MIPS32: lw [[T0:.*]], 527; MIPS32: lw [[T1:.*]], 528; MIPS32: lw [[T2:.*]], 529; MIPS32: lw [[T3:.*]], 530; MIPS32: andi [[T4:.*]],a0,0x1 531; MIPS32: andi [[T0]],[[T0]],0x1 532; MIPS32: sll [[T4]],[[T4]],0x1f 533; MIPS32: sll [[T0]],[[T0]],0x1f 534; MIPS32: sltu v0,[[T0]],[[T4]] 535; MIPS32: andi [[T5:.*]],a1,0x1 536; MIPS32: andi [[T1]],[[T1]],0x1 537; MIPS32: sll [[T5]],[[T5]],0x1f 538; MIPS32: sll [[T1]],[[T1]],0x1f 539; MIPS32: sltu v1,[[T1]],[[T5]] 540; MIPS32: andi [[T6:.*]],a2,0x1 541; MIPS32: andi [[T2]],[[T2]],0x1 542; MIPS32: sll [[T6]],[[T6]],0x1f 543; MIPS32: sll [[T2]],[[T2]],0x1f 544; MIPS32: sltu [[T2]],[[T2]],[[T6]] 545; MIPS32: andi [[T7:.*]],a3,0x1 546; MIPS32: andi [[T3]],[[T3]],0x1 547; MIPS32: sll [[T7]],[[T7]],0x1f 548; MIPS32: sll [[T3]],[[T3]],0x1f 549; MIPS32: sltu [[T3]],[[T3]],[[T7]] 550; MIPS32: move a0,[[T2]] 551; MIPS32: move a1,[[T3]] 552} 553 554define internal <4 x i1> @test_icmp_v4i1_ule(<4 x i1> %a, <4 x i1> %b) { 555entry: 556 %res = icmp ule <4 x i1> %a, %b 557 ret <4 x i1> %res 558; CHECK-LABEL: test_icmp_v4i1_ule 559; CHECK: pxor 560; CHECK: pcmpgtd 561; CHECK: pxor 562 563; MIPS32-LABEL: test_icmp_v4i1_ule 564; MIPS32: lw [[T0:.*]], 565; MIPS32: lw [[T1:.*]], 566; MIPS32: lw [[T2:.*]], 567; MIPS32: lw [[T3:.*]], 568; MIPS32: andi [[T4:.*]],a0,0x1 569; MIPS32: andi [[T0]],[[T0]],0x1 570; MIPS32: sll [[T4]],[[T4]],0x1f 571; MIPS32: sll [[T0]],[[T0]],0x1f 572; MIPS32: sltu [[T0]],[[T0]],[[T4]] 573; MIPS32: xori v0,[[T0]],0x1 574; MIPS32: andi [[T5:.*]],a1,0x1 575; MIPS32: andi [[T1]],[[T1]],0x1 576; MIPS32: sll [[T5]],[[T5]],0x1f 577; MIPS32: sll [[T1]],[[T1]],0x1f 578; MIPS32: sltu [[T1]],[[T1]],[[T5]] 579; MIPS32: xori v1,[[T1]],0x1 580; MIPS32: andi [[T6:.*]],a2,0x1 581; MIPS32: andi [[T2]],[[T2]],0x1 582; MIPS32: sll [[T6]],[[T6]],0x1f 583; MIPS32: sll [[T2]],[[T2]],0x1f 584; MIPS32: sltu [[T2]],[[T2]],[[T6]] 585; MIPS32: xori [[T2]],[[T2]],0x1 586; MIPS32: andi [[T7:.*]],a3,0x1 587; MIPS32: andi [[T3]],[[T3]],0x1 588; MIPS32: sll [[T7]],[[T7]],0x1f 589; MIPS32: sll [[T3]],[[T3]],0x1f 590; MIPS32: sltu [[T3]],[[T3]],[[T7]] 591; MIPS32: xori [[T3]],[[T3]],0x1 592; MIPS32: move a0,[[T2]] 593; MIPS32: move a1,[[T3]] 594} 595 596define internal <4 x i1> @test_icmp_v4i1_ult(<4 x i1> %a, <4 x i1> %b) { 597entry: 598 %res = icmp ult <4 x i1> %a, %b 599 ret <4 x i1> %res 600; CHECK-LABEL: test_icmp_v4i1_ult 601; CHECK: pxor 602; CHECK: pcmpgtd 603 604; MIPS32-LABEL: test_icmp_v4i1_ult 605; MIPS32: lw [[T0:.*]], 606; MIPS32: lw [[T1:.*]], 607; MIPS32: lw [[T2:.*]], 608; MIPS32: lw [[T3:.*]], 609; MIPS32: andi [[T4:.*]],a0,0x1 610; MIPS32: andi [[T0]],[[T0]],0x1 611; MIPS32: sll [[T4]],[[T4]],0x1f 612; MIPS32: sll [[T0]],[[T0]],0x1f 613; MIPS32: sltu [[T4]],[[T4]],[[T0]] 614; MIPS32: andi [[T5:.*]],a1,0x1 615; MIPS32: andi [[T1]],[[T1]],0x1 616; MIPS32: sll [[T5]],[[T5]],0x1f 617; MIPS32: sll [[T1]],[[T1]],0x1f 618; MIPS32: sltu [[T5]],[[T5]],[[T1]] 619; MIPS32: andi [[T6:.*]],a2,0x1 620; MIPS32: andi [[T2]],[[T2]],0x1 621; MIPS32: sll [[T6]],[[T6]],0x1f 622; MIPS32: sll [[T2]],[[T2]],0x1f 623; MIPS32: sltu [[T6]],[[T6]],[[T2]] 624; MIPS32: andi [[T7:.*]],a3,0x1 625; MIPS32: andi [[T3]],[[T3]],0x1 626; MIPS32: sll [[T7]],[[T7]],0x1f 627; MIPS32: sll [[T3]],[[T3]],0x1f 628; MIPS32: sltu [[T7]],[[T7]],[[T3]] 629; MIPS32: move v0,[[T4]] 630; MIPS32: move v1,[[T5]] 631; MIPS32: move a0,[[T6]] 632; MIPS32: move a1,[[T7]] 633} 634 635define internal <8 x i1> @test_icmp_v8i16_eq(<8 x i16> %a, <8 x i16> %b) { 636entry: 637 %res = icmp eq <8 x i16> %a, %b 638 ret <8 x i1> %res 639; CHECK-LABEL: test_icmp_v8i16_eq 640; CHECK: pcmpeqw 641 642; MIPS32-LABEL: test_icmp_v8i16_eq 643; MIPS32: lw [[T0:.*]], 644; MIPS32: lw [[T1:.*]], 645; MIPS32: lw [[T2:.*]], 646; MIPS32: lw [[T3:.*]], 647; MIPS32: move [[T4:.*]],zero 648; MIPS32: move [[T5:.*]],zero 649; MIPS32: move [[T6:.*]],zero 650; MIPS32: move [[T7:.*]],zero 651; MIPS32: move [[T8:.*]],a0 652; MIPS32: andi [[T8]],[[T8]],0xffff 653; MIPS32: move [[T9:.*]],[[T0]] 654; MIPS32: andi [[T9]],[[T9]],0xffff 655; MIPS32: sll [[T8]],[[T8]],0x10 656; MIPS32: sll [[T9]],[[T9]],0x10 657; MIPS32: xor [[T8]],[[T8]],[[T9]] 658; MIPS32: sltiu [[T8]],[[T8]],1 659; MIPS32: andi [[T8]],[[T8]],0xffff 660; MIPS32: srl [[T4]],[[T4]],0x10 661; MIPS32: sll [[T4]],[[T4]],0x10 662; MIPS32: or [[T8]],[[T8]],[[T4]] 663; MIPS32: srl [[T10:.*]],a0,0x10 664; MIPS32: srl [[T0]],[[T0]],0x10 665; MIPS32: sll [[T10]],[[T10]],0x10 666; MIPS32: sll [[T0]],[[T0]],0x10 667; MIPS32: xor [[T10]],[[T10]],[[T0]] 668; MIPS32: sltiu [[T10]],[[T10]],1 669; MIPS32: sll [[T10]],[[T10]],0x10 670; MIPS32: sll [[T8]],[[T8]],0x10 671; MIPS32: srl [[T8]],[[T8]],0x10 672; MIPS32: or [[T10]],[[T10]],[[T8]] 673; MIPS32: move [[T0]],a1 674; MIPS32: andi [[T0]],[[T0]],0xffff 675; MIPS32: move [[T4]],[[T1]] 676; MIPS32: andi [[T4]],[[T4]],0xffff 677; MIPS32: sll [[T0]],[[T0]],0x10 678; MIPS32: sll [[T4]],[[T4]],0x10 679; MIPS32: xor [[T0]],[[T0]],[[T4]] 680; MIPS32: sltiu [[T0]],[[T0]],1 681; MIPS32: andi [[T0]],[[T0]],0xffff 682; MIPS32: srl [[T5]],[[T5]],0x10 683; MIPS32: sll [[T5]],[[T5]],0x10 684; MIPS32: or [[T0]],[[T0]],[[T5]] 685; MIPS32: srl [[T11:.*]],a1,0x10 686; MIPS32: srl [[T1]],[[T1]],0x10 687; MIPS32: sll [[T11]],[[T11]],0x10 688; MIPS32: sll [[T1]],[[T1]],0x10 689; MIPS32: xor [[T11]],[[T11]],[[T1]] 690; MIPS32: sltiu [[T11]],[[T11]],1 691; MIPS32: sll [[T11]],[[T11]],0x10 692; MIPS32: sll [[T0]],[[T0]],0x10 693; MIPS32: srl [[T0]],[[T0]],0x10 694; MIPS32: or [[T11]],[[T11]],[[T0]] 695; MIPS32: move [[T0]],a2 696; MIPS32: andi [[T0]],[[T0]],0xffff 697; MIPS32: move [[T1]],[[T2]] 698; MIPS32: andi [[T1]],[[T1]],0xffff 699; MIPS32: sll [[T0]],[[T0]],0x10 700; MIPS32: sll [[T1]],[[T1]],0x10 701; MIPS32: xor [[T0]],[[T0]],[[T1]] 702; MIPS32: sltiu [[T0]],[[T0]],1 703; MIPS32: andi [[T0]],[[T0]],0xffff 704; MIPS32: srl [[T6]],[[T6]],0x10 705; MIPS32: sll [[T6]],[[T6]],0x10 706; MIPS32: or [[T0]],[[T0]],[[T6]] 707; MIPS32: srl [[T12:.*]],a2,0x10 708; MIPS32: srl [[T2]],[[T2]],0x10 709; MIPS32: sll [[T12]],[[T12]],0x10 710; MIPS32: sll [[T2]],[[T2]],0x10 711; MIPS32: xor [[T12]],[[T12]],[[T2]] 712; MIPS32: sltiu [[T12]],[[T12]],1 713; MIPS32: sll [[T12]],[[T12]],0x10 714; MIPS32: sll [[T0]],[[T0]],0x10 715; MIPS32: srl [[T0]],[[T0]],0x10 716; MIPS32: or [[T12]],[[T12]],[[T0]] 717; MIPS32: move [[T0]],a3 718; MIPS32: andi [[T0]],[[T0]],0xffff 719; MIPS32: move [[T1]],[[T3]] 720; MIPS32: andi [[T1]],[[T1]],0xffff 721; MIPS32: sll [[T0]],[[T0]],0x10 722; MIPS32: sll [[T1]],[[T1]],0x10 723; MIPS32: xor [[T0]],[[T0]],[[T1]] 724; MIPS32: sltiu [[T0]],[[T0]],1 725; MIPS32: andi [[T0]],[[T0]],0xffff 726; MIPS32: srl [[T7]],[[T7]],0x10 727; MIPS32: sll [[T7]],[[T7]],0x10 728; MIPS32: or [[T0]],[[T0]],[[T7]] 729; MIPS32: srl [[T13:.*]],a3,0x10 730; MIPS32: srl [[T3]],[[T3]],0x10 731; MIPS32: sll [[T13]],[[T13]],0x10 732; MIPS32: sll [[T3]],[[T3]],0x10 733; MIPS32: xor [[T13]],[[T13]],[[T3]] 734; MIPS32: sltiu [[T13]],[[T13]],1 735; MIPS32: sll [[T13]],[[T13]],0x10 736; MIPS32: sll [[T0]],[[T0]],0x10 737; MIPS32: srl [[T0]],[[T0]],0x10 738; MIPS32: or [[T13]],[[T13]],[[T0]] 739; MIPS32: move v0,[[T10]] 740; MIPS32: move v1,[[T11]] 741; MIPS32: move a0,[[T12]] 742; MIPS32: move a1,[[T13]] 743} 744 745define internal <8 x i1> @test_icmp_v8i16_ne(<8 x i16> %a, <8 x i16> %b) { 746entry: 747 %res = icmp ne <8 x i16> %a, %b 748 ret <8 x i1> %res 749; CHECK-LABEL: test_icmp_v8i16_ne 750; CHECK: pcmpeqw 751; CHECK: pxor 752 753; MIPS32-LABEL: test_icmp_v8i16_ne 754; MIPS32: lw [[T0:.*]], 755; MIPS32: lw [[T1:.*]], 756; MIPS32: lw [[T2:.*]], 757; MIPS32: lw [[T3:.*]], 758; MIPS32: move [[T4:.*]],zero 759; MIPS32: move [[T5:.*]],zero 760; MIPS32: move [[T6:.*]],zero 761; MIPS32: move [[T7:.*]],zero 762; MIPS32: move [[T8:.*]],a0 763; MIPS32: andi [[T8]],[[T8]],0xffff 764; MIPS32: move [[T9:.*]],[[T0]] 765; MIPS32: andi [[T9]],[[T9]],0xffff 766; MIPS32: sll [[T8]],[[T8]],0x10 767; MIPS32: sll [[T9]],[[T9]],0x10 768; MIPS32: xor [[T8]],[[T8]],[[T9]] 769; MIPS32: sltu [[T8]],zero,[[T8]] 770; MIPS32: andi [[T8]],[[T8]],0xffff 771; MIPS32: srl [[T4]],[[T4]],0x10 772; MIPS32: sll [[T4]],[[T4]],0x10 773; MIPS32: or [[T8]],[[T8]],[[T4]] 774; MIPS32: srl [[T10:.*]],a0,0x10 775; MIPS32: srl [[T0]],[[T0]],0x10 776; MIPS32: sll [[T10]],[[T10]],0x10 777; MIPS32: sll [[T0]],[[T0]],0x10 778; MIPS32: xor [[T10]],[[T10]],[[T0]] 779; MIPS32: sltu [[T10]],zero,[[T10]] 780; MIPS32: sll [[T10]],[[T10]],0x10 781; MIPS32: sll [[T8]],[[T8]],0x10 782; MIPS32: srl [[T8]],[[T8]],0x10 783; MIPS32: or [[T10]],[[T10]],[[T8]] 784; MIPS32: move [[T0]],a1 785; MIPS32: andi [[T0]],[[T0]],0xffff 786; MIPS32: move [[T4]],[[T1]] 787; MIPS32: andi [[T4]],[[T4]],0xffff 788; MIPS32: sll [[T0]],[[T0]],0x10 789; MIPS32: sll [[T4]],[[T4]],0x10 790; MIPS32: xor [[T0]],[[T0]],[[T4]] 791; MIPS32: sltu [[T0]],zero,[[T0]] 792; MIPS32: andi [[T0]],[[T0]],0xffff 793; MIPS32: srl [[T5]],[[T5]],0x10 794; MIPS32: sll [[T5]],[[T5]],0x10 795; MIPS32: or [[T0]],[[T0]],[[T5]] 796; MIPS32: srl [[T11:.*]],a1,0x10 797; MIPS32: srl [[T1]],[[T1]],0x10 798; MIPS32: sll [[T11]],[[T11]],0x10 799; MIPS32: sll [[T1]],[[T1]],0x10 800; MIPS32: xor [[T11]],[[T11]],[[T1]] 801; MIPS32: sltu [[T11]],zero,[[T11]] 802; MIPS32: sll [[T11]],[[T11]],0x10 803; MIPS32: sll [[T0]],[[T0]],0x10 804; MIPS32: srl [[T0]],[[T0]],0x10 805; MIPS32: or [[T11]],[[T11]],[[T0]] 806; MIPS32: move [[T0]],a2 807; MIPS32: andi [[T0]],[[T0]],0xffff 808; MIPS32: move [[T1]],[[T2]] 809; MIPS32: andi [[T1]],[[T1]],0xffff 810; MIPS32: sll [[T0]],[[T0]],0x10 811; MIPS32: sll [[T1]],[[T1]],0x10 812; MIPS32: xor [[T0]],[[T0]],[[T1]] 813; MIPS32: sltu [[T0]],zero,[[T0]] 814; MIPS32: andi [[T0]],[[T0]],0xffff 815; MIPS32: srl [[T6]],[[T6]],0x10 816; MIPS32: sll [[T6]],[[T6]],0x10 817; MIPS32: or [[T0]],[[T0]],[[T6]] 818; MIPS32: srl [[T12:.*]],a2,0x10 819; MIPS32: srl [[T2]],[[T2]],0x10 820; MIPS32: sll [[T12]],[[T12]],0x10 821; MIPS32: sll [[T2]],[[T2]],0x10 822; MIPS32: xor [[T12]],[[T12]],[[T2]] 823; MIPS32: sltu [[T12]],zero,[[T12]] 824; MIPS32: sll [[T12]],[[T12]],0x10 825; MIPS32: sll [[T0]],[[T0]],0x10 826; MIPS32: srl [[T0]],[[T0]],0x10 827; MIPS32: or [[T12]],[[T12]],[[T0]] 828; MIPS32: move [[T0]],a3 829; MIPS32: andi [[T0]],[[T0]],0xffff 830; MIPS32: move [[T1]],[[T3]] 831; MIPS32: andi [[T1]],[[T1]],0xffff 832; MIPS32: sll [[T0]],[[T0]],0x10 833; MIPS32: sll [[T1]],[[T1]],0x10 834; MIPS32: xor [[T0]],[[T0]],[[T1]] 835; MIPS32: sltu [[T0]],zero,[[T0]] 836; MIPS32: andi [[T0]],[[T0]],0xffff 837; MIPS32: srl [[T7]],[[T7]],0x10 838; MIPS32: sll [[T7]],[[T7]],0x10 839; MIPS32: or [[T0]],[[T0]],[[T7]] 840; MIPS32: srl [[T13:.*]],a3,0x10 841; MIPS32: srl [[T3]],[[T3]],0x10 842; MIPS32: sll [[T13]],[[T13]],0x10 843; MIPS32: sll [[T3]],[[T3]],0x10 844; MIPS32: xor [[T13]],[[T13]],[[T3]] 845; MIPS32: sltu [[T13]],zero,[[T13]] 846; MIPS32: sll [[T13]],[[T13]],0x10 847; MIPS32: sll [[T0]],[[T0]],0x10 848; MIPS32: srl [[T0]],[[T0]],0x10 849; MIPS32: or [[T13]],[[T13]],[[T0]] 850; MIPS32: move v0,[[T10]] 851; MIPS32: move v1,[[T11]] 852; MIPS32: move a0,[[T12]] 853; MIPS32: move a1,[[T13]] 854} 855 856define internal <8 x i1> @test_icmp_v8i16_sgt(<8 x i16> %a, <8 x i16> %b) { 857entry: 858 %res = icmp sgt <8 x i16> %a, %b 859 ret <8 x i1> %res 860; CHECK-LABEL: test_icmp_v8i16_sgt 861; CHECK: pcmpgtw 862 863; MIPS32-LABEL: test_icmp_v8i16_sgt 864; MIPS32: lw [[T0:.*]], 865; MIPS32: lw [[T1:.*]], 866; MIPS32: lw [[T2:.*]], 867; MIPS32: lw [[T3:.*]], 868; MIPS32: move [[T4:.*]],zero 869; MIPS32: move [[T5:.*]],zero 870; MIPS32: move [[T6:.*]],zero 871; MIPS32: move [[T7:.*]],zero 872; MIPS32: move [[T8:.*]],a0 873; MIPS32: andi [[T8]],[[T8]],0xffff 874; MIPS32: move [[T9:.*]],[[T0]] 875; MIPS32: andi [[T9]],[[T9]],0xffff 876; MIPS32: sll [[T8]],[[T8]],0x10 877; MIPS32: sll [[T9]],[[T9]],0x10 878; MIPS32: slt [[T9]],[[T9]],[[T8]] 879; MIPS32: andi [[T9]],[[T9]],0xffff 880; MIPS32: srl [[T4]],[[T4]],0x10 881; MIPS32: sll [[T4]],[[T4]],0x10 882; MIPS32: or [[T9]],[[T9]],[[T4]] 883; MIPS32: srl [[T10:.*]],a0,0x10 884; MIPS32: srl [[T0]],[[T0]],0x10 885; MIPS32: sll [[T10]],[[T10]],0x10 886; MIPS32: sll [[T0]],[[T0]],0x10 887; MIPS32: slt [[T0]],[[T0]],[[T10]] 888; MIPS32: sll [[T0]],[[T0]],0x10 889; MIPS32: sll [[T9]],[[T9]],0x10 890; MIPS32: srl [[T9]],[[T9]],0x10 891; MIPS32: or v0,[[T0]],[[T9]] 892; MIPS32: move [[T10]],a1 893; MIPS32: andi [[T10]],[[T10]],0xffff 894; MIPS32: move [[T4]],[[T1]] 895; MIPS32: andi [[T4]],[[T4]],0xffff 896; MIPS32: sll [[T10]],[[T10]],0x10 897; MIPS32: sll [[T4]],[[T4]],0x10 898; MIPS32: slt [[T4]],[[T4]],[[T10]] 899; MIPS32: andi [[T4]],[[T4]],0xffff 900; MIPS32: srl [[T5]],[[T5]],0x10 901; MIPS32: sll [[T5]],[[T5]],0x10 902; MIPS32: or [[T4]],[[T4]],[[T5]] 903; MIPS32: srl [[T11:.*]],a1,0x10 904; MIPS32: srl [[T1]],[[T1]],0x10 905; MIPS32: sll [[T11]],[[T11]],0x10 906; MIPS32: sll [[T1]],[[T1]],0x10 907; MIPS32: slt [[T1]],[[T1]],[[T11]] 908; MIPS32: sll [[T1]],[[T1]],0x10 909; MIPS32: sll [[T4]],[[T4]],0x10 910; MIPS32: srl [[T4]],[[T4]],0x10 911; MIPS32: or v1,[[T1]],[[T4]] 912; MIPS32: move [[T10]],a2 913; MIPS32: andi [[T10]],[[T10]],0xffff 914; MIPS32: move [[T11]],[[T2]] 915; MIPS32: andi [[T11]],[[T11]],0xffff 916; MIPS32: sll [[T10]],[[T10]],0x10 917; MIPS32: sll [[T11]],[[T11]],0x10 918; MIPS32: slt [[T11]],[[T11]],[[T10]] 919; MIPS32: andi [[T11]],[[T11]],0xffff 920; MIPS32: srl [[T6]],[[T6]],0x10 921; MIPS32: sll [[T6]],[[T6]],0x10 922; MIPS32: or [[T11]],[[T11]],[[T6]] 923; MIPS32: srl [[T12:.*]],a2,0x10 924; MIPS32: srl [[T2]],[[T2]],0x10 925; MIPS32: sll [[T12]],[[T12]],0x10 926; MIPS32: sll [[T2]],[[T2]],0x10 927; MIPS32: slt [[T2]],[[T2]],[[T12]] 928; MIPS32: sll [[T2]],[[T2]],0x10 929; MIPS32: sll [[T11]],[[T11]],0x10 930; MIPS32: srl [[T11]],[[T11]],0x10 931; MIPS32: or [[T2]],[[T2]],[[T11]] 932; MIPS32: move [[T10]],a3 933; MIPS32: andi [[T10]],[[T10]],0xffff 934; MIPS32: move [[T11]],[[T3]] 935; MIPS32: andi [[T11]],[[T11]],0xffff 936; MIPS32: sll [[T10]],[[T10]],0x10 937; MIPS32: sll [[T11]],[[T11]],0x10 938; MIPS32: slt [[T11]],[[T11]],[[T10]] 939; MIPS32: andi [[T11]],[[T11]],0xffff 940; MIPS32: srl [[T7]],[[T7]],0x10 941; MIPS32: sll [[T7]],[[T7]],0x10 942; MIPS32: or [[T11]],[[T11]],[[T7]] 943; MIPS32: srl [[T13:.*]],a3,0x10 944; MIPS32: srl [[T3]],[[T3]],0x10 945; MIPS32: sll [[T13]],[[T13]],0x10 946; MIPS32: sll [[T3]],[[T3]],0x10 947; MIPS32: slt [[T3]],[[T3]],[[T13]] 948; MIPS32: sll [[T3]],[[T3]],0x10 949; MIPS32: sll [[T11]],[[T11]],0x10 950; MIPS32: srl [[T11]],[[T11]],0x10 951; MIPS32: or [[T3]],[[T3]],[[T11]] 952; MIPS32: move a0,[[T2]] 953; MIPS32: move a1,[[T3]] 954} 955 956define internal <8 x i1> @test_icmp_v8i16_sle(<8 x i16> %a, <8 x i16> %b) { 957entry: 958 %res = icmp sle <8 x i16> %a, %b 959 ret <8 x i1> %res 960; CHECK-LABEL: test_icmp_v8i16_sle 961; CHECK: pcmpgtw 962; CHECK: pxor 963 964; MIPS32-LABEL: test_icmp_v8i16_sle 965; MIPS32: lw [[T0:.*]], 966; MIPS32: lw [[T1:.*]], 967; MIPS32: lw [[T2:.*]], 968; MIPS32: lw [[T3:.*]], 969; MIPS32: move [[T4:.*]],zero 970; MIPS32: move [[T5:.*]],zero 971; MIPS32: move [[T6:.*]],zero 972; MIPS32: move [[T7:.*]],zero 973; MIPS32: move [[T8:.*]],a0 974; MIPS32: andi [[T8]],[[T8]],0xffff 975; MIPS32: move [[T9:.*]],[[T0]] 976; MIPS32: andi [[T9]],[[T9]],0xffff 977; MIPS32: sll [[T8]],[[T8]],0x10 978; MIPS32: sll [[T9]],[[T9]],0x10 979; MIPS32: slt [[T9]],[[T9]],[[T8]] 980; MIPS32: xori [[T9]],[[T9]],0x1 981; MIPS32: andi [[T9]],[[T9]],0xffff 982; MIPS32: srl [[T4]],[[T4]],0x10 983; MIPS32: sll [[T4]],[[T4]],0x10 984; MIPS32: or [[T9]],[[T9]],[[T4]] 985; MIPS32: srl [[T10:.*]],a0,0x10 986; MIPS32: srl [[T0]],[[T0]],0x10 987; MIPS32: sll [[T10]],[[T10]],0x10 988; MIPS32: sll [[T0]],[[T0]],0x10 989; MIPS32: slt [[T0]],[[T0]],[[T10]] 990; MIPS32: xori [[T0]],[[T0]],0x1 991; MIPS32: sll [[T0]],[[T0]],0x10 992; MIPS32: sll [[T9]],[[T9]],0x10 993; MIPS32: srl [[T9]],[[T9]],0x10 994; MIPS32: or v0,[[T0]],[[T9]] 995; MIPS32: move [[T10]],a1 996; MIPS32: andi [[T10]],[[T10]],0xffff 997; MIPS32: move [[T4]],[[T1]] 998; MIPS32: andi [[T4]],[[T4]],0xffff 999; MIPS32: sll [[T10]],[[T10]],0x10 1000; MIPS32: sll [[T4]],[[T4]],0x10 1001; MIPS32: slt [[T4]],[[T4]],[[T10]] 1002; MIPS32: xori [[T4]],[[T4]],0x1 1003; MIPS32: andi [[T4]],[[T4]],0xffff 1004; MIPS32: srl [[T5]],[[T5]],0x10 1005; MIPS32: sll [[T5]],[[T5]],0x10 1006; MIPS32: or [[T4]],[[T4]],[[T5]] 1007; MIPS32: srl [[T11:.*]],a1,0x10 1008; MIPS32: srl [[T1]],[[T1]],0x10 1009; MIPS32: sll [[T11]],[[T11]],0x10 1010; MIPS32: sll [[T1]],[[T1]],0x10 1011; MIPS32: slt [[T1]],[[T1]],[[T11]] 1012; MIPS32: xori [[T1]],[[T1]],0x1 1013; MIPS32: sll [[T1]],[[T1]],0x10 1014; MIPS32: sll [[T4]],[[T4]],0x10 1015; MIPS32: srl [[T4]],[[T4]],0x10 1016; MIPS32: or v1,[[T1]],[[T4]] 1017; MIPS32: move [[T10]],a2 1018; MIPS32: andi [[T10]],[[T10]],0xffff 1019; MIPS32: move [[T11]],[[T2]] 1020; MIPS32: andi [[T11]],[[T11]],0xffff 1021; MIPS32: sll [[T10]],[[T10]],0x10 1022; MIPS32: sll [[T11]],[[T11]],0x10 1023; MIPS32: slt [[T11]],[[T11]],[[T10]] 1024; MIPS32: xori [[T11]],[[T11]],0x1 1025; MIPS32: andi [[T11]],[[T11]],0xffff 1026; MIPS32: srl [[T6]],[[T6]],0x10 1027; MIPS32: sll [[T6]],[[T6]],0x10 1028; MIPS32: or [[T11]],[[T11]],[[T6]] 1029; MIPS32: srl [[T12:.*]],a2,0x10 1030; MIPS32: srl [[T2]],[[T2]],0x10 1031; MIPS32: sll [[T12]],[[T12]],0x10 1032; MIPS32: sll [[T2]],[[T2]],0x10 1033; MIPS32: slt [[T2]],[[T2]],[[T12]] 1034; MIPS32: xori [[T2]],[[T2]],0x1 1035; MIPS32: sll [[T2]],[[T2]],0x10 1036; MIPS32: sll [[T11]],[[T11]],0x10 1037; MIPS32: srl [[T11]],[[T11]],0x10 1038; MIPS32: or [[T2]],[[T2]],[[T11]] 1039; MIPS32: move [[T10]],a3 1040; MIPS32: andi [[T10]],[[T10]],0xffff 1041; MIPS32: move [[T11]],[[T3]] 1042; MIPS32: andi [[T11]],[[T11]],0xffff 1043; MIPS32: sll [[T10]],[[T10]],0x10 1044; MIPS32: sll [[T11]],[[T11]],0x10 1045; MIPS32: slt [[T11]],[[T11]],[[T10]] 1046; MIPS32: xori [[T11]],[[T11]],0x1 1047; MIPS32: andi [[T11]],[[T11]],0xffff 1048; MIPS32: srl [[T7]],[[T7]],0x10 1049; MIPS32: sll [[T7]],[[T7]],0x10 1050; MIPS32: or [[T11]],[[T11]],[[T7]] 1051; MIPS32: srl [[T13:.*]],a3,0x10 1052; MIPS32: srl [[T3]],[[T3]],0x10 1053; MIPS32: sll [[T13]],[[T13]],0x10 1054; MIPS32: sll [[T3]],[[T3]],0x10 1055; MIPS32: slt [[T3]],[[T3]],[[T13]] 1056; MIPS32: xori [[T3]],[[T3]],0x1 1057; MIPS32: sll [[T3]],[[T3]],0x10 1058; MIPS32: sll [[T11]],[[T11]],0x10 1059; MIPS32: srl [[T11]],[[T11]],0x10 1060; MIPS32: or [[T3]],[[T3]],[[T11]] 1061; MIPS32: move a0,[[T2]] 1062; MIPS32: move a1,[[T3]] 1063} 1064 1065define internal <8 x i1> @test_icmp_v8i16_slt(<8 x i16> %a, <8 x i16> %b) { 1066entry: 1067 %res = icmp slt <8 x i16> %a, %b 1068 ret <8 x i1> %res 1069; CHECK-LABEL: test_icmp_v8i16_slt 1070; CHECK: pcmpgtw 1071 1072; MIPS32-LABEL: test_icmp_v8i16_slt 1073; MIPS32: lw [[T0:.*]], 1074; MIPS32: lw [[T1:.*]], 1075; MIPS32: lw [[T2:.*]], 1076; MIPS32: lw [[T3:.*]], 1077; MIPS32: move [[T4:.*]],zero 1078; MIPS32: move [[T5:.*]],zero 1079; MIPS32: move [[T6:.*]],zero 1080; MIPS32: move [[T7:.*]],zero 1081; MIPS32: move [[T8:.*]],a0 1082; MIPS32: andi [[T8]],[[T8]],0xffff 1083; MIPS32: move [[T9:.*]],[[T0]] 1084; MIPS32: andi [[T9]],[[T9]],0xffff 1085; MIPS32: sll [[T8]],[[T8]],0x10 1086; MIPS32: sll [[T9]],[[T9]],0x10 1087; MIPS32: slt [[T8]],[[T8]],[[T9]] 1088; MIPS32: andi [[T8]],[[T8]],0xffff 1089; MIPS32: srl [[T4]],[[T4]],0x10 1090; MIPS32: sll [[T4]],[[T4]],0x10 1091; MIPS32: or [[T8]],[[T8]],[[T4]] 1092; MIPS32: srl [[T10:.*]],a0,0x10 1093; MIPS32: srl [[T0]],[[T0]],0x10 1094; MIPS32: sll [[T10]],[[T10]],0x10 1095; MIPS32: sll [[T0]],[[T0]],0x10 1096; MIPS32: slt [[T10]],[[T10]],[[T0]] 1097; MIPS32: sll [[T10]],[[T10]],0x10 1098; MIPS32: sll [[T8]],[[T8]],0x10 1099; MIPS32: srl [[T8]],[[T8]],0x10 1100; MIPS32: or [[T10]],[[T10]],[[T8]] 1101; MIPS32: move [[T0]],a1 1102; MIPS32: andi [[T0]],[[T0]],0xffff 1103; MIPS32: move [[T4]],[[T1]] 1104; MIPS32: andi [[T4]],[[T4]],0xffff 1105; MIPS32: sll [[T0]],[[T0]],0x10 1106; MIPS32: sll [[T4]],[[T4]],0x10 1107; MIPS32: slt [[T0]],[[T0]],[[T4]] 1108; MIPS32: andi [[T0]],[[T0]],0xffff 1109; MIPS32: srl [[T5]],[[T5]],0x10 1110; MIPS32: sll [[T5]],[[T5]],0x10 1111; MIPS32: or [[T0]],[[T0]],[[T5]] 1112; MIPS32: srl [[T11:.*]],a1,0x10 1113; MIPS32: srl [[T1]],[[T1]],0x10 1114; MIPS32: sll [[T11]],[[T11]],0x10 1115; MIPS32: sll [[T1]],[[T1]],0x10 1116; MIPS32: slt [[T11]],[[T11]],[[T1]] 1117; MIPS32: sll [[T11]],[[T11]],0x10 1118; MIPS32: sll [[T0]],[[T0]],0x10 1119; MIPS32: srl [[T0]],[[T0]],0x10 1120; MIPS32: or [[T11]],[[T11]],[[T0]] 1121; MIPS32: move [[T0]],a2 1122; MIPS32: andi [[T0]],[[T0]],0xffff 1123; MIPS32: move [[T1]],[[T2]] 1124; MIPS32: andi [[T1]],[[T1]],0xffff 1125; MIPS32: sll [[T0]],[[T0]],0x10 1126; MIPS32: sll [[T1]],[[T1]],0x10 1127; MIPS32: slt [[T0]],[[T0]],[[T1]] 1128; MIPS32: andi [[T0]],[[T0]],0xffff 1129; MIPS32: srl [[T6]],[[T6]],0x10 1130; MIPS32: sll [[T6]],[[T6]],0x10 1131; MIPS32: or [[T0]],[[T0]],[[T6]] 1132; MIPS32: srl [[T12:.*]],a2,0x10 1133; MIPS32: srl [[T2]],[[T2]],0x10 1134; MIPS32: sll [[T12]],[[T12]],0x10 1135; MIPS32: sll [[T2]],[[T2]],0x10 1136; MIPS32: slt [[T12]],[[T12]],[[T2]] 1137; MIPS32: sll [[T12]],[[T12]],0x10 1138; MIPS32: sll [[T0]],[[T0]],0x10 1139; MIPS32: srl [[T0]],[[T0]],0x10 1140; MIPS32: or [[T12]],[[T12]],[[T0]] 1141; MIPS32: move [[T0]],a3 1142; MIPS32: andi [[T0]],[[T0]],0xffff 1143; MIPS32: move [[T1]],[[T3]] 1144; MIPS32: andi [[T1]],[[T1]],0xffff 1145; MIPS32: sll [[T0]],[[T0]],0x10 1146; MIPS32: sll [[T1]],[[T1]],0x10 1147; MIPS32: slt [[T0]],[[T0]],[[T1]] 1148; MIPS32: andi [[T0]],[[T0]],0xffff 1149; MIPS32: srl [[T7]],[[T7]],0x10 1150; MIPS32: sll [[T7]],[[T7]],0x10 1151; MIPS32: or [[T0]],[[T0]],[[T7]] 1152; MIPS32: srl [[T13:.*]],a3,0x10 1153; MIPS32: srl [[T3]],[[T3]],0x10 1154; MIPS32: sll [[T13]],[[T13]],0x10 1155; MIPS32: sll [[T3]],[[T3]],0x10 1156; MIPS32: slt [[T13]],[[T13]],[[T3]] 1157; MIPS32: sll [[T13]],[[T13]],0x10 1158; MIPS32: sll [[T0]],[[T0]],0x10 1159; MIPS32: srl [[T0]],[[T0]],0x10 1160; MIPS32: or [[T13]],[[T13]],[[T0]] 1161; MIPS32: move v0,[[T10]] 1162; MIPS32: move v1,[[T11]] 1163; MIPS32: move a0,[[T12]] 1164; MIPS32: move a1,[[T13]] 1165} 1166 1167define internal <8 x i1> @test_icmp_v8i16_uge(<8 x i16> %a, <8 x i16> %b) { 1168entry: 1169 %res = icmp uge <8 x i16> %a, %b 1170 ret <8 x i1> %res 1171; CHECK-LABEL: test_icmp_v8i16_uge 1172; CHECK: pxor 1173; CHECK: pcmpgtw 1174; CHECK: pxor 1175 1176; MIPS32-LABEL: test_icmp_v8i16_uge 1177; MIPS32: lw [[T0:.*]], 1178; MIPS32: lw [[T1:.*]], 1179; MIPS32: lw [[T2:.*]], 1180; MIPS32: lw [[T3:.*]], 1181; MIPS32: move [[T4:.*]],zero 1182; MIPS32: move [[T5:.*]],zero 1183; MIPS32: move [[T6:.*]],zero 1184; MIPS32: move [[T7:.*]],zero 1185; MIPS32: move [[T8:.*]],a0 1186; MIPS32: andi [[T8]],[[T8]],0xffff 1187; MIPS32: move [[T9:.*]],[[T0]] 1188; MIPS32: andi [[T9]],[[T9]],0xffff 1189; MIPS32: sll [[T8]],[[T8]],0x10 1190; MIPS32: sll [[T9]],[[T9]],0x10 1191; MIPS32: sltu [[T8]],[[T8]],[[T9]] 1192; MIPS32: xori [[T8]],[[T8]],0x1 1193; MIPS32: andi [[T8]],[[T8]],0xffff 1194; MIPS32: srl [[T4]],[[T4]],0x10 1195; MIPS32: sll [[T4]],[[T4]],0x10 1196; MIPS32: or [[T8]],[[T8]],[[T4]] 1197; MIPS32: srl [[T10:.*]],a0,0x10 1198; MIPS32: srl [[T0]],[[T0]],0x10 1199; MIPS32: sll [[T10]],[[T10]],0x10 1200; MIPS32: sll [[T0]],[[T0]],0x10 1201; MIPS32: sltu [[T10]],[[T10]],[[T0]] 1202; MIPS32: xori [[T10]],[[T10]],0x1 1203; MIPS32: sll [[T10]],[[T10]],0x10 1204; MIPS32: sll [[T8]],[[T8]],0x10 1205; MIPS32: srl [[T8]],[[T8]],0x10 1206; MIPS32: or [[T10]],[[T10]],[[T8]] 1207; MIPS32: move [[T0]],a1 1208; MIPS32: andi [[T0]],[[T0]],0xffff 1209; MIPS32: move [[T4]],[[T1]] 1210; MIPS32: andi [[T4]],[[T4]],0xffff 1211; MIPS32: sll [[T0]],[[T0]],0x10 1212; MIPS32: sll [[T4]],[[T4]],0x10 1213; MIPS32: sltu [[T0]],[[T0]],[[T4]] 1214; MIPS32: xori [[T0]],[[T0]],0x1 1215; MIPS32: andi [[T0]],[[T0]],0xffff 1216; MIPS32: srl [[T5]],[[T5]],0x10 1217; MIPS32: sll [[T5]],[[T5]],0x10 1218; MIPS32: or [[T0]],[[T0]],[[T5]] 1219; MIPS32: srl [[T11:.*]],a1,0x10 1220; MIPS32: srl [[T1]],[[T1]],0x10 1221; MIPS32: sll [[T11]],[[T11]],0x10 1222; MIPS32: sll [[T1]],[[T1]],0x10 1223; MIPS32: sltu [[T11]],[[T11]],[[T1]] 1224; MIPS32: xori [[T11]],[[T11]],0x1 1225; MIPS32: sll [[T11]],[[T11]],0x10 1226; MIPS32: sll [[T0]],[[T0]],0x10 1227; MIPS32: srl [[T0]],[[T0]],0x10 1228; MIPS32: or [[T11]],[[T11]],[[T0]] 1229; MIPS32: move [[T0]],a2 1230; MIPS32: andi [[T0]],[[T0]],0xffff 1231; MIPS32: move [[T1]],[[T2]] 1232; MIPS32: andi [[T1]],[[T1]],0xffff 1233; MIPS32: sll [[T0]],[[T0]],0x10 1234; MIPS32: sll [[T1]],[[T1]],0x10 1235; MIPS32: sltu [[T0]],[[T0]],[[T1]] 1236; MIPS32: xori [[T0]],[[T0]],0x1 1237; MIPS32: andi [[T0]],[[T0]],0xffff 1238; MIPS32: srl [[T6]],[[T6]],0x10 1239; MIPS32: sll [[T6]],[[T6]],0x10 1240; MIPS32: or [[T0]],[[T0]],[[T6]] 1241; MIPS32: srl [[T12:.*]],a2,0x10 1242; MIPS32: srl [[T2]],[[T2]],0x10 1243; MIPS32: sll [[T12]],[[T12]],0x10 1244; MIPS32: sll [[T2]],[[T2]],0x10 1245; MIPS32: sltu [[T12]],[[T12]],[[T2]] 1246; MIPS32: xori [[T12]],[[T12]],0x1 1247; MIPS32: sll [[T12]],[[T12]],0x10 1248; MIPS32: sll [[T0]],[[T0]],0x10 1249; MIPS32: srl [[T0]],[[T0]],0x10 1250; MIPS32: or [[T12]],[[T12]],[[T0]] 1251; MIPS32: move [[T0]],a3 1252; MIPS32: andi [[T0]],[[T0]],0xffff 1253; MIPS32: move [[T1]],[[T3]] 1254; MIPS32: andi [[T1]],[[T1]],0xffff 1255; MIPS32: sll [[T0]],[[T0]],0x10 1256; MIPS32: sll [[T1]],[[T1]],0x10 1257; MIPS32: sltu [[T0]],[[T0]],[[T1]] 1258; MIPS32: xori [[T0]],[[T0]],0x1 1259; MIPS32: andi [[T0]],[[T0]],0xffff 1260; MIPS32: srl [[T7]],[[T7]],0x10 1261; MIPS32: sll [[T7]],[[T7]],0x10 1262; MIPS32: or [[T0]],[[T0]],[[T7]] 1263; MIPS32: srl [[T13:.*]],a3,0x10 1264; MIPS32: srl [[T3]],[[T3]],0x10 1265; MIPS32: sll [[T13]],[[T13]],0x10 1266; MIPS32: sll [[T3]],[[T3]],0x10 1267; MIPS32: sltu [[T13]],[[T13]],[[T3]] 1268; MIPS32: xori [[T13]],[[T13]],0x1 1269; MIPS32: sll [[T13]],[[T13]],0x10 1270; MIPS32: sll [[T0]],[[T0]],0x10 1271; MIPS32: srl [[T0]],[[T0]],0x10 1272; MIPS32: or [[T13]],[[T13]],[[T0]] 1273; MIPS32: move v0,[[T10]] 1274; MIPS32: move v1,[[T11]] 1275; MIPS32: move a0,[[T12]] 1276; MIPS32: move a1,[[T13]] 1277} 1278 1279define internal <8 x i1> @test_icmp_v8i16_ugt(<8 x i16> %a, <8 x i16> %b) { 1280entry: 1281 %res = icmp ugt <8 x i16> %a, %b 1282 ret <8 x i1> %res 1283; CHECK-LABEL: test_icmp_v8i16_ugt 1284; CHECK: pxor 1285; CHECK: pcmpgtw 1286 1287; MIPS32-LABEL: test_icmp_v8i16_ugt 1288; MIPS32: lw [[T0:.*]], 1289; MIPS32: lw [[T1:.*]], 1290; MIPS32: lw [[T2:.*]], 1291; MIPS32: lw [[T3:.*]], 1292; MIPS32: move [[T4:.*]],zero 1293; MIPS32: move [[T5:.*]],zero 1294; MIPS32: move [[T6:.*]],zero 1295; MIPS32: move [[T7:.*]],zero 1296; MIPS32: move [[T8:.*]],a0 1297; MIPS32: andi [[T8]],[[T8]],0xffff 1298; MIPS32: move [[T9:.*]],[[T0]] 1299; MIPS32: andi [[T9]],[[T9]],0xffff 1300; MIPS32: sll [[T8]],[[T8]],0x10 1301; MIPS32: sll [[T9]],[[T9]],0x10 1302; MIPS32: sltu [[T9]],[[T9]],[[T8]] 1303; MIPS32: andi [[T9]],[[T9]],0xffff 1304; MIPS32: srl [[T4]],[[T4]],0x10 1305; MIPS32: sll [[T4]],[[T4]],0x10 1306; MIPS32: or [[T9]],[[T9]],[[T4]] 1307; MIPS32: srl [[T10:.*]],a0,0x10 1308; MIPS32: srl [[T0]],[[T0]],0x10 1309; MIPS32: sll [[T10]],[[T10]],0x10 1310; MIPS32: sll [[T0]],[[T0]],0x10 1311; MIPS32: sltu [[T0]],[[T0]],[[T10]] 1312; MIPS32: sll [[T0]],[[T0]],0x10 1313; MIPS32: sll [[T9]],[[T9]],0x10 1314; MIPS32: srl [[T9]],[[T9]],0x10 1315; MIPS32: or v0,[[T0]],[[T9]] 1316; MIPS32: move [[T10]],a1 1317; MIPS32: andi [[T10]],[[T10]],0xffff 1318; MIPS32: move [[T4]],[[T1]] 1319; MIPS32: andi [[T4]],[[T4]],0xffff 1320; MIPS32: sll [[T10]],[[T10]],0x10 1321; MIPS32: sll [[T4]],[[T4]],0x10 1322; MIPS32: sltu [[T4]],[[T4]],[[T10]] 1323; MIPS32: andi [[T4]],[[T4]],0xffff 1324; MIPS32: srl [[T5]],[[T5]],0x10 1325; MIPS32: sll [[T5]],[[T5]],0x10 1326; MIPS32: or [[T4]],[[T4]],[[T5]] 1327; MIPS32: srl [[T11:.*]],a1,0x10 1328; MIPS32: srl [[T1]],[[T1]],0x10 1329; MIPS32: sll [[T11]],[[T11]],0x10 1330; MIPS32: sll [[T1]],[[T1]],0x10 1331; MIPS32: sltu [[T1]],[[T1]],[[T11]] 1332; MIPS32: sll [[T1]],[[T1]],0x10 1333; MIPS32: sll [[T4]],[[T4]],0x10 1334; MIPS32: srl [[T4]],[[T4]],0x10 1335; MIPS32: or v1,[[T1]],[[T4]] 1336; MIPS32: move [[T10]],a2 1337; MIPS32: andi [[T10]],[[T10]],0xffff 1338; MIPS32: move [[T11]],[[T2]] 1339; MIPS32: andi [[T11]],[[T11]],0xffff 1340; MIPS32: sll [[T10]],[[T10]],0x10 1341; MIPS32: sll [[T11]],[[T11]],0x10 1342; MIPS32: sltu [[T11]],[[T11]],[[T10]] 1343; MIPS32: andi [[T11]],[[T11]],0xffff 1344; MIPS32: srl [[T6]],[[T6]],0x10 1345; MIPS32: sll [[T6]],[[T6]],0x10 1346; MIPS32: or [[T11]],[[T11]],[[T6]] 1347; MIPS32: srl [[T12:.*]],a2,0x10 1348; MIPS32: srl [[T2]],[[T2]],0x10 1349; MIPS32: sll [[T12]],[[T12]],0x10 1350; MIPS32: sll [[T2]],[[T2]],0x10 1351; MIPS32: sltu [[T2]],[[T2]],[[T12]] 1352; MIPS32: sll [[T2]],[[T2]],0x10 1353; MIPS32: sll [[T11]],[[T11]],0x10 1354; MIPS32: srl [[T11]],[[T11]],0x10 1355; MIPS32: or [[T2]],[[T2]],[[T11]] 1356; MIPS32: move [[T10]],a3 1357; MIPS32: andi [[T10]],[[T10]],0xffff 1358; MIPS32: move [[T11]],[[T3]] 1359; MIPS32: andi [[T11]],[[T11]],0xffff 1360; MIPS32: sll [[T10]],[[T10]],0x10 1361; MIPS32: sll [[T11]],[[T11]],0x10 1362; MIPS32: sltu [[T11]],[[T11]],[[T10]] 1363; MIPS32: andi [[T11]],[[T11]],0xffff 1364; MIPS32: srl [[T7]],[[T7]],0x10 1365; MIPS32: sll [[T7]],[[T7]],0x10 1366; MIPS32: or [[T11]],[[T11]],[[T7]] 1367; MIPS32: srl [[T13:.*]],a3,0x10 1368; MIPS32: srl [[T3]],[[T3]],0x10 1369; MIPS32: sll [[T13]],[[T13]],0x10 1370; MIPS32: sll [[T3]],[[T3]],0x10 1371; MIPS32: sltu [[T3]],[[T3]],[[T13]] 1372; MIPS32: sll [[T3]],[[T3]],0x10 1373; MIPS32: sll [[T11]],[[T11]],0x10 1374; MIPS32: srl [[T11]],[[T11]],0x10 1375; MIPS32: or [[T3]],[[T3]],[[T11]] 1376; MIPS32: move a0,[[T2]] 1377; MIPS32: move a1,[[T3]] 1378} 1379 1380define internal <8 x i1> @test_icmp_v8i16_ule(<8 x i16> %a, <8 x i16> %b) { 1381entry: 1382 %res = icmp ule <8 x i16> %a, %b 1383 ret <8 x i1> %res 1384; CHECK-LABEL: test_icmp_v8i16_ule 1385; CHECK: pxor 1386; CHECK: pcmpgtw 1387; CHECK: pxor 1388 1389; MIPS32-LABEL: test_icmp_v8i16_ule 1390; MIPS32: lw [[T0:.*]], 1391; MIPS32: lw [[T1:.*]], 1392; MIPS32: lw [[T2:.*]], 1393; MIPS32: lw [[T3:.*]], 1394; MIPS32: move [[T4:.*]],zero 1395; MIPS32: move [[T5:.*]],zero 1396; MIPS32: move [[T6:.*]],zero 1397; MIPS32: move [[T7:.*]],zero 1398; MIPS32: move [[T8:.*]],a0 1399; MIPS32: andi [[T8]],[[T8]],0xffff 1400; MIPS32: move [[T9:.*]],[[T0]] 1401; MIPS32: andi [[T9]],[[T9]],0xffff 1402; MIPS32: sll [[T8]],[[T8]],0x10 1403; MIPS32: sll [[T9]],[[T9]],0x10 1404; MIPS32: sltu [[T9]],[[T9]],[[T8]] 1405; MIPS32: xori [[T9]],[[T9]],0x1 1406; MIPS32: andi [[T9]],[[T9]],0xffff 1407; MIPS32: srl [[T4]],[[T4]],0x10 1408; MIPS32: sll [[T4]],[[T4]],0x10 1409; MIPS32: or [[T9]],[[T9]],[[T4]] 1410; MIPS32: srl [[T10:.*]],a0,0x10 1411; MIPS32: srl [[T0]],[[T0]],0x10 1412; MIPS32: sll [[T10]],[[T10]],0x10 1413; MIPS32: sll [[T0]],[[T0]],0x10 1414; MIPS32: sltu [[T0]],[[T0]],[[T10]] 1415; MIPS32: xori [[T0]],[[T0]],0x1 1416; MIPS32: sll [[T0]],[[T0]],0x10 1417; MIPS32: sll [[T9]],[[T9]],0x10 1418; MIPS32: srl [[T9]],[[T9]],0x10 1419; MIPS32: or v0,[[T0]],[[T9]] 1420; MIPS32: move [[T10]],a1 1421; MIPS32: andi [[T10]],[[T10]],0xffff 1422; MIPS32: move [[T4]],[[T1]] 1423; MIPS32: andi [[T4]],[[T4]],0xffff 1424; MIPS32: sll [[T10]],[[T10]],0x10 1425; MIPS32: sll [[T4]],[[T4]],0x10 1426; MIPS32: sltu [[T4]],[[T4]],[[T10]] 1427; MIPS32: xori [[T4]],[[T4]],0x1 1428; MIPS32: andi [[T4]],[[T4]],0xffff 1429; MIPS32: srl [[T5]],[[T5]],0x10 1430; MIPS32: sll [[T5]],[[T5]],0x10 1431; MIPS32: or [[T4]],[[T4]],[[T5]] 1432; MIPS32: srl [[T11:.*]],a1,0x10 1433; MIPS32: srl [[T1]],[[T1]],0x10 1434; MIPS32: sll [[T11]],[[T11]],0x10 1435; MIPS32: sll [[T1]],[[T1]],0x10 1436; MIPS32: sltu [[T1]],[[T1]],[[T11]] 1437; MIPS32: xori [[T1]],[[T1]],0x1 1438; MIPS32: sll [[T1]],[[T1]],0x10 1439; MIPS32: sll [[T4]],[[T4]],0x10 1440; MIPS32: srl [[T4]],[[T4]],0x10 1441; MIPS32: or v1,[[T1]],[[T4]] 1442; MIPS32: move [[T10]],a2 1443; MIPS32: andi [[T10]],[[T10]],0xffff 1444; MIPS32: move [[T11]],[[T2]] 1445; MIPS32: andi [[T11]],[[T11]],0xffff 1446; MIPS32: sll [[T10]],[[T10]],0x10 1447; MIPS32: sll [[T11]],[[T11]],0x10 1448; MIPS32: sltu [[T11]],[[T11]],[[T10]] 1449; MIPS32: xori [[T11]],[[T11]],0x1 1450; MIPS32: andi [[T11]],[[T11]],0xffff 1451; MIPS32: srl [[T6]],[[T6]],0x10 1452; MIPS32: sll [[T6]],[[T6]],0x10 1453; MIPS32: or [[T11]],[[T11]],[[T6]] 1454; MIPS32: srl [[T12:.*]],a2,0x10 1455; MIPS32: srl [[T2]],[[T2]],0x10 1456; MIPS32: sll [[T12]],[[T12]],0x10 1457; MIPS32: sll [[T2]],[[T2]],0x10 1458; MIPS32: sltu [[T2]],[[T2]],[[T12]] 1459; MIPS32: xori [[T2]],[[T2]],0x1 1460; MIPS32: sll [[T2]],[[T2]],0x10 1461; MIPS32: sll [[T11]],[[T11]],0x10 1462; MIPS32: srl [[T11]],[[T11]],0x10 1463; MIPS32: or [[T2]],[[T2]],[[T11]] 1464; MIPS32: move [[T10]],a3 1465; MIPS32: andi [[T10]],[[T10]],0xffff 1466; MIPS32: move [[T11]],[[T3]] 1467; MIPS32: andi [[T11]],[[T11]],0xffff 1468; MIPS32: sll [[T10]],[[T10]],0x10 1469; MIPS32: sll [[T11]],[[T11]],0x10 1470; MIPS32: sltu [[T11]],[[T11]],[[T10]] 1471; MIPS32: xori [[T11]],[[T11]],0x1 1472; MIPS32: andi [[T11]],[[T11]],0xffff 1473; MIPS32: srl [[T7]],[[T7]],0x10 1474; MIPS32: sll [[T7]],[[T7]],0x10 1475; MIPS32: or [[T11]],[[T11]],[[T7]] 1476; MIPS32: srl [[T13:.*]],a3,0x10 1477; MIPS32: srl [[T3]],[[T3]],0x10 1478; MIPS32: sll [[T13]],[[T13]],0x10 1479; MIPS32: sll [[T3]],[[T3]],0x10 1480; MIPS32: sltu [[T3]],[[T3]],[[T13]] 1481; MIPS32: xori [[T3]],[[T3]],0x1 1482; MIPS32: sll [[T3]],[[T3]],0x10 1483; MIPS32: sll [[T11]],[[T11]],0x10 1484; MIPS32: srl [[T11]],[[T11]],0x10 1485; MIPS32: or [[T3]],[[T3]],[[T11]] 1486; MIPS32: move a0,[[T2]] 1487; MIPS32: move a1,[[T3]] 1488} 1489 1490define internal <8 x i1> @test_icmp_v8i16_ult(<8 x i16> %a, <8 x i16> %b) { 1491entry: 1492 %res = icmp ult <8 x i16> %a, %b 1493 ret <8 x i1> %res 1494; CHECK-LABEL: test_icmp_v8i16_ult 1495; CHECK: pxor 1496; CHECK: pcmpgtw 1497 1498; MIPS32-LABEL: test_icmp_v8i16_ult 1499; MIPS32: lw [[T0:.*]], 1500; MIPS32: lw [[T1:.*]], 1501; MIPS32: lw [[T2:.*]], 1502; MIPS32: lw [[T3:.*]], 1503; MIPS32: move [[T4:.*]],zero 1504; MIPS32: move [[T5:.*]],zero 1505; MIPS32: move [[T6:.*]],zero 1506; MIPS32: move [[T7:.*]],zero 1507; MIPS32: move [[T8:.*]],a0 1508; MIPS32: andi [[T8]],[[T8]],0xffff 1509; MIPS32: move [[T9:.*]],[[T0]] 1510; MIPS32: andi [[T9]],[[T9]],0xffff 1511; MIPS32: sll [[T8]],[[T8]],0x10 1512; MIPS32: sll [[T9]],[[T9]],0x10 1513; MIPS32: sltu [[T8]],[[T8]],[[T9]] 1514; MIPS32: andi [[T8]],[[T8]],0xffff 1515; MIPS32: srl [[T4]],[[T4]],0x10 1516; MIPS32: sll [[T4]],[[T4]],0x10 1517; MIPS32: or [[T8]],[[T8]],[[T4]] 1518; MIPS32: srl [[T10:.*]],a0,0x10 1519; MIPS32: srl [[T0]],[[T0]],0x10 1520; MIPS32: sll [[T10]],[[T10]],0x10 1521; MIPS32: sll [[T0]],[[T0]],0x10 1522; MIPS32: sltu [[T10]],[[T10]],[[T0]] 1523; MIPS32: sll [[T10]],[[T10]],0x10 1524; MIPS32: sll [[T8]],[[T8]],0x10 1525; MIPS32: srl [[T8]],[[T8]],0x10 1526; MIPS32: or [[T10]],[[T10]],[[T8]] 1527; MIPS32: move [[T0]],a1 1528; MIPS32: andi [[T0]],[[T0]],0xffff 1529; MIPS32: move [[T4]],[[T1]] 1530; MIPS32: andi [[T4]],[[T4]],0xffff 1531; MIPS32: sll [[T0]],[[T0]],0x10 1532; MIPS32: sll [[T4]],[[T4]],0x10 1533; MIPS32: sltu [[T0]],[[T0]],[[T4]] 1534; MIPS32: andi [[T0]],[[T0]],0xffff 1535; MIPS32: srl [[T5]],[[T5]],0x10 1536; MIPS32: sll [[T5]],[[T5]],0x10 1537; MIPS32: or [[T0]],[[T0]],[[T5]] 1538; MIPS32: srl [[T11:.*]],a1,0x10 1539; MIPS32: srl [[T1]],[[T1]],0x10 1540; MIPS32: sll [[T11]],[[T11]],0x10 1541; MIPS32: sll [[T1]],[[T1]],0x10 1542; MIPS32: sltu [[T11]],[[T11]],[[T1]] 1543; MIPS32: sll [[T11]],[[T11]],0x10 1544; MIPS32: sll [[T0]],[[T0]],0x10 1545; MIPS32: srl [[T0]],[[T0]],0x10 1546; MIPS32: or [[T11]],[[T11]],[[T0]] 1547; MIPS32: move [[T0]],a2 1548; MIPS32: andi [[T0]],[[T0]],0xffff 1549; MIPS32: move [[T1]],[[T2]] 1550; MIPS32: andi [[T1]],[[T1]],0xffff 1551; MIPS32: sll [[T0]],[[T0]],0x10 1552; MIPS32: sll [[T1]],[[T1]],0x10 1553; MIPS32: sltu [[T0]],[[T0]],[[T1]] 1554; MIPS32: andi [[T0]],[[T0]],0xffff 1555; MIPS32: srl [[T6]],[[T6]],0x10 1556; MIPS32: sll [[T6]],[[T6]],0x10 1557; MIPS32: or [[T0]],[[T0]],[[T6]] 1558; MIPS32: srl [[T12:.*]],a2,0x10 1559; MIPS32: srl [[T2]],[[T2]],0x10 1560; MIPS32: sll [[T12]],[[T12]],0x10 1561; MIPS32: sll [[T2]],[[T2]],0x10 1562; MIPS32: sltu [[T12]],[[T12]],[[T2]] 1563; MIPS32: sll [[T12]],[[T12]],0x10 1564; MIPS32: sll [[T0]],[[T0]],0x10 1565; MIPS32: srl [[T0]],[[T0]],0x10 1566; MIPS32: or [[T12]],[[T12]],[[T0]] 1567; MIPS32: move [[T0]],a3 1568; MIPS32: andi [[T0]],[[T0]],0xffff 1569; MIPS32: move [[T1]],[[T3]] 1570; MIPS32: andi [[T1]],[[T1]],0xffff 1571; MIPS32: sll [[T0]],[[T0]],0x10 1572; MIPS32: sll [[T1]],[[T1]],0x10 1573; MIPS32: sltu [[T0]],[[T0]],[[T1]] 1574; MIPS32: andi [[T0]],[[T0]],0xffff 1575; MIPS32: srl [[T7]],[[T7]],0x10 1576; MIPS32: sll [[T7]],[[T7]],0x10 1577; MIPS32: or [[T0]],[[T0]],[[T7]] 1578; MIPS32: srl [[T13:.*]],a3,0x10 1579; MIPS32: srl [[T3]],[[T3]],0x10 1580; MIPS32: sll [[T13]],[[T13]],0x10 1581; MIPS32: sll [[T3]],[[T3]],0x10 1582; MIPS32: sltu [[T13]],[[T13]],[[T3]] 1583; MIPS32: sll [[T13]],[[T13]],0x10 1584; MIPS32: sll [[T0]],[[T0]],0x10 1585; MIPS32: srl [[T0]],[[T0]],0x10 1586; MIPS32: or [[T13]],[[T13]],[[T0]] 1587; MIPS32: move v0,[[T10]] 1588; MIPS32: move v1,[[T11]] 1589; MIPS32: move a0,[[T12]] 1590; MIPS32: move a1,[[T13]] 1591} 1592 1593define internal <8 x i1> @test_icmp_v8i1_eq(<8 x i1> %a, <8 x i1> %b) { 1594entry: 1595 %res = icmp eq <8 x i1> %a, %b 1596 ret <8 x i1> %res 1597; CHECK-LABEL: test_icmp_v8i1_eq 1598; CHECK: pcmpeqw 1599 1600; MIPS32-LABEL: test_icmp_v8i1_eq 1601; MIPS32: lw [[T0:.*]], 1602; MIPS32: lw [[T1:.*]], 1603; MIPS32: lw [[T2:.*]], 1604; MIPS32: lw [[T3:.*]], 1605; MIPS32: move [[T4:.*]],zero 1606; MIPS32: move [[T5:.*]],zero 1607; MIPS32: move [[T6:.*]],zero 1608; MIPS32: move [[T7:.*]],zero 1609; MIPS32: move [[T8:.*]],a0 1610; MIPS32: andi [[T8]],[[T8]],0xffff 1611; MIPS32: andi [[T8]],[[T8]],0x1 1612; MIPS32: move [[T9:.*]],[[T0]] 1613; MIPS32: andi [[T9]],[[T9]],0xffff 1614; MIPS32: andi [[T9]],[[T9]],0x1 1615; MIPS32: sll [[T8]],[[T8]],0x1f 1616; MIPS32: sll [[T9]],[[T9]],0x1f 1617; MIPS32: xor [[T8]],[[T8]],[[T9]] 1618; MIPS32: sltiu [[T8]],[[T8]],1 1619; MIPS32: andi [[T8]],[[T8]],0xffff 1620; MIPS32: srl [[T4]],[[T4]],0x10 1621; MIPS32: sll [[T4]],[[T4]],0x10 1622; MIPS32: or [[T8]],[[T8]],[[T4]] 1623; MIPS32: srl [[T10:.*]],a0,0x10 1624; MIPS32: andi [[T10]],[[T10]],0x1 1625; MIPS32: srl [[T0]],[[T0]],0x10 1626; MIPS32: andi [[T0]],[[T0]],0x1 1627; MIPS32: sll [[T10]],[[T10]],0x1f 1628; MIPS32: sll [[T0]],[[T0]],0x1f 1629; MIPS32: xor [[T10]],[[T10]],[[T0]] 1630; MIPS32: sltiu [[T10]],[[T10]],1 1631; MIPS32: sll [[T10]],[[T10]],0x10 1632; MIPS32: sll [[T8]],[[T8]],0x10 1633; MIPS32: srl [[T8]],[[T8]],0x10 1634; MIPS32: or [[T10]],[[T10]],[[T8]] 1635; MIPS32: move [[T0]],a1 1636; MIPS32: andi [[T0]],[[T0]],0xffff 1637; MIPS32: andi [[T0]],[[T0]],0x1 1638; MIPS32: move [[T4]],[[T1]] 1639; MIPS32: andi [[T4]],[[T4]],0xffff 1640; MIPS32: andi [[T4]],[[T4]],0x1 1641; MIPS32: sll [[T0]],[[T0]],0x1f 1642; MIPS32: sll [[T4]],[[T4]],0x1f 1643; MIPS32: xor [[T0]],[[T0]],[[T4]] 1644; MIPS32: sltiu [[T0]],[[T0]],1 1645; MIPS32: andi [[T0]],[[T0]],0xffff 1646; MIPS32: srl [[T5]],[[T5]],0x10 1647; MIPS32: sll [[T5]],[[T5]],0x10 1648; MIPS32: or [[T0]],[[T0]],[[T5]] 1649; MIPS32: srl [[T11:.*]],a1,0x10 1650; MIPS32: andi [[T11]],[[T11]],0x1 1651; MIPS32: srl [[T1]],[[T1]],0x10 1652; MIPS32: andi [[T1]],[[T1]],0x1 1653; MIPS32: sll [[T11]],[[T11]],0x1f 1654; MIPS32: sll [[T1]],[[T1]],0x1f 1655; MIPS32: xor [[T11]],[[T11]],[[T1]] 1656; MIPS32: sltiu [[T11]],[[T11]],1 1657; MIPS32: sll [[T11]],[[T11]],0x10 1658; MIPS32: sll [[T0]],[[T0]],0x10 1659; MIPS32: srl [[T0]],[[T0]],0x10 1660; MIPS32: or [[T11]],[[T11]],[[T0]] 1661; MIPS32: move [[T0]],a2 1662; MIPS32: andi [[T0]],[[T0]],0xffff 1663; MIPS32: andi [[T0]],[[T0]],0x1 1664; MIPS32: move [[T1]],[[T2]] 1665; MIPS32: andi [[T1]],[[T1]],0xffff 1666; MIPS32: andi [[T1]],[[T1]],0x1 1667; MIPS32: sll [[T0]],[[T0]],0x1f 1668; MIPS32: sll [[T1]],[[T1]],0x1f 1669; MIPS32: xor [[T0]],[[T0]],[[T1]] 1670; MIPS32: sltiu [[T0]],[[T0]],1 1671; MIPS32: andi [[T0]],[[T0]],0xffff 1672; MIPS32: srl [[T6]],[[T6]],0x10 1673; MIPS32: sll [[T6]],[[T6]],0x10 1674; MIPS32: or [[T0]],[[T0]],[[T6]] 1675; MIPS32: srl [[T12:.*]],a2,0x10 1676; MIPS32: andi [[T12]],[[T12]],0x1 1677; MIPS32: srl [[T2]],[[T2]],0x10 1678; MIPS32: andi [[T2]],[[T2]],0x1 1679; MIPS32: sll [[T12]],[[T12]],0x1f 1680; MIPS32: sll [[T2]],[[T2]],0x1f 1681; MIPS32: xor [[T12]],[[T12]],[[T2]] 1682; MIPS32: sltiu [[T12]],[[T12]],1 1683; MIPS32: sll [[T12]],[[T12]],0x10 1684; MIPS32: sll [[T0]],[[T0]],0x10 1685; MIPS32: srl [[T0]],[[T0]],0x10 1686; MIPS32: or [[T12]],[[T12]],[[T0]] 1687; MIPS32: move [[T0]],a3 1688; MIPS32: andi [[T0]],[[T0]],0xffff 1689; MIPS32: andi [[T0]],[[T0]],0x1 1690; MIPS32: move [[T1]],[[T3]] 1691; MIPS32: andi [[T1]],[[T1]],0xffff 1692; MIPS32: andi [[T1]],[[T1]],0x1 1693; MIPS32: sll [[T0]],[[T0]],0x1f 1694; MIPS32: sll [[T1]],[[T1]],0x1f 1695; MIPS32: xor [[T0]],[[T0]],[[T1]] 1696; MIPS32: sltiu [[T0]],[[T0]],1 1697; MIPS32: andi [[T0]],[[T0]],0xffff 1698; MIPS32: srl [[T7]],[[T7]],0x10 1699; MIPS32: sll [[T7]],[[T7]],0x10 1700; MIPS32: or [[T0]],[[T0]],[[T7]] 1701; MIPS32: srl [[T13:.*]],a3,0x10 1702; MIPS32: andi [[T13]],[[T13]],0x1 1703; MIPS32: srl [[T3]],[[T3]],0x10 1704; MIPS32: andi [[T3]],[[T3]],0x1 1705; MIPS32: sll [[T13]],[[T13]],0x1f 1706; MIPS32: sll [[T3]],[[T3]],0x1f 1707; MIPS32: xor [[T13]],[[T13]],[[T3]] 1708; MIPS32: sltiu [[T13]],[[T13]],1 1709; MIPS32: sll [[T13]],[[T13]],0x10 1710; MIPS32: sll [[T0]],[[T0]],0x10 1711; MIPS32: srl [[T0]],[[T0]],0x10 1712; MIPS32: or [[T13]],[[T13]],[[T0]] 1713; MIPS32: move v0,[[T10]] 1714; MIPS32: move v1,[[T11]] 1715; MIPS32: move a0,[[T12]] 1716; MIPS32: move a1,[[T13]] 1717} 1718 1719define internal <8 x i1> @test_icmp_v8i1_ne(<8 x i1> %a, <8 x i1> %b) { 1720entry: 1721 %res = icmp ne <8 x i1> %a, %b 1722 ret <8 x i1> %res 1723; CHECK-LABEL: test_icmp_v8i1_ne 1724; CHECK: pcmpeqw 1725; CHECK: pxor 1726 1727; MIPS32-LABEL: test_icmp_v8i1_ne 1728; MIPS32: lw [[T0:.*]], 1729; MIPS32: lw [[T1:.*]], 1730; MIPS32: lw [[T2:.*]], 1731; MIPS32: lw [[T3:.*]], 1732; MIPS32: move [[T4:.*]],zero 1733; MIPS32: move [[T5:.*]],zero 1734; MIPS32: move [[T6:.*]],zero 1735; MIPS32: move [[T7:.*]],zero 1736; MIPS32: move [[T8:.*]],a0 1737; MIPS32: andi [[T8]],[[T8]],0xffff 1738; MIPS32: andi [[T8]],[[T8]],0x1 1739; MIPS32: move [[T9:.*]],[[T0]] 1740; MIPS32: andi [[T9]],[[T9]],0xffff 1741; MIPS32: andi [[T9]],[[T9]],0x1 1742; MIPS32: sll [[T8]],[[T8]],0x1f 1743; MIPS32: sll [[T9]],[[T9]],0x1f 1744; MIPS32: xor [[T8]],[[T8]],[[T9]] 1745; MIPS32: sltu [[T8]],zero,[[T8]] 1746; MIPS32: andi [[T8]],[[T8]],0xffff 1747; MIPS32: srl [[T4]],[[T4]],0x10 1748; MIPS32: sll [[T4]],[[T4]],0x10 1749; MIPS32: or [[T8]],[[T8]],[[T4]] 1750; MIPS32: srl [[T10:.*]],a0,0x10 1751; MIPS32: andi [[T10]],[[T10]],0x1 1752; MIPS32: srl [[T0]],[[T0]],0x10 1753; MIPS32: andi [[T0]],[[T0]],0x1 1754; MIPS32: sll [[T10]],[[T10]],0x1f 1755; MIPS32: sll [[T0]],[[T0]],0x1f 1756; MIPS32: xor [[T10]],[[T10]],[[T0]] 1757; MIPS32: sltu [[T10]],zero,[[T10]] 1758; MIPS32: sll [[T10]],[[T10]],0x10 1759; MIPS32: sll [[T8]],[[T8]],0x10 1760; MIPS32: srl [[T8]],[[T8]],0x10 1761; MIPS32: or [[T10]],[[T10]],[[T8]] 1762; MIPS32: move [[T0]],a1 1763; MIPS32: andi [[T0]],[[T0]],0xffff 1764; MIPS32: andi [[T0]],[[T0]],0x1 1765; MIPS32: move [[T4]],[[T1]] 1766; MIPS32: andi [[T4]],[[T4]],0xffff 1767; MIPS32: andi [[T4]],[[T4]],0x1 1768; MIPS32: sll [[T0]],[[T0]],0x1f 1769; MIPS32: sll [[T4]],[[T4]],0x1f 1770; MIPS32: xor [[T0]],[[T0]],[[T4]] 1771; MIPS32: sltu [[T0]],zero,[[T0]] 1772; MIPS32: andi [[T0]],[[T0]],0xffff 1773; MIPS32: srl [[T5]],[[T5]],0x10 1774; MIPS32: sll [[T5]],[[T5]],0x10 1775; MIPS32: or [[T0]],[[T0]],[[T5]] 1776; MIPS32: srl [[T11:.*]],a1,0x10 1777; MIPS32: andi [[T11]],[[T11]],0x1 1778; MIPS32: srl [[T1]],[[T1]],0x10 1779; MIPS32: andi [[T1]],[[T1]],0x1 1780; MIPS32: sll [[T11]],[[T11]],0x1f 1781; MIPS32: sll [[T1]],[[T1]],0x1f 1782; MIPS32: xor [[T11]],[[T11]],[[T1]] 1783; MIPS32: sltu [[T11]],zero,[[T11]] 1784; MIPS32: sll [[T11]],[[T11]],0x10 1785; MIPS32: sll [[T0]],[[T0]],0x10 1786; MIPS32: srl [[T0]],[[T0]],0x10 1787; MIPS32: or [[T11]],[[T11]],[[T0]] 1788; MIPS32: move [[T0]],a2 1789; MIPS32: andi [[T0]],[[T0]],0xffff 1790; MIPS32: andi [[T0]],[[T0]],0x1 1791; MIPS32: move [[T1]],[[T2]] 1792; MIPS32: andi [[T1]],[[T1]],0xffff 1793; MIPS32: andi [[T1]],[[T1]],0x1 1794; MIPS32: sll [[T0]],[[T0]],0x1f 1795; MIPS32: sll [[T1]],[[T1]],0x1f 1796; MIPS32: xor [[T0]],[[T0]],[[T1]] 1797; MIPS32: sltu [[T0]],zero,[[T0]] 1798; MIPS32: andi [[T0]],[[T0]],0xffff 1799; MIPS32: srl [[T6]],[[T6]],0x10 1800; MIPS32: sll [[T6]],[[T6]],0x10 1801; MIPS32: or [[T0]],[[T0]],[[T6]] 1802; MIPS32: srl [[T12:.*]],a2,0x10 1803; MIPS32: andi [[T12]],[[T12]],0x1 1804; MIPS32: srl [[T2]],[[T2]],0x10 1805; MIPS32: andi [[T2]],[[T2]],0x1 1806; MIPS32: sll [[T12]],[[T12]],0x1f 1807; MIPS32: sll [[T2]],[[T2]],0x1f 1808; MIPS32: xor [[T12]],[[T12]],[[T2]] 1809; MIPS32: sltu [[T12]],zero,[[T12]] 1810; MIPS32: sll [[T12]],[[T12]],0x10 1811; MIPS32: sll [[T0]],[[T0]],0x10 1812; MIPS32: srl [[T0]],[[T0]],0x10 1813; MIPS32: or [[T12]],[[T12]],[[T0]] 1814; MIPS32: move [[T0]],a3 1815; MIPS32: andi [[T0]],[[T0]],0xffff 1816; MIPS32: andi [[T0]],[[T0]],0x1 1817; MIPS32: move [[T1]],[[T3]] 1818; MIPS32: andi [[T1]],[[T1]],0xffff 1819; MIPS32: andi [[T1]],[[T1]],0x1 1820; MIPS32: sll [[T0]],[[T0]],0x1f 1821; MIPS32: sll [[T1]],[[T1]],0x1f 1822; MIPS32: xor [[T0]],[[T0]],[[T1]] 1823; MIPS32: sltu [[T0]],zero,[[T0]] 1824; MIPS32: andi [[T0]],[[T0]],0xffff 1825; MIPS32: srl [[T7]],[[T7]],0x10 1826; MIPS32: sll [[T7]],[[T7]],0x10 1827; MIPS32: or [[T0]],[[T0]],[[T7]] 1828; MIPS32: srl [[T13:.*]],a3,0x10 1829; MIPS32: andi [[T13]],[[T13]],0x1 1830; MIPS32: srl [[T3]],[[T3]],0x10 1831; MIPS32: andi [[T3]],[[T3]],0x1 1832; MIPS32: sll [[T13]],[[T13]],0x1f 1833; MIPS32: sll [[T3]],[[T3]],0x1f 1834; MIPS32: xor [[T13]],[[T13]],[[T3]] 1835; MIPS32: sltu [[T13]],zero,[[T13]] 1836; MIPS32: sll [[T13]],[[T13]],0x10 1837; MIPS32: sll [[T0]],[[T0]],0x10 1838; MIPS32: srl [[T0]],[[T0]],0x10 1839; MIPS32: or [[T13]],[[T13]],[[T0]] 1840; MIPS32: move v0,[[T10]] 1841; MIPS32: move v1,[[T11]] 1842; MIPS32: move a0,[[T12]] 1843; MIPS32: move a1,[[T13]] 1844} 1845 1846define internal <8 x i1> @test_icmp_v8i1_sgt(<8 x i1> %a, <8 x i1> %b) { 1847entry: 1848 %res = icmp sgt <8 x i1> %a, %b 1849 ret <8 x i1> %res 1850; CHECK-LABEL: test_icmp_v8i1_sgt 1851; CHECK: pcmpgtw 1852 1853; MIPS32-LABEL: test_icmp_v8i1_sgt 1854; MIPS32: lw [[T0:.*]], 1855; MIPS32: lw [[T1:.*]], 1856; MIPS32: lw [[T2:.*]], 1857; MIPS32: lw [[T3:.*]], 1858; MIPS32: move [[T4:.*]],zero 1859; MIPS32: move [[T5:.*]],zero 1860; MIPS32: move [[T6:.*]],zero 1861; MIPS32: move [[T7:.*]],zero 1862; MIPS32: move [[T8:.*]],a0 1863; MIPS32: andi [[T8]],[[T8]],0xffff 1864; MIPS32: andi [[T8]],[[T8]],0x1 1865; MIPS32: move [[T9:.*]],[[T0]] 1866; MIPS32: andi [[T9]],[[T9]],0xffff 1867; MIPS32: andi [[T9]],[[T9]],0x1 1868; MIPS32: sll [[T8]],[[T8]],0x1f 1869; MIPS32: sll [[T9]],[[T9]],0x1f 1870; MIPS32: slt [[T9]],[[T9]],[[T8]] 1871; MIPS32: andi [[T9]],[[T9]],0xffff 1872; MIPS32: srl [[T4]],[[T4]],0x10 1873; MIPS32: sll [[T4]],[[T4]],0x10 1874; MIPS32: or [[T9]],[[T9]],[[T4]] 1875; MIPS32: srl [[T10:.*]],a0,0x10 1876; MIPS32: andi [[T10]],[[T10]],0x1 1877; MIPS32: srl [[T0]],[[T0]],0x10 1878; MIPS32: andi [[T0]],[[T0]],0x1 1879; MIPS32: sll [[T10]],[[T10]],0x1f 1880; MIPS32: sll [[T0]],[[T0]],0x1f 1881; MIPS32: slt [[T0]],[[T0]],[[T10]] 1882; MIPS32: sll [[T0]],[[T0]],0x10 1883; MIPS32: sll [[T9]],[[T9]],0x10 1884; MIPS32: srl [[T9]],[[T9]],0x10 1885; MIPS32: or v0,[[T0]],[[T9]] 1886; MIPS32: move [[T10]],a1 1887; MIPS32: andi [[T10]],[[T10]],0xffff 1888; MIPS32: andi [[T10]],[[T10]],0x1 1889; MIPS32: move [[T4]],[[T1]] 1890; MIPS32: andi [[T4]],[[T4]],0xffff 1891; MIPS32: andi [[T4]],[[T4]],0x1 1892; MIPS32: sll [[T10]],[[T10]],0x1f 1893; MIPS32: sll [[T4]],[[T4]],0x1f 1894; MIPS32: slt [[T4]],[[T4]],[[T10]] 1895; MIPS32: andi [[T4]],[[T4]],0xffff 1896; MIPS32: srl [[T5]],[[T5]],0x10 1897; MIPS32: sll [[T5]],[[T5]],0x10 1898; MIPS32: or [[T4]],[[T4]],[[T5]] 1899; MIPS32: srl [[T11:.*]],a1,0x10 1900; MIPS32: andi [[T11]],[[T11]],0x1 1901; MIPS32: srl [[T1]],[[T1]],0x10 1902; MIPS32: andi [[T1]],[[T1]],0x1 1903; MIPS32: sll [[T11]],[[T11]],0x1f 1904; MIPS32: sll [[T1]],[[T1]],0x1f 1905; MIPS32: slt [[T1]],[[T1]],[[T11]] 1906; MIPS32: sll [[T1]],[[T1]],0x10 1907; MIPS32: sll [[T4]],[[T4]],0x10 1908; MIPS32: srl [[T4]],[[T4]],0x10 1909; MIPS32: or v1,[[T1]],[[T4]] 1910; MIPS32: move [[T10]],a2 1911; MIPS32: andi [[T10]],[[T10]],0xffff 1912; MIPS32: andi [[T10]],[[T10]],0x1 1913; MIPS32: move [[T11]],[[T2]] 1914; MIPS32: andi [[T11]],[[T11]],0xffff 1915; MIPS32: andi [[T11]],[[T11]],0x1 1916; MIPS32: sll [[T10]],[[T10]],0x1f 1917; MIPS32: sll [[T11]],[[T11]],0x1f 1918; MIPS32: slt [[T11]],[[T11]],[[T10]] 1919; MIPS32: andi [[T11]],[[T11]],0xffff 1920; MIPS32: srl [[T6]],[[T6]],0x10 1921; MIPS32: sll [[T6]],[[T6]],0x10 1922; MIPS32: or [[T11]],[[T11]],[[T6]] 1923; MIPS32: srl [[T12:.*]],a2,0x10 1924; MIPS32: andi [[T12]],[[T12]],0x1 1925; MIPS32: srl [[T2]],[[T2]],0x10 1926; MIPS32: andi [[T2]],[[T2]],0x1 1927; MIPS32: sll [[T12]],[[T12]],0x1f 1928; MIPS32: sll [[T2]],[[T2]],0x1f 1929; MIPS32: slt [[T2]],[[T2]],[[T12]] 1930; MIPS32: sll [[T2]],[[T2]],0x10 1931; MIPS32: sll [[T11]],[[T11]],0x10 1932; MIPS32: srl [[T11]],[[T11]],0x10 1933; MIPS32: or [[T2]],[[T2]],[[T11]] 1934; MIPS32: move [[T10]],a3 1935; MIPS32: andi [[T10]],[[T10]],0xffff 1936; MIPS32: andi [[T10]],[[T10]],0x1 1937; MIPS32: move [[T11]],[[T3]] 1938; MIPS32: andi [[T11]],[[T11]],0xffff 1939; MIPS32: andi [[T11]],[[T11]],0x1 1940; MIPS32: sll [[T10]],[[T10]],0x1f 1941; MIPS32: sll [[T11]],[[T11]],0x1f 1942; MIPS32: slt [[T11]],[[T11]],[[T10]] 1943; MIPS32: andi [[T11]],[[T11]],0xffff 1944; MIPS32: srl [[T7]],[[T7]],0x10 1945; MIPS32: sll [[T7]],[[T7]],0x10 1946; MIPS32: or [[T11]],[[T11]],[[T7]] 1947; MIPS32: srl [[T13:.*]],a3,0x10 1948; MIPS32: andi [[T13]],[[T13]],0x1 1949; MIPS32: srl [[T3]],[[T3]],0x10 1950; MIPS32: andi [[T3]],[[T3]],0x1 1951; MIPS32: sll [[T13]],[[T13]],0x1f 1952; MIPS32: sll [[T3]],[[T3]],0x1f 1953; MIPS32: slt [[T3]],[[T3]],[[T13]] 1954; MIPS32: sll [[T3]],[[T3]],0x10 1955; MIPS32: sll [[T11]],[[T11]],0x10 1956; MIPS32: srl [[T11]],[[T11]],0x10 1957; MIPS32: or [[T3]],[[T3]],[[T11]] 1958; MIPS32: move a0,[[T2]] 1959; MIPS32: move a1,[[T3]] 1960} 1961 1962define internal <8 x i1> @test_icmp_v8i1_sle(<8 x i1> %a, <8 x i1> %b) { 1963entry: 1964 %res = icmp sle <8 x i1> %a, %b 1965 ret <8 x i1> %res 1966; CHECK-LABEL: test_icmp_v8i1_sle 1967; CHECK: pcmpgtw 1968; CHECK: pxor 1969 1970; MIPS32-LABEL: test_icmp_v8i1_sle 1971; MIPS32: lw [[T0:.*]], 1972; MIPS32: lw [[T1:.*]], 1973; MIPS32: lw [[T2:.*]], 1974; MIPS32: lw [[T3:.*]], 1975; MIPS32: move [[T4:.*]],zero 1976; MIPS32: move [[T5:.*]],zero 1977; MIPS32: move [[T6:.*]],zero 1978; MIPS32: move [[T7:.*]],zero 1979; MIPS32: move [[T8:.*]],a0 1980; MIPS32: andi [[T8]],[[T8]],0xffff 1981; MIPS32: andi [[T8]],[[T8]],0x1 1982; MIPS32: move [[T9:.*]],[[T0]] 1983; MIPS32: andi [[T9]],[[T9]],0xffff 1984; MIPS32: andi [[T9]],[[T9]],0x1 1985; MIPS32: sll [[T8]],[[T8]],0x1f 1986; MIPS32: sll [[T9]],[[T9]],0x1f 1987; MIPS32: slt [[T9]],[[T9]],[[T8]] 1988; MIPS32: xori [[T9]],[[T9]],0x1 1989; MIPS32: andi [[T9]],[[T9]],0xffff 1990; MIPS32: srl [[T4]],[[T4]],0x10 1991; MIPS32: sll [[T4]],[[T4]],0x10 1992; MIPS32: or [[T9]],[[T9]],[[T4]] 1993; MIPS32: srl [[T10:.*]],a0,0x10 1994; MIPS32: andi [[T10]],[[T10]],0x1 1995; MIPS32: srl [[T0]],[[T0]],0x10 1996; MIPS32: andi [[T0]],[[T0]],0x1 1997; MIPS32: sll [[T10]],[[T10]],0x1f 1998; MIPS32: sll [[T0]],[[T0]],0x1f 1999; MIPS32: slt [[T0]],[[T0]],[[T10]] 2000; MIPS32: xori [[T0]],[[T0]],0x1 2001; MIPS32: sll [[T0]],[[T0]],0x10 2002; MIPS32: sll [[T9]],[[T9]],0x10 2003; MIPS32: srl [[T9]],[[T9]],0x10 2004; MIPS32: or v0,[[T0]],[[T9]] 2005; MIPS32: move [[T10]],a1 2006; MIPS32: andi [[T10]],[[T10]],0xffff 2007; MIPS32: andi [[T10]],[[T10]],0x1 2008; MIPS32: move [[T4]],[[T1]] 2009; MIPS32: andi [[T4]],[[T4]],0xffff 2010; MIPS32: andi [[T4]],[[T4]],0x1 2011; MIPS32: sll [[T10]],[[T10]],0x1f 2012; MIPS32: sll [[T4]],[[T4]],0x1f 2013; MIPS32: slt [[T4]],[[T4]],[[T10]] 2014; MIPS32: xori [[T4]],[[T4]],0x1 2015; MIPS32: andi [[T4]],[[T4]],0xffff 2016; MIPS32: srl [[T5]],[[T5]],0x10 2017; MIPS32: sll [[T5]],[[T5]],0x10 2018; MIPS32: or [[T4]],[[T4]],[[T5]] 2019; MIPS32: srl [[T11:.*]],a1,0x10 2020; MIPS32: andi [[T11]],[[T11]],0x1 2021; MIPS32: srl [[T1]],[[T1]],0x10 2022; MIPS32: andi [[T1]],[[T1]],0x1 2023; MIPS32: sll [[T11]],[[T11]],0x1f 2024; MIPS32: sll [[T1]],[[T1]],0x1f 2025; MIPS32: slt [[T1]],[[T1]],[[T11]] 2026; MIPS32: xori [[T1]],[[T1]],0x1 2027; MIPS32: sll [[T1]],[[T1]],0x10 2028; MIPS32: sll [[T4]],[[T4]],0x10 2029; MIPS32: srl [[T4]],[[T4]],0x10 2030; MIPS32: or v1,[[T1]],[[T4]] 2031; MIPS32: move [[T10]],a2 2032; MIPS32: andi [[T10]],[[T10]],0xffff 2033; MIPS32: andi [[T10]],[[T10]],0x1 2034; MIPS32: move [[T11]],[[T2]] 2035; MIPS32: andi [[T11]],[[T11]],0xffff 2036; MIPS32: andi [[T11]],[[T11]],0x1 2037; MIPS32: sll [[T10]],[[T10]],0x1f 2038; MIPS32: sll [[T11]],[[T11]],0x1f 2039; MIPS32: slt [[T11]],[[T11]],[[T10]] 2040; MIPS32: xori [[T11]],[[T11]],0x1 2041; MIPS32: andi [[T11]],[[T11]],0xffff 2042; MIPS32: srl [[T6]],[[T6]],0x10 2043; MIPS32: sll [[T6]],[[T6]],0x10 2044; MIPS32: or [[T11]],[[T11]],[[T6]] 2045; MIPS32: srl [[T12:.*]],a2,0x10 2046; MIPS32: andi [[T12]],[[T12]],0x1 2047; MIPS32: srl [[T2]],[[T2]],0x10 2048; MIPS32: andi [[T2]],[[T2]],0x1 2049; MIPS32: sll [[T12]],[[T12]],0x1f 2050; MIPS32: sll [[T2]],[[T2]],0x1f 2051; MIPS32: slt [[T2]],[[T2]],[[T12]] 2052; MIPS32: xori [[T2]],[[T2]],0x1 2053; MIPS32: sll [[T2]],[[T2]],0x10 2054; MIPS32: sll [[T11]],[[T11]],0x10 2055; MIPS32: srl [[T11]],[[T11]],0x10 2056; MIPS32: or [[T2]],[[T2]],[[T11]] 2057; MIPS32: move [[T10]],a3 2058; MIPS32: andi [[T10]],[[T10]],0xffff 2059; MIPS32: andi [[T10]],[[T10]],0x1 2060; MIPS32: move [[T11]],[[T3]] 2061; MIPS32: andi [[T11]],[[T11]],0xffff 2062; MIPS32: andi [[T11]],[[T11]],0x1 2063; MIPS32: sll [[T10]],[[T10]],0x1f 2064; MIPS32: sll [[T11]],[[T11]],0x1f 2065; MIPS32: slt [[T11]],[[T11]],[[T10]] 2066; MIPS32: xori [[T11]],[[T11]],0x1 2067; MIPS32: andi [[T11]],[[T11]],0xffff 2068; MIPS32: srl [[T7]],[[T7]],0x10 2069; MIPS32: sll [[T7]],[[T7]],0x10 2070; MIPS32: or [[T11]],[[T11]],[[T7]] 2071; MIPS32: srl [[T13:.*]],a3,0x10 2072; MIPS32: andi [[T13]],[[T13]],0x1 2073; MIPS32: srl [[T3]],[[T3]],0x10 2074; MIPS32: andi [[T3]],[[T3]],0x1 2075; MIPS32: sll [[T13]],[[T13]],0x1f 2076; MIPS32: sll [[T3]],[[T3]],0x1f 2077; MIPS32: slt [[T3]],[[T3]],[[T13]] 2078; MIPS32: xori [[T3]],[[T3]],0x1 2079; MIPS32: sll [[T3]],[[T3]],0x10 2080; MIPS32: sll [[T11]],[[T11]],0x10 2081; MIPS32: srl [[T11]],[[T11]],0x10 2082; MIPS32: or [[T3]],[[T3]],[[T11]] 2083; MIPS32: move a0,[[T2]] 2084; MIPS32: move a1,[[T3]] 2085} 2086 2087define internal <8 x i1> @test_icmp_v8i1_slt(<8 x i1> %a, <8 x i1> %b) { 2088entry: 2089 %res = icmp slt <8 x i1> %a, %b 2090 ret <8 x i1> %res 2091; CHECK-LABEL: test_icmp_v8i1_slt 2092; CHECK: pcmpgtw 2093 2094; MIPS32-LABEL: test_icmp_v8i1_slt 2095; MIPS32: lw [[T0:.*]], 2096; MIPS32: lw [[T1:.*]], 2097; MIPS32: lw [[T2:.*]], 2098; MIPS32: lw [[T3:.*]], 2099; MIPS32: move [[T4:.*]],zero 2100; MIPS32: move [[T5:.*]],zero 2101; MIPS32: move [[T6:.*]],zero 2102; MIPS32: move [[T7:.*]],zero 2103; MIPS32: move [[T8:.*]],a0 2104; MIPS32: andi [[T8]],[[T8]],0xffff 2105; MIPS32: andi [[T8]],[[T8]],0x1 2106; MIPS32: move [[T9:.*]],[[T0]] 2107; MIPS32: andi [[T9]],[[T9]],0xffff 2108; MIPS32: andi [[T9]],[[T9]],0x1 2109; MIPS32: sll [[T8]],[[T8]],0x1f 2110; MIPS32: sll [[T9]],[[T9]],0x1f 2111; MIPS32: slt [[T8]],[[T8]],[[T9]] 2112; MIPS32: andi [[T8]],[[T8]],0xffff 2113; MIPS32: srl [[T4]],[[T4]],0x10 2114; MIPS32: sll [[T4]],[[T4]],0x10 2115; MIPS32: or [[T8]],[[T8]],[[T4]] 2116; MIPS32: srl [[T10:.*]],a0,0x10 2117; MIPS32: andi [[T10]],[[T10]],0x1 2118; MIPS32: srl [[T0]],[[T0]],0x10 2119; MIPS32: andi [[T0]],[[T0]],0x1 2120; MIPS32: sll [[T10]],[[T10]],0x1f 2121; MIPS32: sll [[T0]],[[T0]],0x1f 2122; MIPS32: slt [[T10]],[[T10]],[[T0]] 2123; MIPS32: sll [[T10]],[[T10]],0x10 2124; MIPS32: sll [[T8]],[[T8]],0x10 2125; MIPS32: srl [[T8]],[[T8]],0x10 2126; MIPS32: or [[T10]],[[T10]],[[T8]] 2127; MIPS32: move [[T0]],a1 2128; MIPS32: andi [[T0]],[[T0]],0xffff 2129; MIPS32: andi [[T0]],[[T0]],0x1 2130; MIPS32: move [[T4]],[[T1]] 2131; MIPS32: andi [[T4]],[[T4]],0xffff 2132; MIPS32: andi [[T4]],[[T4]],0x1 2133; MIPS32: sll [[T0]],[[T0]],0x1f 2134; MIPS32: sll [[T4]],[[T4]],0x1f 2135; MIPS32: slt [[T0]],[[T0]],[[T4]] 2136; MIPS32: andi [[T0]],[[T0]],0xffff 2137; MIPS32: srl [[T5]],[[T5]],0x10 2138; MIPS32: sll [[T5]],[[T5]],0x10 2139; MIPS32: or [[T0]],[[T0]],[[T5]] 2140; MIPS32: srl [[T11:.*]],a1,0x10 2141; MIPS32: andi [[T11]],[[T11]],0x1 2142; MIPS32: srl [[T1]],[[T1]],0x10 2143; MIPS32: andi [[T1]],[[T1]],0x1 2144; MIPS32: sll [[T11]],[[T11]],0x1f 2145; MIPS32: sll [[T1]],[[T1]],0x1f 2146; MIPS32: slt [[T11]],[[T11]],[[T1]] 2147; MIPS32: sll [[T11]],[[T11]],0x10 2148; MIPS32: sll [[T0]],[[T0]],0x10 2149; MIPS32: srl [[T0]],[[T0]],0x10 2150; MIPS32: or [[T11]],[[T11]],[[T0]] 2151; MIPS32: move [[T0]],a2 2152; MIPS32: andi [[T0]],[[T0]],0xffff 2153; MIPS32: andi [[T0]],[[T0]],0x1 2154; MIPS32: move [[T1]],[[T2]] 2155; MIPS32: andi [[T1]],[[T1]],0xffff 2156; MIPS32: andi [[T1]],[[T1]],0x1 2157; MIPS32: sll [[T0]],[[T0]],0x1f 2158; MIPS32: sll [[T1]],[[T1]],0x1f 2159; MIPS32: slt [[T0]],[[T0]],[[T1]] 2160; MIPS32: andi [[T0]],[[T0]],0xffff 2161; MIPS32: srl [[T6]],[[T6]],0x10 2162; MIPS32: sll [[T6]],[[T6]],0x10 2163; MIPS32: or [[T0]],[[T0]],[[T6]] 2164; MIPS32: srl [[T12:.*]],a2,0x10 2165; MIPS32: andi [[T12]],[[T12]],0x1 2166; MIPS32: srl [[T2]],[[T2]],0x10 2167; MIPS32: andi [[T2]],[[T2]],0x1 2168; MIPS32: sll [[T12]],[[T12]],0x1f 2169; MIPS32: sll [[T2]],[[T2]],0x1f 2170; MIPS32: slt [[T12]],[[T12]],[[T2]] 2171; MIPS32: sll [[T12]],[[T12]],0x10 2172; MIPS32: sll [[T0]],[[T0]],0x10 2173; MIPS32: srl [[T0]],[[T0]],0x10 2174; MIPS32: or [[T12]],[[T12]],[[T0]] 2175; MIPS32: move [[T0]],a3 2176; MIPS32: andi [[T0]],[[T0]],0xffff 2177; MIPS32: andi [[T0]],[[T0]],0x1 2178; MIPS32: move [[T1]],[[T3]] 2179; MIPS32: andi [[T1]],[[T1]],0xffff 2180; MIPS32: andi [[T1]],[[T1]],0x1 2181; MIPS32: sll [[T0]],[[T0]],0x1f 2182; MIPS32: sll [[T1]],[[T1]],0x1f 2183; MIPS32: slt [[T0]],[[T0]],[[T1]] 2184; MIPS32: andi [[T0]],[[T0]],0xffff 2185; MIPS32: srl [[T7]],[[T7]],0x10 2186; MIPS32: sll [[T7]],[[T7]],0x10 2187; MIPS32: or [[T0]],[[T0]],[[T7]] 2188; MIPS32: srl [[T13:.*]],a3,0x10 2189; MIPS32: andi [[T13]],[[T13]],0x1 2190; MIPS32: srl [[T3]],[[T3]],0x10 2191; MIPS32: andi [[T3]],[[T3]],0x1 2192; MIPS32: sll [[T13]],[[T13]],0x1f 2193; MIPS32: sll [[T3]],[[T3]],0x1f 2194; MIPS32: slt [[T13]],[[T13]],[[T3]] 2195; MIPS32: sll [[T13]],[[T13]],0x10 2196; MIPS32: sll [[T0]],[[T0]],0x10 2197; MIPS32: srl [[T0]],[[T0]],0x10 2198; MIPS32: or [[T13]],[[T13]],[[T0]] 2199; MIPS32: move v0,[[T10]] 2200; MIPS32: move v1,[[T11]] 2201; MIPS32: move a0,[[T12]] 2202; MIPS32: move a1,[[T13]] 2203} 2204 2205define internal <8 x i1> @test_icmp_v8i1_uge(<8 x i1> %a, <8 x i1> %b) { 2206entry: 2207 %res = icmp uge <8 x i1> %a, %b 2208 ret <8 x i1> %res 2209; CHECK-LABEL: test_icmp_v8i1_uge 2210; CHECK: pxor 2211; CHECK: pcmpgtw 2212; CHECK: pxor 2213 2214; MIPS32-LABEL: test_icmp_v8i1_uge 2215; MIPS32: lw [[T0:.*]], 2216; MIPS32: lw [[T1:.*]], 2217; MIPS32: lw [[T2:.*]], 2218; MIPS32: lw [[T3:.*]], 2219; MIPS32: move [[T4:.*]],zero 2220; MIPS32: move [[T5:.*]],zero 2221; MIPS32: move [[T6:.*]],zero 2222; MIPS32: move [[T7:.*]],zero 2223; MIPS32: move [[T8:.*]],a0 2224; MIPS32: andi [[T8]],[[T8]],0xffff 2225; MIPS32: andi [[T8]],[[T8]],0x1 2226; MIPS32: move [[T9:.*]],[[T0]] 2227; MIPS32: andi [[T9]],[[T9]],0xffff 2228; MIPS32: andi [[T9]],[[T9]],0x1 2229; MIPS32: sll [[T8]],[[T8]],0x1f 2230; MIPS32: sll [[T9]],[[T9]],0x1f 2231; MIPS32: sltu [[T8]],[[T8]],[[T9]] 2232; MIPS32: xori [[T8]],[[T8]],0x1 2233; MIPS32: andi [[T8]],[[T8]],0xffff 2234; MIPS32: srl [[T4]],[[T4]],0x10 2235; MIPS32: sll [[T4]],[[T4]],0x10 2236; MIPS32: or [[T8]],[[T8]],[[T4]] 2237; MIPS32: srl [[T10:.*]],a0,0x10 2238; MIPS32: andi [[T10]],[[T10]],0x1 2239; MIPS32: srl [[T0]],[[T0]],0x10 2240; MIPS32: andi [[T0]],[[T0]],0x1 2241; MIPS32: sll [[T10]],[[T10]],0x1f 2242; MIPS32: sll [[T0]],[[T0]],0x1f 2243; MIPS32: sltu [[T10]],[[T10]],[[T0]] 2244; MIPS32: xori [[T10]],[[T10]],0x1 2245; MIPS32: sll [[T10]],[[T10]],0x10 2246; MIPS32: sll [[T8]],[[T8]],0x10 2247; MIPS32: srl [[T8]],[[T8]],0x10 2248; MIPS32: or [[T10]],[[T10]],[[T8]] 2249; MIPS32: move [[T0]],a1 2250; MIPS32: andi [[T0]],[[T0]],0xffff 2251; MIPS32: andi [[T0]],[[T0]],0x1 2252; MIPS32: move [[T4]],[[T1]] 2253; MIPS32: andi [[T4]],[[T4]],0xffff 2254; MIPS32: andi [[T4]],[[T4]],0x1 2255; MIPS32: sll [[T0]],[[T0]],0x1f 2256; MIPS32: sll [[T4]],[[T4]],0x1f 2257; MIPS32: sltu [[T0]],[[T0]],[[T4]] 2258; MIPS32: xori [[T0]],[[T0]],0x1 2259; MIPS32: andi [[T0]],[[T0]],0xffff 2260; MIPS32: srl [[T5]],[[T5]],0x10 2261; MIPS32: sll [[T5]],[[T5]],0x10 2262; MIPS32: or [[T0]],[[T0]],[[T5]] 2263; MIPS32: srl [[T11:.*]],a1,0x10 2264; MIPS32: andi [[T11]],[[T11]],0x1 2265; MIPS32: srl [[T1]],[[T1]],0x10 2266; MIPS32: andi [[T1]],[[T1]],0x1 2267; MIPS32: sll [[T11]],[[T11]],0x1f 2268; MIPS32: sll [[T1]],[[T1]],0x1f 2269; MIPS32: sltu [[T11]],[[T11]],[[T1]] 2270; MIPS32: xori [[T11]],[[T11]],0x1 2271; MIPS32: sll [[T11]],[[T11]],0x10 2272; MIPS32: sll [[T0]],[[T0]],0x10 2273; MIPS32: srl [[T0]],[[T0]],0x10 2274; MIPS32: or [[T11]],[[T11]],[[T0]] 2275; MIPS32: move [[T0]],a2 2276; MIPS32: andi [[T0]],[[T0]],0xffff 2277; MIPS32: andi [[T0]],[[T0]],0x1 2278; MIPS32: move [[T1]],[[T2]] 2279; MIPS32: andi [[T1]],[[T1]],0xffff 2280; MIPS32: andi [[T1]],[[T1]],0x1 2281; MIPS32: sll [[T0]],[[T0]],0x1f 2282; MIPS32: sll [[T1]],[[T1]],0x1f 2283; MIPS32: sltu [[T0]],[[T0]],[[T1]] 2284; MIPS32: xori [[T0]],[[T0]],0x1 2285; MIPS32: andi [[T0]],[[T0]],0xffff 2286; MIPS32: srl [[T6]],[[T6]],0x10 2287; MIPS32: sll [[T6]],[[T6]],0x10 2288; MIPS32: or [[T0]],[[T0]],[[T6]] 2289; MIPS32: srl [[T12:.*]],a2,0x10 2290; MIPS32: andi [[T12]],[[T12]],0x1 2291; MIPS32: srl [[T2]],[[T2]],0x10 2292; MIPS32: andi [[T2]],[[T2]],0x1 2293; MIPS32: sll [[T12]],[[T12]],0x1f 2294; MIPS32: sll [[T2]],[[T2]],0x1f 2295; MIPS32: sltu [[T12]],[[T12]],[[T2]] 2296; MIPS32: xori [[T12]],[[T12]],0x1 2297; MIPS32: sll [[T12]],[[T12]],0x10 2298; MIPS32: sll [[T0]],[[T0]],0x10 2299; MIPS32: srl [[T0]],[[T0]],0x10 2300; MIPS32: or [[T12]],[[T12]],[[T0]] 2301; MIPS32: move [[T0]],a3 2302; MIPS32: andi [[T0]],[[T0]],0xffff 2303; MIPS32: andi [[T0]],[[T0]],0x1 2304; MIPS32: move [[T1]],[[T3]] 2305; MIPS32: andi [[T1]],[[T1]],0xffff 2306; MIPS32: andi [[T1]],[[T1]],0x1 2307; MIPS32: sll [[T0]],[[T0]],0x1f 2308; MIPS32: sll [[T1]],[[T1]],0x1f 2309; MIPS32: sltu [[T0]],[[T0]],[[T1]] 2310; MIPS32: xori [[T0]],[[T0]],0x1 2311; MIPS32: andi [[T0]],[[T0]],0xffff 2312; MIPS32: srl [[T7]],[[T7]],0x10 2313; MIPS32: sll [[T7]],[[T7]],0x10 2314; MIPS32: or [[T0]],[[T0]],[[T7]] 2315; MIPS32: srl [[T13:.*]],a3,0x10 2316; MIPS32: andi [[T13]],[[T13]],0x1 2317; MIPS32: srl [[T3]],[[T3]],0x10 2318; MIPS32: andi [[T3]],[[T3]],0x1 2319; MIPS32: sll [[T13]],[[T13]],0x1f 2320; MIPS32: sll [[T3]],[[T3]],0x1f 2321; MIPS32: sltu [[T13]],[[T13]],[[T3]] 2322; MIPS32: xori [[T13]],[[T13]],0x1 2323; MIPS32: sll [[T13]],[[T13]],0x10 2324; MIPS32: sll [[T0]],[[T0]],0x10 2325; MIPS32: srl [[T0]],[[T0]],0x10 2326; MIPS32: or [[T13]],[[T13]],[[T0]] 2327; MIPS32: move v0,[[T10]] 2328; MIPS32: move v1,[[T11]] 2329; MIPS32: move a0,[[T12]] 2330; MIPS32: move a1,[[T13]] 2331} 2332 2333define internal <8 x i1> @test_icmp_v8i1_ugt(<8 x i1> %a, <8 x i1> %b) { 2334entry: 2335 %res = icmp ugt <8 x i1> %a, %b 2336 ret <8 x i1> %res 2337; CHECK-LABEL: test_icmp_v8i1_ugt 2338; CHECK: pxor 2339; CHECK: pcmpgtw 2340 2341; MIPS32-LABEL: test_icmp_v8i1_ugt 2342; MIPS32: lw [[T0:.*]], 2343; MIPS32: lw [[T1:.*]], 2344; MIPS32: lw [[T2:.*]], 2345; MIPS32: lw [[T3:.*]], 2346; MIPS32: move [[T4:.*]],zero 2347; MIPS32: move [[T5:.*]],zero 2348; MIPS32: move [[T6:.*]],zero 2349; MIPS32: move [[T7:.*]],zero 2350; MIPS32: move [[T8:.*]],a0 2351; MIPS32: andi [[T8]],[[T8]],0xffff 2352; MIPS32: andi [[T8]],[[T8]],0x1 2353; MIPS32: move [[T9:.*]],[[T0]] 2354; MIPS32: andi [[T9]],[[T9]],0xffff 2355; MIPS32: andi [[T9]],[[T9]],0x1 2356; MIPS32: sll [[T8]],[[T8]],0x1f 2357; MIPS32: sll [[T9]],[[T9]],0x1f 2358; MIPS32: sltu [[T9]],[[T9]],[[T8]] 2359; MIPS32: andi [[T9]],[[T9]],0xffff 2360; MIPS32: srl [[T4]],[[T4]],0x10 2361; MIPS32: sll [[T4]],[[T4]],0x10 2362; MIPS32: or [[T9]],[[T9]],[[T4]] 2363; MIPS32: srl [[T10:.*]],a0,0x10 2364; MIPS32: andi [[T10]],[[T10]],0x1 2365; MIPS32: srl [[T0]],[[T0]],0x10 2366; MIPS32: andi [[T0]],[[T0]],0x1 2367; MIPS32: sll [[T10]],[[T10]],0x1f 2368; MIPS32: sll [[T0]],[[T0]],0x1f 2369; MIPS32: sltu [[T0]],[[T0]],[[T10]] 2370; MIPS32: sll [[T0]],[[T0]],0x10 2371; MIPS32: sll [[T9]],[[T9]],0x10 2372; MIPS32: srl [[T9]],[[T9]],0x10 2373; MIPS32: or v0,[[T0]],[[T9]] 2374; MIPS32: move [[T10]],a1 2375; MIPS32: andi [[T10]],[[T10]],0xffff 2376; MIPS32: andi [[T10]],[[T10]],0x1 2377; MIPS32: move [[T4]],[[T1]] 2378; MIPS32: andi [[T4]],[[T4]],0xffff 2379; MIPS32: andi [[T4]],[[T4]],0x1 2380; MIPS32: sll [[T10]],[[T10]],0x1f 2381; MIPS32: sll [[T4]],[[T4]],0x1f 2382; MIPS32: sltu [[T4]],[[T4]],[[T10]] 2383; MIPS32: andi [[T4]],[[T4]],0xffff 2384; MIPS32: srl [[T5]],[[T5]],0x10 2385; MIPS32: sll [[T5]],[[T5]],0x10 2386; MIPS32: or [[T4]],[[T4]],[[T5]] 2387; MIPS32: srl [[T11:.*]],a1,0x10 2388; MIPS32: andi [[T11]],[[T11]],0x1 2389; MIPS32: srl [[T1]],[[T1]],0x10 2390; MIPS32: andi [[T1]],[[T1]],0x1 2391; MIPS32: sll [[T11]],[[T11]],0x1f 2392; MIPS32: sll [[T1]],[[T1]],0x1f 2393; MIPS32: sltu [[T1]],[[T1]],[[T11]] 2394; MIPS32: sll [[T1]],[[T1]],0x10 2395; MIPS32: sll [[T4]],[[T4]],0x10 2396; MIPS32: srl [[T4]],[[T4]],0x10 2397; MIPS32: or v1,[[T1]],[[T4]] 2398; MIPS32: move [[T10]],a2 2399; MIPS32: andi [[T10]],[[T10]],0xffff 2400; MIPS32: andi [[T10]],[[T10]],0x1 2401; MIPS32: move [[T11]],[[T2]] 2402; MIPS32: andi [[T11]],[[T11]],0xffff 2403; MIPS32: andi [[T11]],[[T11]],0x1 2404; MIPS32: sll [[T10]],[[T10]],0x1f 2405; MIPS32: sll [[T11]],[[T11]],0x1f 2406; MIPS32: sltu [[T11]],[[T11]],[[T10]] 2407; MIPS32: andi [[T11]],[[T11]],0xffff 2408; MIPS32: srl [[T6]],[[T6]],0x10 2409; MIPS32: sll [[T6]],[[T6]],0x10 2410; MIPS32: or [[T11]],[[T11]],[[T6]] 2411; MIPS32: srl [[T12:.*]],a2,0x10 2412; MIPS32: andi [[T12]],[[T12]],0x1 2413; MIPS32: srl [[T2]],[[T2]],0x10 2414; MIPS32: andi [[T2]],[[T2]],0x1 2415; MIPS32: sll [[T12]],[[T12]],0x1f 2416; MIPS32: sll [[T2]],[[T2]],0x1f 2417; MIPS32: sltu [[T2]],[[T2]],[[T12]] 2418; MIPS32: sll [[T2]],[[T2]],0x10 2419; MIPS32: sll [[T11]],[[T11]],0x10 2420; MIPS32: srl [[T11]],[[T11]],0x10 2421; MIPS32: or [[T2]],[[T2]],[[T11]] 2422; MIPS32: move [[T10]],a3 2423; MIPS32: andi [[T10]],[[T10]],0xffff 2424; MIPS32: andi [[T10]],[[T10]],0x1 2425; MIPS32: move [[T11]],[[T3]] 2426; MIPS32: andi [[T11]],[[T11]],0xffff 2427; MIPS32: andi [[T11]],[[T11]],0x1 2428; MIPS32: sll [[T10]],[[T10]],0x1f 2429; MIPS32: sll [[T11]],[[T11]],0x1f 2430; MIPS32: sltu [[T11]],[[T11]],[[T10]] 2431; MIPS32: andi [[T11]],[[T11]],0xffff 2432; MIPS32: srl [[T7]],[[T7]],0x10 2433; MIPS32: sll [[T7]],[[T7]],0x10 2434; MIPS32: or [[T11]],[[T11]],[[T7]] 2435; MIPS32: srl [[T13:.*]],a3,0x10 2436; MIPS32: andi [[T13]],[[T13]],0x1 2437; MIPS32: srl [[T3]],[[T3]],0x10 2438; MIPS32: andi [[T3]],[[T3]],0x1 2439; MIPS32: sll [[T13]],[[T13]],0x1f 2440; MIPS32: sll [[T3]],[[T3]],0x1f 2441; MIPS32: sltu [[T3]],[[T3]],[[T13]] 2442; MIPS32: sll [[T3]],[[T3]],0x10 2443; MIPS32: sll [[T11]],[[T11]],0x10 2444; MIPS32: srl [[T11]],[[T11]],0x10 2445; MIPS32: or [[T3]],[[T3]],[[T11]] 2446; MIPS32: move a0,[[T2]] 2447; MIPS32: move a1,[[T3]] 2448} 2449 2450define internal <8 x i1> @test_icmp_v8i1_ule(<8 x i1> %a, <8 x i1> %b) { 2451entry: 2452 %res = icmp ule <8 x i1> %a, %b 2453 ret <8 x i1> %res 2454; CHECK-LABEL: test_icmp_v8i1_ule 2455; CHECK: pxor 2456; CHECK: pcmpgtw 2457; CHECK: pxor 2458 2459; MIPS32-LABEL: test_icmp_v8i1_ule 2460; MIPS32: lw [[T0:.*]], 2461; MIPS32: lw [[T1:.*]], 2462; MIPS32: lw [[T2:.*]], 2463; MIPS32: lw [[T3:.*]], 2464; MIPS32: move [[T4:.*]],zero 2465; MIPS32: move [[T5:.*]],zero 2466; MIPS32: move [[T6:.*]],zero 2467; MIPS32: move [[T7:.*]],zero 2468; MIPS32: move [[T8:.*]],a0 2469; MIPS32: andi [[T8]],[[T8]],0xffff 2470; MIPS32: andi [[T8]],[[T8]],0x1 2471; MIPS32: move [[T9:.*]],[[T0]] 2472; MIPS32: andi [[T9]],[[T9]],0xffff 2473; MIPS32: andi [[T9]],[[T9]],0x1 2474; MIPS32: sll [[T8]],[[T8]],0x1f 2475; MIPS32: sll [[T9]],[[T9]],0x1f 2476; MIPS32: sltu [[T9]],[[T9]],[[T8]] 2477; MIPS32: xori [[T9]],[[T9]],0x1 2478; MIPS32: andi [[T9]],[[T9]],0xffff 2479; MIPS32: srl [[T4]],[[T4]],0x10 2480; MIPS32: sll [[T4]],[[T4]],0x10 2481; MIPS32: or [[T9]],[[T9]],[[T4]] 2482; MIPS32: srl [[T10:.*]],a0,0x10 2483; MIPS32: andi [[T10]],[[T10]],0x1 2484; MIPS32: srl [[T0]],[[T0]],0x10 2485; MIPS32: andi [[T0]],[[T0]],0x1 2486; MIPS32: sll [[T10]],[[T10]],0x1f 2487; MIPS32: sll [[T0]],[[T0]],0x1f 2488; MIPS32: sltu [[T0]],[[T0]],[[T10]] 2489; MIPS32: xori [[T0]],[[T0]],0x1 2490; MIPS32: sll [[T0]],[[T0]],0x10 2491; MIPS32: sll [[T9]],[[T9]],0x10 2492; MIPS32: srl [[T9]],[[T9]],0x10 2493; MIPS32: or v0,[[T0]],[[T9]] 2494; MIPS32: move [[T10]],a1 2495; MIPS32: andi [[T10]],[[T10]],0xffff 2496; MIPS32: andi [[T10]],[[T10]],0x1 2497; MIPS32: move [[T4]],[[T1]] 2498; MIPS32: andi [[T4]],[[T4]],0xffff 2499; MIPS32: andi [[T4]],[[T4]],0x1 2500; MIPS32: sll [[T10]],[[T10]],0x1f 2501; MIPS32: sll [[T4]],[[T4]],0x1f 2502; MIPS32: sltu [[T4]],[[T4]],[[T10]] 2503; MIPS32: xori [[T4]],[[T4]],0x1 2504; MIPS32: andi [[T4]],[[T4]],0xffff 2505; MIPS32: srl [[T5]],[[T5]],0x10 2506; MIPS32: sll [[T5]],[[T5]],0x10 2507; MIPS32: or [[T4]],[[T4]],[[T5]] 2508; MIPS32: srl [[T11:.*]],a1,0x10 2509; MIPS32: andi [[T11]],[[T11]],0x1 2510; MIPS32: srl [[T1]],[[T1]],0x10 2511; MIPS32: andi [[T1]],[[T1]],0x1 2512; MIPS32: sll [[T11]],[[T11]],0x1f 2513; MIPS32: sll [[T1]],[[T1]],0x1f 2514; MIPS32: sltu [[T1]],[[T1]],[[T11]] 2515; MIPS32: xori [[T1]],[[T1]],0x1 2516; MIPS32: sll [[T1]],[[T1]],0x10 2517; MIPS32: sll [[T4]],[[T4]],0x10 2518; MIPS32: srl [[T4]],[[T4]],0x10 2519; MIPS32: or v1,[[T1]],[[T4]] 2520; MIPS32: move [[T10]],a2 2521; MIPS32: andi [[T10]],[[T10]],0xffff 2522; MIPS32: andi [[T10]],[[T10]],0x1 2523; MIPS32: move [[T11]],[[T2]] 2524; MIPS32: andi [[T11]],[[T11]],0xffff 2525; MIPS32: andi [[T11]],[[T11]],0x1 2526; MIPS32: sll [[T10]],[[T10]],0x1f 2527; MIPS32: sll [[T11]],[[T11]],0x1f 2528; MIPS32: sltu [[T11]],[[T11]],[[T10]] 2529; MIPS32: xori [[T11]],[[T11]],0x1 2530; MIPS32: andi [[T11]],[[T11]],0xffff 2531; MIPS32: srl [[T6]],[[T6]],0x10 2532; MIPS32: sll [[T6]],[[T6]],0x10 2533; MIPS32: or [[T11]],[[T11]],[[T6]] 2534; MIPS32: srl [[T12:.*]],a2,0x10 2535; MIPS32: andi [[T12]],[[T12]],0x1 2536; MIPS32: srl [[T2]],[[T2]],0x10 2537; MIPS32: andi [[T2]],[[T2]],0x1 2538; MIPS32: sll [[T12]],[[T12]],0x1f 2539; MIPS32: sll [[T2]],[[T2]],0x1f 2540; MIPS32: sltu [[T2]],[[T2]],[[T12]] 2541; MIPS32: xori [[T2]],[[T2]],0x1 2542; MIPS32: sll [[T2]],[[T2]],0x10 2543; MIPS32: sll [[T11]],[[T11]],0x10 2544; MIPS32: srl [[T11]],[[T11]],0x10 2545; MIPS32: or [[T2]],[[T2]],[[T11]] 2546; MIPS32: move [[T10]],a3 2547; MIPS32: andi [[T10]],[[T10]],0xffff 2548; MIPS32: andi [[T10]],[[T10]],0x1 2549; MIPS32: move [[T11]],[[T3]] 2550; MIPS32: andi [[T11]],[[T11]],0xffff 2551; MIPS32: andi [[T11]],[[T11]],0x1 2552; MIPS32: sll [[T10]],[[T10]],0x1f 2553; MIPS32: sll [[T11]],[[T11]],0x1f 2554; MIPS32: sltu [[T11]],[[T11]],[[T10]] 2555; MIPS32: xori [[T11]],[[T11]],0x1 2556; MIPS32: andi [[T11]],[[T11]],0xffff 2557; MIPS32: srl [[T7]],[[T7]],0x10 2558; MIPS32: sll [[T7]],[[T7]],0x10 2559; MIPS32: or [[T11]],[[T11]],[[T7]] 2560; MIPS32: srl [[T13:.*]],a3,0x10 2561; MIPS32: andi [[T13]],[[T13]],0x1 2562; MIPS32: srl [[T3]],[[T3]],0x10 2563; MIPS32: andi [[T3]],[[T3]],0x1 2564; MIPS32: sll [[T13]],[[T13]],0x1f 2565; MIPS32: sll [[T3]],[[T3]],0x1f 2566; MIPS32: sltu [[T3]],[[T3]],[[T13]] 2567; MIPS32: xori [[T3]],[[T3]],0x1 2568; MIPS32: sll [[T3]],[[T3]],0x10 2569; MIPS32: sll [[T11]],[[T11]],0x10 2570; MIPS32: srl [[T11]],[[T11]],0x10 2571; MIPS32: or [[T3]],[[T3]],[[T11]] 2572; MIPS32: move a0,[[T2]] 2573; MIPS32: move a1,[[T3]] 2574} 2575 2576define internal <8 x i1> @test_icmp_v8i1_ult(<8 x i1> %a, <8 x i1> %b) { 2577entry: 2578 %res = icmp ult <8 x i1> %a, %b 2579 ret <8 x i1> %res 2580; CHECK-LABEL: test_icmp_v8i1_ult 2581; CHECK: pxor 2582; CHECK: pcmpgtw 2583 2584; MIPS32-LABEL: test_icmp_v8i1_ult 2585; MIPS32: lw [[T0:.*]], 2586; MIPS32: lw [[T1:.*]], 2587; MIPS32: lw [[T2:.*]], 2588; MIPS32: lw [[T3:.*]], 2589; MIPS32: move [[T4:.*]],zero 2590; MIPS32: move [[T5:.*]],zero 2591; MIPS32: move [[T6:.*]],zero 2592; MIPS32: move [[T7:.*]],zero 2593; MIPS32: move [[T8:.*]],a0 2594; MIPS32: andi [[T8]],[[T8]],0xffff 2595; MIPS32: andi [[T8]],[[T8]],0x1 2596; MIPS32: move [[T9:.*]],[[T0]] 2597; MIPS32: andi [[T9]],[[T9]],0xffff 2598; MIPS32: andi [[T9]],[[T9]],0x1 2599; MIPS32: sll [[T8]],[[T8]],0x1f 2600; MIPS32: sll [[T9]],[[T9]],0x1f 2601; MIPS32: sltu [[T8]],[[T8]],[[T9]] 2602; MIPS32: andi [[T8]],[[T8]],0xffff 2603; MIPS32: srl [[T4]],[[T4]],0x10 2604; MIPS32: sll [[T4]],[[T4]],0x10 2605; MIPS32: or [[T8]],[[T8]],[[T4]] 2606; MIPS32: srl [[T10:.*]],a0,0x10 2607; MIPS32: andi [[T10]],[[T10]],0x1 2608; MIPS32: srl [[T0]],[[T0]],0x10 2609; MIPS32: andi [[T0]],[[T0]],0x1 2610; MIPS32: sll [[T10]],[[T10]],0x1f 2611; MIPS32: sll [[T0]],[[T0]],0x1f 2612; MIPS32: sltu [[T10]],[[T10]],[[T0]] 2613; MIPS32: sll [[T10]],[[T10]],0x10 2614; MIPS32: sll [[T8]],[[T8]],0x10 2615; MIPS32: srl [[T8]],[[T8]],0x10 2616; MIPS32: or [[T10]],[[T10]],[[T8]] 2617; MIPS32: move [[T0]],a1 2618; MIPS32: andi [[T0]],[[T0]],0xffff 2619; MIPS32: andi [[T0]],[[T0]],0x1 2620; MIPS32: move [[T4]],[[T1]] 2621; MIPS32: andi [[T4]],[[T4]],0xffff 2622; MIPS32: andi [[T4]],[[T4]],0x1 2623; MIPS32: sll [[T0]],[[T0]],0x1f 2624; MIPS32: sll [[T4]],[[T4]],0x1f 2625; MIPS32: sltu [[T0]],[[T0]],[[T4]] 2626; MIPS32: andi [[T0]],[[T0]],0xffff 2627; MIPS32: srl [[T5]],[[T5]],0x10 2628; MIPS32: sll [[T5]],[[T5]],0x10 2629; MIPS32: or [[T0]],[[T0]],[[T5]] 2630; MIPS32: srl [[T11:.*]],a1,0x10 2631; MIPS32: andi [[T11]],[[T11]],0x1 2632; MIPS32: srl [[T1]],[[T1]],0x10 2633; MIPS32: andi [[T1]],[[T1]],0x1 2634; MIPS32: sll [[T11]],[[T11]],0x1f 2635; MIPS32: sll [[T1]],[[T1]],0x1f 2636; MIPS32: sltu [[T11]],[[T11]],[[T1]] 2637; MIPS32: sll [[T11]],[[T11]],0x10 2638; MIPS32: sll [[T0]],[[T0]],0x10 2639; MIPS32: srl [[T0]],[[T0]],0x10 2640; MIPS32: or [[T11]],[[T11]],[[T0]] 2641; MIPS32: move [[T0]],a2 2642; MIPS32: andi [[T0]],[[T0]],0xffff 2643; MIPS32: andi [[T0]],[[T0]],0x1 2644; MIPS32: move [[T1]],[[T2]] 2645; MIPS32: andi [[T1]],[[T1]],0xffff 2646; MIPS32: andi [[T1]],[[T1]],0x1 2647; MIPS32: sll [[T0]],[[T0]],0x1f 2648; MIPS32: sll [[T1]],[[T1]],0x1f 2649; MIPS32: sltu [[T0]],[[T0]],[[T1]] 2650; MIPS32: andi [[T0]],[[T0]],0xffff 2651; MIPS32: srl [[T6]],[[T6]],0x10 2652; MIPS32: sll [[T6]],[[T6]],0x10 2653; MIPS32: or [[T0]],[[T0]],[[T6]] 2654; MIPS32: srl [[T12:.*]],a2,0x10 2655; MIPS32: andi [[T12]],[[T12]],0x1 2656; MIPS32: srl [[T2]],[[T2]],0x10 2657; MIPS32: andi [[T2]],[[T2]],0x1 2658; MIPS32: sll [[T12]],[[T12]],0x1f 2659; MIPS32: sll [[T2]],[[T2]],0x1f 2660; MIPS32: sltu [[T12]],[[T12]],[[T2]] 2661; MIPS32: sll [[T12]],[[T12]],0x10 2662; MIPS32: sll [[T0]],[[T0]],0x10 2663; MIPS32: srl [[T0]],[[T0]],0x10 2664; MIPS32: or [[T12]],[[T12]],[[T0]] 2665; MIPS32: move [[T0]],a3 2666; MIPS32: andi [[T0]],[[T0]],0xffff 2667; MIPS32: andi [[T0]],[[T0]],0x1 2668; MIPS32: move [[T1]],[[T3]] 2669; MIPS32: andi [[T1]],[[T1]],0xffff 2670; MIPS32: andi [[T1]],[[T1]],0x1 2671; MIPS32: sll [[T0]],[[T0]],0x1f 2672; MIPS32: sll [[T1]],[[T1]],0x1f 2673; MIPS32: sltu [[T0]],[[T0]],[[T1]] 2674; MIPS32: andi [[T0]],[[T0]],0xffff 2675; MIPS32: srl [[T7]],[[T7]],0x10 2676; MIPS32: sll [[T7]],[[T7]],0x10 2677; MIPS32: or [[T0]],[[T0]],[[T7]] 2678; MIPS32: srl [[T13:.*]],a3,0x10 2679; MIPS32: andi [[T13]],[[T13]],0x1 2680; MIPS32: srl [[T3]],[[T3]],0x10 2681; MIPS32: andi [[T3]],[[T3]],0x1 2682; MIPS32: sll [[T13]],[[T13]],0x1f 2683; MIPS32: sll [[T3]],[[T3]],0x1f 2684; MIPS32: sltu [[T13]],[[T13]],[[T3]] 2685; MIPS32: sll [[T13]],[[T13]],0x10 2686; MIPS32: sll [[T0]],[[T0]],0x10 2687; MIPS32: srl [[T0]],[[T0]],0x10 2688; MIPS32: or [[T13]],[[T13]],[[T0]] 2689; MIPS32: move v0,[[T10]] 2690; MIPS32: move v1,[[T11]] 2691; MIPS32: move a0,[[T12]] 2692; MIPS32: move a1,[[T13]] 2693} 2694 2695define internal <16 x i1> @test_icmp_v16i8_eq(<16 x i8> %a, <16 x i8> %b) { 2696entry: 2697 %res = icmp eq <16 x i8> %a, %b 2698 ret <16 x i1> %res 2699; CHECK-LABEL: test_icmp_v16i8_eq 2700; CHECK: pcmpeqb 2701 2702; MIPS32-LABEL: test_icmp_v16i8_eq 2703; MIPS32: lw [[T0:.*]], 2704; MIPS32: lw [[T1:.*]], 2705; MIPS32: lw [[T2:.*]], 2706; MIPS32: lw [[T3:.*]], 2707; MIPS32: move [[T4:.*]],zero 2708; MIPS32: move [[T5:.*]],zero 2709; MIPS32: move [[T6:.*]],zero 2710; MIPS32: move [[T7:.*]],zero 2711; MIPS32: move [[T8:.*]],a0 2712; MIPS32: andi [[T8]],[[T8]],0xff 2713; MIPS32: move [[T9:.*]],[[T0]] 2714; MIPS32: andi [[T9]],[[T9]],0xff 2715; MIPS32: sll [[T8]],[[T8]],0x18 2716; MIPS32: sll [[T9]],[[T9]],0x18 2717; MIPS32: xor [[T8]],[[T8]],[[T9]] 2718; MIPS32: sltiu [[T8]],[[T8]],1 2719; MIPS32: andi [[T8]],[[T8]],0xff 2720; MIPS32: srl [[T4]],[[T4]],0x8 2721; MIPS32: sll [[T4]],[[T4]],0x8 2722; MIPS32: or [[T8]],[[T8]],[[T4]] 2723; MIPS32: move [[T4]],a0 2724; MIPS32: srl [[T4]],[[T4]],0x8 2725; MIPS32: andi [[T4]],[[T4]],0xff 2726; MIPS32: move [[T9]],[[T0]] 2727; MIPS32: srl [[T9]],[[T9]],0x8 2728; MIPS32: andi [[T9]],[[T9]],0xff 2729; MIPS32: sll [[T4]],[[T4]],0x18 2730; MIPS32: sll [[T9]],[[T9]],0x18 2731; MIPS32: xor [[T4]],[[T4]],[[T9]] 2732; MIPS32: sltiu [[T4]],[[T4]],1 2733; MIPS32: andi [[T4]],[[T4]],0xff 2734; MIPS32: sll [[T4]],[[T4]],0x8 2735; MIPS32: lui [[T9]],0xffff 2736; MIPS32: ori [[T9]],[[T9]],0xff 2737; MIPS32: and [[T8]],[[T8]],[[T9]] 2738; MIPS32: or [[T4]],[[T4]],[[T8]] 2739; MIPS32: move [[T8]],a0 2740; MIPS32: srl [[T8]],[[T8]],0x10 2741; MIPS32: andi [[T8]],[[T8]],0xff 2742; MIPS32: move [[T9]],[[T0]] 2743; MIPS32: srl [[T9]],[[T9]],0x10 2744; MIPS32: andi [[T9]],[[T9]],0xff 2745; MIPS32: sll [[T8]],[[T8]],0x18 2746; MIPS32: sll [[T9]],[[T9]],0x18 2747; MIPS32: xor [[T8]],[[T8]],[[T9]] 2748; MIPS32: sltiu [[T8]],[[T8]],1 2749; MIPS32: andi [[T8]],[[T8]],0xff 2750; MIPS32: sll [[T8]],[[T8]],0x10 2751; MIPS32: lui [[T9]],0xff00 2752; MIPS32: ori [[T9]],[[T9]],0xffff 2753; MIPS32: and [[T4]],[[T4]],[[T9]] 2754; MIPS32: or [[T8]],[[T8]],[[T4]] 2755; MIPS32: srl [[T10:.*]],a0,0x18 2756; MIPS32: srl [[T0]],[[T0]],0x18 2757; MIPS32: sll [[T10]],[[T10]],0x18 2758; MIPS32: sll [[T0]],[[T0]],0x18 2759; MIPS32: xor [[T10]],[[T10]],[[T0]] 2760; MIPS32: sltiu [[T10]],[[T10]],1 2761; MIPS32: sll [[T10]],[[T10]],0x18 2762; MIPS32: sll [[T8]],[[T8]],0x8 2763; MIPS32: srl [[T8]],[[T8]],0x8 2764; MIPS32: or [[T10]],[[T10]],[[T8]] 2765; MIPS32: move [[T0]],a1 2766; MIPS32: andi [[T0]],[[T0]],0xff 2767; MIPS32: move [[T4]],[[T1]] 2768; MIPS32: andi [[T4]],[[T4]],0xff 2769; MIPS32: sll [[T0]],[[T0]],0x18 2770; MIPS32: sll [[T4]],[[T4]],0x18 2771; MIPS32: xor [[T0]],[[T0]],[[T4]] 2772; MIPS32: sltiu [[T0]],[[T0]],1 2773; MIPS32: andi [[T0]],[[T0]],0xff 2774; MIPS32: srl [[T5]],[[T5]],0x8 2775; MIPS32: sll [[T5]],[[T5]],0x8 2776; MIPS32: or [[T0]],[[T0]],[[T5]] 2777; MIPS32: move [[T4]],a1 2778; MIPS32: srl [[T4]],[[T4]],0x8 2779; MIPS32: andi [[T4]],[[T4]],0xff 2780; MIPS32: move [[T5]],[[T1]] 2781; MIPS32: srl [[T5]],[[T5]],0x8 2782; MIPS32: andi [[T5]],[[T5]],0xff 2783; MIPS32: sll [[T4]],[[T4]],0x18 2784; MIPS32: sll [[T5]],[[T5]],0x18 2785; MIPS32: xor [[T4]],[[T4]],[[T5]] 2786; MIPS32: sltiu [[T4]],[[T4]],1 2787; MIPS32: andi [[T4]],[[T4]],0xff 2788; MIPS32: sll [[T4]],[[T4]],0x8 2789; MIPS32: lui [[T5]],0xffff 2790; MIPS32: ori [[T5]],[[T5]],0xff 2791; MIPS32: and [[T0]],[[T0]],[[T5]] 2792; MIPS32: or [[T4]],[[T4]],[[T0]] 2793; MIPS32: move [[T0]],a1 2794; MIPS32: srl [[T0]],[[T0]],0x10 2795; MIPS32: andi [[T0]],[[T0]],0xff 2796; MIPS32: move [[T5]],[[T1]] 2797; MIPS32: srl [[T5]],[[T5]],0x10 2798; MIPS32: andi [[T5]],[[T5]],0xff 2799; MIPS32: sll [[T0]],[[T0]],0x18 2800; MIPS32: sll [[T5]],[[T5]],0x18 2801; MIPS32: xor [[T0]],[[T0]],[[T5]] 2802; MIPS32: sltiu [[T0]],[[T0]],1 2803; MIPS32: andi [[T0]],[[T0]],0xff 2804; MIPS32: sll [[T0]],[[T0]],0x10 2805; MIPS32: lui [[T5]],0xff00 2806; MIPS32: ori [[T5]],[[T5]],0xffff 2807; MIPS32: and [[T4]],[[T4]],[[T5]] 2808; MIPS32: or [[T0]],[[T0]],[[T4]] 2809; MIPS32: srl [[T11:.*]],a1,0x18 2810; MIPS32: srl [[T1]],[[T1]],0x18 2811; MIPS32: sll [[T11]],[[T11]],0x18 2812; MIPS32: sll [[T1]],[[T1]],0x18 2813; MIPS32: xor [[T11]],[[T11]],[[T1]] 2814; MIPS32: sltiu [[T11]],[[T11]],1 2815; MIPS32: sll [[T11]],[[T11]],0x18 2816; MIPS32: sll [[T0]],[[T0]],0x8 2817; MIPS32: srl [[T0]],[[T0]],0x8 2818; MIPS32: or [[T11]],[[T11]],[[T0]] 2819; MIPS32: move [[T0]],a2 2820; MIPS32: andi [[T0]],[[T0]],0xff 2821; MIPS32: move [[T1]],[[T2]] 2822; MIPS32: andi [[T1]],[[T1]],0xff 2823; MIPS32: sll [[T0]],[[T0]],0x18 2824; MIPS32: sll [[T1]],[[T1]],0x18 2825; MIPS32: xor [[T0]],[[T0]],[[T1]] 2826; MIPS32: sltiu [[T0]],[[T0]],1 2827; MIPS32: andi [[T0]],[[T0]],0xff 2828; MIPS32: srl [[T6]],[[T6]],0x8 2829; MIPS32: sll [[T6]],[[T6]],0x8 2830; MIPS32: or [[T0]],[[T0]],[[T6]] 2831; MIPS32: move [[T1]],a2 2832; MIPS32: srl [[T1]],[[T1]],0x8 2833; MIPS32: andi [[T1]],[[T1]],0xff 2834; MIPS32: move [[T4]],[[T2]] 2835; MIPS32: srl [[T4]],[[T4]],0x8 2836; MIPS32: andi [[T4]],[[T4]],0xff 2837; MIPS32: sll [[T1]],[[T1]],0x18 2838; MIPS32: sll [[T4]],[[T4]],0x18 2839; MIPS32: xor [[T1]],[[T1]],[[T4]] 2840; MIPS32: sltiu [[T1]],[[T1]],1 2841; MIPS32: andi [[T1]],[[T1]],0xff 2842; MIPS32: sll [[T1]],[[T1]],0x8 2843; MIPS32: lui [[T4]],0xffff 2844; MIPS32: ori [[T4]],[[T4]],0xff 2845; MIPS32: and [[T0]],[[T0]],[[T4]] 2846; MIPS32: or [[T1]],[[T1]],[[T0]] 2847; MIPS32: move [[T0]],a2 2848; MIPS32: srl [[T0]],[[T0]],0x10 2849; MIPS32: andi [[T0]],[[T0]],0xff 2850; MIPS32: move [[T4]],[[T2]] 2851; MIPS32: srl [[T4]],[[T4]],0x10 2852; MIPS32: andi [[T4]],[[T4]],0xff 2853; MIPS32: sll [[T0]],[[T0]],0x18 2854; MIPS32: sll [[T4]],[[T4]],0x18 2855; MIPS32: xor [[T0]],[[T0]],[[T4]] 2856; MIPS32: sltiu [[T0]],[[T0]],1 2857; MIPS32: andi [[T0]],[[T0]],0xff 2858; MIPS32: sll [[T0]],[[T0]],0x10 2859; MIPS32: lui [[T4]],0xff00 2860; MIPS32: ori [[T4]],[[T4]],0xffff 2861; MIPS32: and [[T1]],[[T1]],[[T4]] 2862; MIPS32: or [[T0]],[[T0]],[[T1]] 2863; MIPS32: srl [[T12:.*]],a2,0x18 2864; MIPS32: srl [[T2]],[[T2]],0x18 2865; MIPS32: sll [[T12]],[[T12]],0x18 2866; MIPS32: sll [[T2]],[[T2]],0x18 2867; MIPS32: xor [[T12]],[[T12]],[[T2]] 2868; MIPS32: sltiu [[T12]],[[T12]],1 2869; MIPS32: sll [[T12]],[[T12]],0x18 2870; MIPS32: sll [[T0]],[[T0]],0x8 2871; MIPS32: srl [[T0]],[[T0]],0x8 2872; MIPS32: or [[T12]],[[T12]],[[T0]] 2873; MIPS32: move [[T0]],a3 2874; MIPS32: andi [[T0]],[[T0]],0xff 2875; MIPS32: move [[T1]],[[T3]] 2876; MIPS32: andi [[T1]],[[T1]],0xff 2877; MIPS32: sll [[T0]],[[T0]],0x18 2878; MIPS32: sll [[T1]],[[T1]],0x18 2879; MIPS32: xor [[T0]],[[T0]],[[T1]] 2880; MIPS32: sltiu [[T0]],[[T0]],1 2881; MIPS32: andi [[T0]],[[T0]],0xff 2882; MIPS32: srl [[T7]],[[T7]],0x8 2883; MIPS32: sll [[T7]],[[T7]],0x8 2884; MIPS32: or [[T0]],[[T0]],[[T7]] 2885; MIPS32: move [[T1]],a3 2886; MIPS32: srl [[T1]],[[T1]],0x8 2887; MIPS32: andi [[T1]],[[T1]],0xff 2888; MIPS32: move [[T2]],[[T3]] 2889; MIPS32: srl [[T2]],[[T2]],0x8 2890; MIPS32: andi [[T2]],[[T2]],0xff 2891; MIPS32: sll [[T1]],[[T1]],0x18 2892; MIPS32: sll [[T2]],[[T2]],0x18 2893; MIPS32: xor [[T1]],[[T1]],[[T2]] 2894; MIPS32: sltiu [[T1]],[[T1]],1 2895; MIPS32: andi [[T1]],[[T1]],0xff 2896; MIPS32: sll [[T1]],[[T1]],0x8 2897; MIPS32: lui [[T2]],0xffff 2898; MIPS32: ori [[T2]],[[T2]],0xff 2899; MIPS32: and [[T0]],[[T0]],[[T2]] 2900; MIPS32: or [[T1]],[[T1]],[[T0]] 2901; MIPS32: move [[T0]],a3 2902; MIPS32: srl [[T0]],[[T0]],0x10 2903; MIPS32: andi [[T0]],[[T0]],0xff 2904; MIPS32: move [[T2]],[[T3]] 2905; MIPS32: srl [[T2]],[[T2]],0x10 2906; MIPS32: andi [[T2]],[[T2]],0xff 2907; MIPS32: sll [[T0]],[[T0]],0x18 2908; MIPS32: sll [[T2]],[[T2]],0x18 2909; MIPS32: xor [[T0]],[[T0]],[[T2]] 2910; MIPS32: sltiu [[T0]],[[T0]],1 2911; MIPS32: andi [[T0]],[[T0]],0xff 2912; MIPS32: sll [[T0]],[[T0]],0x10 2913; MIPS32: lui [[T2]],0xff00 2914; MIPS32: ori [[T2]],[[T2]],0xffff 2915; MIPS32: and [[T1]],[[T1]],[[T2]] 2916; MIPS32: or [[T0]],[[T0]],[[T1]] 2917; MIPS32: srl [[T13:.*]],a3,0x18 2918; MIPS32: srl [[T3]],[[T3]],0x18 2919; MIPS32: sll [[T13]],[[T13]],0x18 2920; MIPS32: sll [[T3]],[[T3]],0x18 2921; MIPS32: xor [[T13]],[[T13]],[[T3]] 2922; MIPS32: sltiu [[T13]],[[T13]],1 2923; MIPS32: sll [[T13]],[[T13]],0x18 2924; MIPS32: sll [[T0]],[[T0]],0x8 2925; MIPS32: srl [[T0]],[[T0]],0x8 2926; MIPS32: or [[T13]],[[T13]],[[T0]] 2927; MIPS32: move v0,[[T10]] 2928; MIPS32: move v1,[[T11]] 2929; MIPS32: move a0,[[T12]] 2930; MIPS32: move a1,[[T13]] 2931} 2932 2933define internal <16 x i1> @test_icmp_v16i8_ne(<16 x i8> %a, <16 x i8> %b) { 2934entry: 2935 %res = icmp ne <16 x i8> %a, %b 2936 ret <16 x i1> %res 2937; CHECK-LABEL: test_icmp_v16i8_ne 2938; CHECK: pcmpeqb 2939; CHECK: pxor 2940 2941; MIPS32-LABEL: test_icmp_v16i8_ne 2942; MIPS32: lw [[T0:.*]], 2943; MIPS32: lw [[T1:.*]], 2944; MIPS32: lw [[T2:.*]], 2945; MIPS32: lw [[T3:.*]], 2946; MIPS32: move [[T4:.*]],zero 2947; MIPS32: move [[T5:.*]],zero 2948; MIPS32: move [[T6:.*]],zero 2949; MIPS32: move [[T7:.*]],zero 2950; MIPS32: move [[T8:.*]],a0 2951; MIPS32: andi [[T8]],[[T8]],0xff 2952; MIPS32: move [[T9:.*]],[[T0]] 2953; MIPS32: andi [[T9]],[[T9]],0xff 2954; MIPS32: sll [[T8]],[[T8]],0x18 2955; MIPS32: sll [[T9]],[[T9]],0x18 2956; MIPS32: xor [[T8]],[[T8]],[[T9]] 2957; MIPS32: sltu [[T8]],zero,[[T8]] 2958; MIPS32: andi [[T8]],[[T8]],0xff 2959; MIPS32: srl [[T4]],[[T4]],0x8 2960; MIPS32: sll [[T4]],[[T4]],0x8 2961; MIPS32: or [[T8]],[[T8]],[[T4]] 2962; MIPS32: move [[T4]],a0 2963; MIPS32: srl [[T4]],[[T4]],0x8 2964; MIPS32: andi [[T4]],[[T4]],0xff 2965; MIPS32: move [[T9]],[[T0]] 2966; MIPS32: srl [[T9]],[[T9]],0x8 2967; MIPS32: andi [[T9]],[[T9]],0xff 2968; MIPS32: sll [[T4]],[[T4]],0x18 2969; MIPS32: sll [[T9]],[[T9]],0x18 2970; MIPS32: xor [[T4]],[[T4]],[[T9]] 2971; MIPS32: sltu [[T4]],zero,[[T4]] 2972; MIPS32: andi [[T4]],[[T4]],0xff 2973; MIPS32: sll [[T4]],[[T4]],0x8 2974; MIPS32: lui [[T9]],0xffff 2975; MIPS32: ori [[T9]],[[T9]],0xff 2976; MIPS32: and [[T8]],[[T8]],[[T9]] 2977; MIPS32: or [[T4]],[[T4]],[[T8]] 2978; MIPS32: move [[T8]],a0 2979; MIPS32: srl [[T8]],[[T8]],0x10 2980; MIPS32: andi [[T8]],[[T8]],0xff 2981; MIPS32: move [[T9]],[[T0]] 2982; MIPS32: srl [[T9]],[[T9]],0x10 2983; MIPS32: andi [[T9]],[[T9]],0xff 2984; MIPS32: sll [[T8]],[[T8]],0x18 2985; MIPS32: sll [[T9]],[[T9]],0x18 2986; MIPS32: xor [[T8]],[[T8]],[[T9]] 2987; MIPS32: sltu [[T8]],zero,[[T8]] 2988; MIPS32: andi [[T8]],[[T8]],0xff 2989; MIPS32: sll [[T8]],[[T8]],0x10 2990; MIPS32: lui [[T9]],0xff00 2991; MIPS32: ori [[T9]],[[T9]],0xffff 2992; MIPS32: and [[T4]],[[T4]],[[T9]] 2993; MIPS32: or [[T8]],[[T8]],[[T4]] 2994; MIPS32: srl [[T10:.*]],a0,0x18 2995; MIPS32: srl [[T0]],[[T0]],0x18 2996; MIPS32: sll [[T10]],[[T10]],0x18 2997; MIPS32: sll [[T0]],[[T0]],0x18 2998; MIPS32: xor [[T10]],[[T10]],[[T0]] 2999; MIPS32: sltu [[T10]],zero,[[T10]] 3000; MIPS32: sll [[T10]],[[T10]],0x18 3001; MIPS32: sll [[T8]],[[T8]],0x8 3002; MIPS32: srl [[T8]],[[T8]],0x8 3003; MIPS32: or [[T10]],[[T10]],[[T8]] 3004; MIPS32: move [[T0]],a1 3005; MIPS32: andi [[T0]],[[T0]],0xff 3006; MIPS32: move [[T4]],[[T1]] 3007; MIPS32: andi [[T4]],[[T4]],0xff 3008; MIPS32: sll [[T0]],[[T0]],0x18 3009; MIPS32: sll [[T4]],[[T4]],0x18 3010; MIPS32: xor [[T0]],[[T0]],[[T4]] 3011; MIPS32: sltu [[T0]],zero,[[T0]] 3012; MIPS32: andi [[T0]],[[T0]],0xff 3013; MIPS32: srl [[T5]],[[T5]],0x8 3014; MIPS32: sll [[T5]],[[T5]],0x8 3015; MIPS32: or [[T0]],[[T0]],[[T5]] 3016; MIPS32: move [[T4]],a1 3017; MIPS32: srl [[T4]],[[T4]],0x8 3018; MIPS32: andi [[T4]],[[T4]],0xff 3019; MIPS32: move [[T5]],[[T1]] 3020; MIPS32: srl [[T5]],[[T5]],0x8 3021; MIPS32: andi [[T5]],[[T5]],0xff 3022; MIPS32: sll [[T4]],[[T4]],0x18 3023; MIPS32: sll [[T5]],[[T5]],0x18 3024; MIPS32: xor [[T4]],[[T4]],[[T5]] 3025; MIPS32: sltu [[T4]],zero,[[T4]] 3026; MIPS32: andi [[T4]],[[T4]],0xff 3027; MIPS32: sll [[T4]],[[T4]],0x8 3028; MIPS32: lui [[T5]],0xffff 3029; MIPS32: ori [[T5]],[[T5]],0xff 3030; MIPS32: and [[T0]],[[T0]],[[T5]] 3031; MIPS32: or [[T4]],[[T4]],[[T0]] 3032; MIPS32: move [[T0]],a1 3033; MIPS32: srl [[T0]],[[T0]],0x10 3034; MIPS32: andi [[T0]],[[T0]],0xff 3035; MIPS32: move [[T5]],[[T1]] 3036; MIPS32: srl [[T5]],[[T5]],0x10 3037; MIPS32: andi [[T5]],[[T5]],0xff 3038; MIPS32: sll [[T0]],[[T0]],0x18 3039; MIPS32: sll [[T5]],[[T5]],0x18 3040; MIPS32: xor [[T0]],[[T0]],[[T5]] 3041; MIPS32: sltu [[T0]],zero,[[T0]] 3042; MIPS32: andi [[T0]],[[T0]],0xff 3043; MIPS32: sll [[T0]],[[T0]],0x10 3044; MIPS32: lui [[T5]],0xff00 3045; MIPS32: ori [[T5]],[[T5]],0xffff 3046; MIPS32: and [[T4]],[[T4]],[[T5]] 3047; MIPS32: or [[T0]],[[T0]],[[T4]] 3048; MIPS32: srl [[T11:.*]],a1,0x18 3049; MIPS32: srl [[T1]],[[T1]],0x18 3050; MIPS32: sll [[T11]],[[T11]],0x18 3051; MIPS32: sll [[T1]],[[T1]],0x18 3052; MIPS32: xor [[T11]],[[T11]],[[T1]] 3053; MIPS32: sltu [[T11]],zero,[[T11]] 3054; MIPS32: sll [[T11]],[[T11]],0x18 3055; MIPS32: sll [[T0]],[[T0]],0x8 3056; MIPS32: srl [[T0]],[[T0]],0x8 3057; MIPS32: or [[T11]],[[T11]],[[T0]] 3058; MIPS32: move [[T0]],a2 3059; MIPS32: andi [[T0]],[[T0]],0xff 3060; MIPS32: move [[T1]],[[T2]] 3061; MIPS32: andi [[T1]],[[T1]],0xff 3062; MIPS32: sll [[T0]],[[T0]],0x18 3063; MIPS32: sll [[T1]],[[T1]],0x18 3064; MIPS32: xor [[T0]],[[T0]],[[T1]] 3065; MIPS32: sltu [[T0]],zero,[[T0]] 3066; MIPS32: andi [[T0]],[[T0]],0xff 3067; MIPS32: srl [[T6]],[[T6]],0x8 3068; MIPS32: sll [[T6]],[[T6]],0x8 3069; MIPS32: or [[T0]],[[T0]],[[T6]] 3070; MIPS32: move [[T1]],a2 3071; MIPS32: srl [[T1]],[[T1]],0x8 3072; MIPS32: andi [[T1]],[[T1]],0xff 3073; MIPS32: move [[T4]],[[T2]] 3074; MIPS32: srl [[T4]],[[T4]],0x8 3075; MIPS32: andi [[T4]],[[T4]],0xff 3076; MIPS32: sll [[T1]],[[T1]],0x18 3077; MIPS32: sll [[T4]],[[T4]],0x18 3078; MIPS32: xor [[T1]],[[T1]],[[T4]] 3079; MIPS32: sltu [[T1]],zero,[[T1]] 3080; MIPS32: andi [[T1]],[[T1]],0xff 3081; MIPS32: sll [[T1]],[[T1]],0x8 3082; MIPS32: lui [[T4]],0xffff 3083; MIPS32: ori [[T4]],[[T4]],0xff 3084; MIPS32: and [[T0]],[[T0]],[[T4]] 3085; MIPS32: or [[T1]],[[T1]],[[T0]] 3086; MIPS32: move [[T0]],a2 3087; MIPS32: srl [[T0]],[[T0]],0x10 3088; MIPS32: andi [[T0]],[[T0]],0xff 3089; MIPS32: move [[T4]],[[T2]] 3090; MIPS32: srl [[T4]],[[T4]],0x10 3091; MIPS32: andi [[T4]],[[T4]],0xff 3092; MIPS32: sll [[T0]],[[T0]],0x18 3093; MIPS32: sll [[T4]],[[T4]],0x18 3094; MIPS32: xor [[T0]],[[T0]],[[T4]] 3095; MIPS32: sltu [[T0]],zero,[[T0]] 3096; MIPS32: andi [[T0]],[[T0]],0xff 3097; MIPS32: sll [[T0]],[[T0]],0x10 3098; MIPS32: lui [[T4]],0xff00 3099; MIPS32: ori [[T4]],[[T4]],0xffff 3100; MIPS32: and [[T1]],[[T1]],[[T4]] 3101; MIPS32: or [[T0]],[[T0]],[[T1]] 3102; MIPS32: srl [[T12:.*]],a2,0x18 3103; MIPS32: srl [[T2]],[[T2]],0x18 3104; MIPS32: sll [[T12]],[[T12]],0x18 3105; MIPS32: sll [[T2]],[[T2]],0x18 3106; MIPS32: xor [[T12]],[[T12]],[[T2]] 3107; MIPS32: sltu [[T12]],zero,[[T12]] 3108; MIPS32: sll [[T12]],[[T12]],0x18 3109; MIPS32: sll [[T0]],[[T0]],0x8 3110; MIPS32: srl [[T0]],[[T0]],0x8 3111; MIPS32: or [[T12]],[[T12]],[[T0]] 3112; MIPS32: move [[T0]],a3 3113; MIPS32: andi [[T0]],[[T0]],0xff 3114; MIPS32: move [[T1]],[[T3]] 3115; MIPS32: andi [[T1]],[[T1]],0xff 3116; MIPS32: sll [[T0]],[[T0]],0x18 3117; MIPS32: sll [[T1]],[[T1]],0x18 3118; MIPS32: xor [[T0]],[[T0]],[[T1]] 3119; MIPS32: sltu [[T0]],zero,[[T0]] 3120; MIPS32: andi [[T0]],[[T0]],0xff 3121; MIPS32: srl [[T7]],[[T7]],0x8 3122; MIPS32: sll [[T7]],[[T7]],0x8 3123; MIPS32: or [[T0]],[[T0]],[[T7]] 3124; MIPS32: move [[T1]],a3 3125; MIPS32: srl [[T1]],[[T1]],0x8 3126; MIPS32: andi [[T1]],[[T1]],0xff 3127; MIPS32: move [[T2]],[[T3]] 3128; MIPS32: srl [[T2]],[[T2]],0x8 3129; MIPS32: andi [[T2]],[[T2]],0xff 3130; MIPS32: sll [[T1]],[[T1]],0x18 3131; MIPS32: sll [[T2]],[[T2]],0x18 3132; MIPS32: xor [[T1]],[[T1]],[[T2]] 3133; MIPS32: sltu [[T1]],zero,[[T1]] 3134; MIPS32: andi [[T1]],[[T1]],0xff 3135; MIPS32: sll [[T1]],[[T1]],0x8 3136; MIPS32: lui [[T2]],0xffff 3137; MIPS32: ori [[T2]],[[T2]],0xff 3138; MIPS32: and [[T0]],[[T0]],[[T2]] 3139; MIPS32: or [[T1]],[[T1]],[[T0]] 3140; MIPS32: move [[T0]],a3 3141; MIPS32: srl [[T0]],[[T0]],0x10 3142; MIPS32: andi [[T0]],[[T0]],0xff 3143; MIPS32: move [[T2]],[[T3]] 3144; MIPS32: srl [[T2]],[[T2]],0x10 3145; MIPS32: andi [[T2]],[[T2]],0xff 3146; MIPS32: sll [[T0]],[[T0]],0x18 3147; MIPS32: sll [[T2]],[[T2]],0x18 3148; MIPS32: xor [[T0]],[[T0]],[[T2]] 3149; MIPS32: sltu [[T0]],zero,[[T0]] 3150; MIPS32: andi [[T0]],[[T0]],0xff 3151; MIPS32: sll [[T0]],[[T0]],0x10 3152; MIPS32: lui [[T2]],0xff00 3153; MIPS32: ori [[T2]],[[T2]],0xffff 3154; MIPS32: and [[T1]],[[T1]],[[T2]] 3155; MIPS32: or [[T0]],[[T0]],[[T1]] 3156; MIPS32: srl [[T13:.*]],a3,0x18 3157; MIPS32: srl [[T3]],[[T3]],0x18 3158; MIPS32: sll [[T13]],[[T13]],0x18 3159; MIPS32: sll [[T3]],[[T3]],0x18 3160; MIPS32: xor [[T13]],[[T13]],[[T3]] 3161; MIPS32: sltu [[T13]],zero,[[T13]] 3162; MIPS32: sll [[T13]],[[T13]],0x18 3163; MIPS32: sll [[T0]],[[T0]],0x8 3164; MIPS32: srl [[T0]],[[T0]],0x8 3165; MIPS32: or [[T13]],[[T13]],[[T0]] 3166; MIPS32: move v0,[[T10]] 3167; MIPS32: move v1,[[T11]] 3168; MIPS32: move a0,[[T12]] 3169; MIPS32: move a1,[[T13]] 3170} 3171 3172define internal <16 x i1> @test_icmp_v16i8_sgt(<16 x i8> %a, <16 x i8> %b) { 3173entry: 3174 %res = icmp sgt <16 x i8> %a, %b 3175 ret <16 x i1> %res 3176; CHECK-LABEL: test_icmp_v16i8_sgt 3177; CHECK: pcmpgtb 3178 3179; MIPS32-LABEL: test_icmp_v16i8_sgt 3180; MIPS32: lw [[T0:.*]], 3181; MIPS32: lw [[T1:.*]], 3182; MIPS32: lw [[T2:.*]], 3183; MIPS32: lw [[T3:.*]], 3184; MIPS32: move [[T4:.*]],zero 3185; MIPS32: move [[T5:.*]],zero 3186; MIPS32: move [[T6:.*]],zero 3187; MIPS32: move [[T7:.*]],zero 3188; MIPS32: move [[T8:.*]],a0 3189; MIPS32: andi [[T8]],[[T8]],0xff 3190; MIPS32: move [[T9:.*]],[[T0]] 3191; MIPS32: andi [[T9]],[[T9]],0xff 3192; MIPS32: sll [[T8]],[[T8]],0x18 3193; MIPS32: sll [[T9]],[[T9]],0x18 3194; MIPS32: slt [[T9]],[[T9]],[[T8]] 3195; MIPS32: andi [[T9]],[[T9]],0xff 3196; MIPS32: srl [[T4]],[[T4]],0x8 3197; MIPS32: sll [[T4]],[[T4]],0x8 3198; MIPS32: or [[T9]],[[T9]],[[T4]] 3199; MIPS32: move [[T4]],a0 3200; MIPS32: srl [[T4]],[[T4]],0x8 3201; MIPS32: andi [[T4]],[[T4]],0xff 3202; MIPS32: move [[T8]],[[T0]] 3203; MIPS32: srl [[T8]],[[T8]],0x8 3204; MIPS32: andi [[T8]],[[T8]],0xff 3205; MIPS32: sll [[T4]],[[T4]],0x18 3206; MIPS32: sll [[T8]],[[T8]],0x18 3207; MIPS32: slt [[T8]],[[T8]],[[T4]] 3208; MIPS32: andi [[T8]],[[T8]],0xff 3209; MIPS32: sll [[T8]],[[T8]],0x8 3210; MIPS32: lui [[T4]],0xffff 3211; MIPS32: ori [[T4]],[[T4]],0xff 3212; MIPS32: and [[T9]],[[T9]],[[T4]] 3213; MIPS32: or [[T8]],[[T8]],[[T9]] 3214; MIPS32: move [[T4]],a0 3215; MIPS32: srl [[T4]],[[T4]],0x10 3216; MIPS32: andi [[T4]],[[T4]],0xff 3217; MIPS32: move [[T9]],[[T0]] 3218; MIPS32: srl [[T9]],[[T9]],0x10 3219; MIPS32: andi [[T9]],[[T9]],0xff 3220; MIPS32: sll [[T4]],[[T4]],0x18 3221; MIPS32: sll [[T9]],[[T9]],0x18 3222; MIPS32: slt [[T9]],[[T9]],[[T4]] 3223; MIPS32: andi [[T9]],[[T9]],0xff 3224; MIPS32: sll [[T9]],[[T9]],0x10 3225; MIPS32: lui [[T4]],0xff00 3226; MIPS32: ori [[T4]],[[T4]],0xffff 3227; MIPS32: and [[T8]],[[T8]],[[T4]] 3228; MIPS32: or [[T9]],[[T9]],[[T8]] 3229; MIPS32: srl [[T10:.*]],a0,0x18 3230; MIPS32: srl [[T0]],[[T0]],0x18 3231; MIPS32: sll [[T10]],[[T10]],0x18 3232; MIPS32: sll [[T0]],[[T0]],0x18 3233; MIPS32: slt [[T0]],[[T0]],[[T10]] 3234; MIPS32: sll [[T0]],[[T0]],0x18 3235; MIPS32: sll [[T9]],[[T9]],0x8 3236; MIPS32: srl [[T9]],[[T9]],0x8 3237; MIPS32: or v0,[[T0]],[[T9]] 3238; MIPS32: move [[T10]],a1 3239; MIPS32: andi [[T10]],[[T10]],0xff 3240; MIPS32: move [[T4]],[[T1]] 3241; MIPS32: andi [[T4]],[[T4]],0xff 3242; MIPS32: sll [[T10]],[[T10]],0x18 3243; MIPS32: sll [[T4]],[[T4]],0x18 3244; MIPS32: slt [[T4]],[[T4]],[[T10]] 3245; MIPS32: andi [[T4]],[[T4]],0xff 3246; MIPS32: srl [[T5]],[[T5]],0x8 3247; MIPS32: sll [[T5]],[[T5]],0x8 3248; MIPS32: or [[T4]],[[T4]],[[T5]] 3249; MIPS32: move [[T10]],a1 3250; MIPS32: srl [[T10]],[[T10]],0x8 3251; MIPS32: andi [[T10]],[[T10]],0xff 3252; MIPS32: move [[T5]],[[T1]] 3253; MIPS32: srl [[T5]],[[T5]],0x8 3254; MIPS32: andi [[T5]],[[T5]],0xff 3255; MIPS32: sll [[T10]],[[T10]],0x18 3256; MIPS32: sll [[T5]],[[T5]],0x18 3257; MIPS32: slt [[T5]],[[T5]],[[T10]] 3258; MIPS32: andi [[T5]],[[T5]],0xff 3259; MIPS32: sll [[T5]],[[T5]],0x8 3260; MIPS32: lui [[T10]],0xffff 3261; MIPS32: ori [[T10]],[[T10]],0xff 3262; MIPS32: and [[T4]],[[T4]],[[T10]] 3263; MIPS32: or [[T5]],[[T5]],[[T4]] 3264; MIPS32: move [[T10]],a1 3265; MIPS32: srl [[T10]],[[T10]],0x10 3266; MIPS32: andi [[T10]],[[T10]],0xff 3267; MIPS32: move [[T4]],[[T1]] 3268; MIPS32: srl [[T4]],[[T4]],0x10 3269; MIPS32: andi [[T4]],[[T4]],0xff 3270; MIPS32: sll [[T10]],[[T10]],0x18 3271; MIPS32: sll [[T4]],[[T4]],0x18 3272; MIPS32: slt [[T4]],[[T4]],[[T10]] 3273; MIPS32: andi [[T4]],[[T4]],0xff 3274; MIPS32: sll [[T4]],[[T4]],0x10 3275; MIPS32: lui [[T10]],0xff00 3276; MIPS32: ori [[T10]],[[T10]],0xffff 3277; MIPS32: and [[T5]],[[T5]],[[T10]] 3278; MIPS32: or [[T4]],[[T4]],[[T5]] 3279; MIPS32: srl [[T11:.*]],a1,0x18 3280; MIPS32: srl [[T1]],[[T1]],0x18 3281; MIPS32: sll [[T11]],[[T11]],0x18 3282; MIPS32: sll [[T1]],[[T1]],0x18 3283; MIPS32: slt [[T1]],[[T1]],[[T11]] 3284; MIPS32: sll [[T1]],[[T1]],0x18 3285; MIPS32: sll [[T4]],[[T4]],0x8 3286; MIPS32: srl [[T4]],[[T4]],0x8 3287; MIPS32: or v1,[[T1]],[[T4]] 3288; MIPS32: move [[T10]],a2 3289; MIPS32: andi [[T10]],[[T10]],0xff 3290; MIPS32: move [[T11]],[[T2]] 3291; MIPS32: andi [[T11]],[[T11]],0xff 3292; MIPS32: sll [[T10]],[[T10]],0x18 3293; MIPS32: sll [[T11]],[[T11]],0x18 3294; MIPS32: slt [[T11]],[[T11]],[[T10]] 3295; MIPS32: andi [[T11]],[[T11]],0xff 3296; MIPS32: srl [[T6]],[[T6]],0x8 3297; MIPS32: sll [[T6]],[[T6]],0x8 3298; MIPS32: or [[T11]],[[T11]],[[T6]] 3299; MIPS32: move [[T10]],a2 3300; MIPS32: srl [[T10]],[[T10]],0x8 3301; MIPS32: andi [[T10]],[[T10]],0xff 3302; MIPS32: move [[T4]],[[T2]] 3303; MIPS32: srl [[T4]],[[T4]],0x8 3304; MIPS32: andi [[T4]],[[T4]],0xff 3305; MIPS32: sll [[T10]],[[T10]],0x18 3306; MIPS32: sll [[T4]],[[T4]],0x18 3307; MIPS32: slt [[T4]],[[T4]],[[T10]] 3308; MIPS32: andi [[T4]],[[T4]],0xff 3309; MIPS32: sll [[T4]],[[T4]],0x8 3310; MIPS32: lui [[T10]],0xffff 3311; MIPS32: ori [[T10]],[[T10]],0xff 3312; MIPS32: and [[T11]],[[T11]],[[T10]] 3313; MIPS32: or [[T4]],[[T4]],[[T11]] 3314; MIPS32: move [[T10]],a2 3315; MIPS32: srl [[T10]],[[T10]],0x10 3316; MIPS32: andi [[T10]],[[T10]],0xff 3317; MIPS32: move [[T11]],[[T2]] 3318; MIPS32: srl [[T11]],[[T11]],0x10 3319; MIPS32: andi [[T11]],[[T11]],0xff 3320; MIPS32: sll [[T10]],[[T10]],0x18 3321; MIPS32: sll [[T11]],[[T11]],0x18 3322; MIPS32: slt [[T11]],[[T11]],[[T10]] 3323; MIPS32: andi [[T11]],[[T11]],0xff 3324; MIPS32: sll [[T11]],[[T11]],0x10 3325; MIPS32: lui [[T10]],0xff00 3326; MIPS32: ori [[T10]],[[T10]],0xffff 3327; MIPS32: and [[T4]],[[T4]],[[T10]] 3328; MIPS32: or [[T11]],[[T11]],[[T4]] 3329; MIPS32: srl [[T12:.*]],a2,0x18 3330; MIPS32: srl [[T2]],[[T2]],0x18 3331; MIPS32: sll [[T12]],[[T12]],0x18 3332; MIPS32: sll [[T2]],[[T2]],0x18 3333; MIPS32: slt [[T2]],[[T2]],[[T12]] 3334; MIPS32: sll [[T2]],[[T2]],0x18 3335; MIPS32: sll [[T11]],[[T11]],0x8 3336; MIPS32: srl [[T11]],[[T11]],0x8 3337; MIPS32: or [[T2]],[[T2]],[[T11]] 3338; MIPS32: move [[T10]],a3 3339; MIPS32: andi [[T10]],[[T10]],0xff 3340; MIPS32: move [[T11]],[[T3]] 3341; MIPS32: andi [[T11]],[[T11]],0xff 3342; MIPS32: sll [[T10]],[[T10]],0x18 3343; MIPS32: sll [[T11]],[[T11]],0x18 3344; MIPS32: slt [[T11]],[[T11]],[[T10]] 3345; MIPS32: andi [[T11]],[[T11]],0xff 3346; MIPS32: srl [[T7]],[[T7]],0x8 3347; MIPS32: sll [[T7]],[[T7]],0x8 3348; MIPS32: or [[T11]],[[T11]],[[T7]] 3349; MIPS32: move [[T10]],a3 3350; MIPS32: srl [[T10]],[[T10]],0x8 3351; MIPS32: andi [[T10]],[[T10]],0xff 3352; MIPS32: move [[T12]],[[T3]] 3353; MIPS32: srl [[T12]],[[T12]],0x8 3354; MIPS32: andi [[T12]],[[T12]],0xff 3355; MIPS32: sll [[T10]],[[T10]],0x18 3356; MIPS32: sll [[T12]],[[T12]],0x18 3357; MIPS32: slt [[T12]],[[T12]],[[T10]] 3358; MIPS32: andi [[T12]],[[T12]],0xff 3359; MIPS32: sll [[T12]],[[T12]],0x8 3360; MIPS32: lui [[T10]],0xffff 3361; MIPS32: ori [[T10]],[[T10]],0xff 3362; MIPS32: and [[T11]],[[T11]],[[T10]] 3363; MIPS32: or [[T12]],[[T12]],[[T11]] 3364; MIPS32: move [[T10]],a3 3365; MIPS32: srl [[T10]],[[T10]],0x10 3366; MIPS32: andi [[T10]],[[T10]],0xff 3367; MIPS32: move [[T11]],[[T3]] 3368; MIPS32: srl [[T11]],[[T11]],0x10 3369; MIPS32: andi [[T11]],[[T11]],0xff 3370; MIPS32: sll [[T10]],[[T10]],0x18 3371; MIPS32: sll [[T11]],[[T11]],0x18 3372; MIPS32: slt [[T11]],[[T11]],[[T10]] 3373; MIPS32: andi [[T11]],[[T11]],0xff 3374; MIPS32: sll [[T11]],[[T11]],0x10 3375; MIPS32: lui [[T10]],0xff00 3376; MIPS32: ori [[T10]],[[T10]],0xffff 3377; MIPS32: and [[T12]],[[T12]],[[T10]] 3378; MIPS32: or [[T11]],[[T11]],[[T12]] 3379; MIPS32: srl [[T13:.*]],a3,0x18 3380; MIPS32: srl [[T3]],[[T3]],0x18 3381; MIPS32: sll [[T13]],[[T13]],0x18 3382; MIPS32: sll [[T3]],[[T3]],0x18 3383; MIPS32: slt [[T3]],[[T3]],[[T13]] 3384; MIPS32: sll [[T3]],[[T3]],0x18 3385; MIPS32: sll [[T11]],[[T11]],0x8 3386; MIPS32: srl [[T11]],[[T11]],0x8 3387; MIPS32: or [[T3]],[[T3]],[[T11]] 3388; MIPS32: move a0,[[T2]] 3389; MIPS32: move a1,[[T3]] 3390} 3391 3392define internal <16 x i1> @test_icmp_v16i8_sle(<16 x i8> %a, <16 x i8> %b) { 3393entry: 3394 %res = icmp sle <16 x i8> %a, %b 3395 ret <16 x i1> %res 3396; CHECK-LABEL: test_icmp_v16i8_sle 3397; CHECK: pcmpgtb 3398; CHECK: pxor 3399 3400; MIPS32-LABEL: test_icmp_v16i8_sle 3401; MIPS32: lw [[T0:.*]], 3402; MIPS32: lw [[T1:.*]], 3403; MIPS32: lw [[T2:.*]], 3404; MIPS32: lw [[T3:.*]], 3405; MIPS32: move [[T4:.*]],zero 3406; MIPS32: move [[T5:.*]],zero 3407; MIPS32: move [[T6:.*]],zero 3408; MIPS32: move [[T7:.*]],zero 3409; MIPS32: move [[T8:.*]],a0 3410; MIPS32: andi [[T8]],[[T8]],0xff 3411; MIPS32: move [[T9:.*]],[[T0]] 3412; MIPS32: andi [[T9]],[[T9]],0xff 3413; MIPS32: sll [[T8]],[[T8]],0x18 3414; MIPS32: sll [[T9]],[[T9]],0x18 3415; MIPS32: slt [[T9]],[[T9]],[[T8]] 3416; MIPS32: xori [[T9]],[[T9]],0x1 3417; MIPS32: andi [[T9]],[[T9]],0xff 3418; MIPS32: srl [[T4]],[[T4]],0x8 3419; MIPS32: sll [[T4]],[[T4]],0x8 3420; MIPS32: or [[T9]],[[T9]],[[T4]] 3421; MIPS32: move [[T4]],a0 3422; MIPS32: srl [[T4]],[[T4]],0x8 3423; MIPS32: andi [[T4]],[[T4]],0xff 3424; MIPS32: move [[T8]],[[T0]] 3425; MIPS32: srl [[T8]],[[T8]],0x8 3426; MIPS32: andi [[T8]],[[T8]],0xff 3427; MIPS32: sll [[T4]],[[T4]],0x18 3428; MIPS32: sll [[T8]],[[T8]],0x18 3429; MIPS32: slt [[T8]],[[T8]],[[T4]] 3430; MIPS32: xori [[T8]],[[T8]],0x1 3431; MIPS32: andi [[T8]],[[T8]],0xff 3432; MIPS32: sll [[T8]],[[T8]],0x8 3433; MIPS32: lui [[T4]],0xffff 3434; MIPS32: ori [[T4]],[[T4]],0xff 3435; MIPS32: and [[T9]],[[T9]],[[T4]] 3436; MIPS32: or [[T8]],[[T8]],[[T9]] 3437; MIPS32: move [[T4]],a0 3438; MIPS32: srl [[T4]],[[T4]],0x10 3439; MIPS32: andi [[T4]],[[T4]],0xff 3440; MIPS32: move [[T9]],[[T0]] 3441; MIPS32: srl [[T9]],[[T9]],0x10 3442; MIPS32: andi [[T9]],[[T9]],0xff 3443; MIPS32: sll [[T4]],[[T4]],0x18 3444; MIPS32: sll [[T9]],[[T9]],0x18 3445; MIPS32: slt [[T9]],[[T9]],[[T4]] 3446; MIPS32: xori [[T9]],[[T9]],0x1 3447; MIPS32: andi [[T9]],[[T9]],0xff 3448; MIPS32: sll [[T9]],[[T9]],0x10 3449; MIPS32: lui [[T4]],0xff00 3450; MIPS32: ori [[T4]],[[T4]],0xffff 3451; MIPS32: and [[T8]],[[T8]],[[T4]] 3452; MIPS32: or [[T9]],[[T9]],[[T8]] 3453; MIPS32: srl [[T10:.*]],a0,0x18 3454; MIPS32: srl [[T0]],[[T0]],0x18 3455; MIPS32: sll [[T10]],[[T10]],0x18 3456; MIPS32: sll [[T0]],[[T0]],0x18 3457; MIPS32: slt [[T0]],[[T0]],[[T10]] 3458; MIPS32: xori [[T0]],[[T0]],0x1 3459; MIPS32: sll [[T0]],[[T0]],0x18 3460; MIPS32: sll [[T9]],[[T9]],0x8 3461; MIPS32: srl [[T9]],[[T9]],0x8 3462; MIPS32: or v0,[[T0]],[[T9]] 3463; MIPS32: move [[T10]],a1 3464; MIPS32: andi [[T10]],[[T10]],0xff 3465; MIPS32: move [[T4]],[[T1]] 3466; MIPS32: andi [[T4]],[[T4]],0xff 3467; MIPS32: sll [[T10]],[[T10]],0x18 3468; MIPS32: sll [[T4]],[[T4]],0x18 3469; MIPS32: slt [[T4]],[[T4]],[[T10]] 3470; MIPS32: xori [[T4]],[[T4]],0x1 3471; MIPS32: andi [[T4]],[[T4]],0xff 3472; MIPS32: srl [[T5]],[[T5]],0x8 3473; MIPS32: sll [[T5]],[[T5]],0x8 3474; MIPS32: or [[T4]],[[T4]],[[T5]] 3475; MIPS32: move [[T10]],a1 3476; MIPS32: srl [[T10]],[[T10]],0x8 3477; MIPS32: andi [[T10]],[[T10]],0xff 3478; MIPS32: move [[T5]],[[T1]] 3479; MIPS32: srl [[T5]],[[T5]],0x8 3480; MIPS32: andi [[T5]],[[T5]],0xff 3481; MIPS32: sll [[T10]],[[T10]],0x18 3482; MIPS32: sll [[T5]],[[T5]],0x18 3483; MIPS32: slt [[T5]],[[T5]],[[T10]] 3484; MIPS32: xori [[T5]],[[T5]],0x1 3485; MIPS32: andi [[T5]],[[T5]],0xff 3486; MIPS32: sll [[T5]],[[T5]],0x8 3487; MIPS32: lui [[T10]],0xffff 3488; MIPS32: ori [[T10]],[[T10]],0xff 3489; MIPS32: and [[T4]],[[T4]],[[T10]] 3490; MIPS32: or [[T5]],[[T5]],[[T4]] 3491; MIPS32: move [[T10]],a1 3492; MIPS32: srl [[T10]],[[T10]],0x10 3493; MIPS32: andi [[T10]],[[T10]],0xff 3494; MIPS32: move [[T4]],[[T1]] 3495; MIPS32: srl [[T4]],[[T4]],0x10 3496; MIPS32: andi [[T4]],[[T4]],0xff 3497; MIPS32: sll [[T10]],[[T10]],0x18 3498; MIPS32: sll [[T4]],[[T4]],0x18 3499; MIPS32: slt [[T4]],[[T4]],[[T10]] 3500; MIPS32: xori [[T4]],[[T4]],0x1 3501; MIPS32: andi [[T4]],[[T4]],0xff 3502; MIPS32: sll [[T4]],[[T4]],0x10 3503; MIPS32: lui [[T10]],0xff00 3504; MIPS32: ori [[T10]],[[T10]],0xffff 3505; MIPS32: and [[T5]],[[T5]],[[T10]] 3506; MIPS32: or [[T4]],[[T4]],[[T5]] 3507; MIPS32: srl [[T11:.*]],a1,0x18 3508; MIPS32: srl [[T1]],[[T1]],0x18 3509; MIPS32: sll [[T11]],[[T11]],0x18 3510; MIPS32: sll [[T1]],[[T1]],0x18 3511; MIPS32: slt [[T1]],[[T1]],[[T11]] 3512; MIPS32: xori [[T1]],[[T1]],0x1 3513; MIPS32: sll [[T1]],[[T1]],0x18 3514; MIPS32: sll [[T4]],[[T4]],0x8 3515; MIPS32: srl [[T4]],[[T4]],0x8 3516; MIPS32: or v1,[[T1]],[[T4]] 3517; MIPS32: move [[T10]],a2 3518; MIPS32: andi [[T10]],[[T10]],0xff 3519; MIPS32: move [[T11]],[[T2]] 3520; MIPS32: andi [[T11]],[[T11]],0xff 3521; MIPS32: sll [[T10]],[[T10]],0x18 3522; MIPS32: sll [[T11]],[[T11]],0x18 3523; MIPS32: slt [[T11]],[[T11]],[[T10]] 3524; MIPS32: xori [[T11]],[[T11]],0x1 3525; MIPS32: andi [[T11]],[[T11]],0xff 3526; MIPS32: srl [[T6]],[[T6]],0x8 3527; MIPS32: sll [[T6]],[[T6]],0x8 3528; MIPS32: or [[T11]],[[T11]],[[T6]] 3529; MIPS32: move [[T10]],a2 3530; MIPS32: srl [[T10]],[[T10]],0x8 3531; MIPS32: andi [[T10]],[[T10]],0xff 3532; MIPS32: move [[T4]],[[T2]] 3533; MIPS32: srl [[T4]],[[T4]],0x8 3534; MIPS32: andi [[T4]],[[T4]],0xff 3535; MIPS32: sll [[T10]],[[T10]],0x18 3536; MIPS32: sll [[T4]],[[T4]],0x18 3537; MIPS32: slt [[T4]],[[T4]],[[T10]] 3538; MIPS32: xori [[T4]],[[T4]],0x1 3539; MIPS32: andi [[T4]],[[T4]],0xff 3540; MIPS32: sll [[T4]],[[T4]],0x8 3541; MIPS32: lui [[T10]],0xffff 3542; MIPS32: ori [[T10]],[[T10]],0xff 3543; MIPS32: and [[T11]],[[T11]],[[T10]] 3544; MIPS32: or [[T4]],[[T4]],[[T11]] 3545; MIPS32: move [[T10]],a2 3546; MIPS32: srl [[T10]],[[T10]],0x10 3547; MIPS32: andi [[T10]],[[T10]],0xff 3548; MIPS32: move [[T11]],[[T2]] 3549; MIPS32: srl [[T11]],[[T11]],0x10 3550; MIPS32: andi [[T11]],[[T11]],0xff 3551; MIPS32: sll [[T10]],[[T10]],0x18 3552; MIPS32: sll [[T11]],[[T11]],0x18 3553; MIPS32: slt [[T11]],[[T11]],[[T10]] 3554; MIPS32: xori [[T11]],[[T11]],0x1 3555; MIPS32: andi [[T11]],[[T11]],0xff 3556; MIPS32: sll [[T11]],[[T11]],0x10 3557; MIPS32: lui [[T10]],0xff00 3558; MIPS32: ori [[T10]],[[T10]],0xffff 3559; MIPS32: and [[T4]],[[T4]],[[T10]] 3560; MIPS32: or [[T11]],[[T11]],[[T4]] 3561; MIPS32: srl [[T12:.*]],a2,0x18 3562; MIPS32: srl [[T2]],[[T2]],0x18 3563; MIPS32: sll [[T12]],[[T12]],0x18 3564; MIPS32: sll [[T2]],[[T2]],0x18 3565; MIPS32: slt [[T2]],[[T2]],[[T12]] 3566; MIPS32: xori [[T2]],[[T2]],0x1 3567; MIPS32: sll [[T2]],[[T2]],0x18 3568; MIPS32: sll [[T11]],[[T11]],0x8 3569; MIPS32: srl [[T11]],[[T11]],0x8 3570; MIPS32: or [[T2]],[[T2]],[[T11]] 3571; MIPS32: move [[T10]],a3 3572; MIPS32: andi [[T10]],[[T10]],0xff 3573; MIPS32: move [[T11]],[[T3]] 3574; MIPS32: andi [[T11]],[[T11]],0xff 3575; MIPS32: sll [[T10]],[[T10]],0x18 3576; MIPS32: sll [[T11]],[[T11]],0x18 3577; MIPS32: slt [[T11]],[[T11]],[[T10]] 3578; MIPS32: xori [[T11]],[[T11]],0x1 3579; MIPS32: andi [[T11]],[[T11]],0xff 3580; MIPS32: srl [[T7]],[[T7]],0x8 3581; MIPS32: sll [[T7]],[[T7]],0x8 3582; MIPS32: or [[T11]],[[T11]],[[T7]] 3583; MIPS32: move [[T10]],a3 3584; MIPS32: srl [[T10]],[[T10]],0x8 3585; MIPS32: andi [[T10]],[[T10]],0xff 3586; MIPS32: move [[T12]],[[T3]] 3587; MIPS32: srl [[T12]],[[T12]],0x8 3588; MIPS32: andi [[T12]],[[T12]],0xff 3589; MIPS32: sll [[T10]],[[T10]],0x18 3590; MIPS32: sll [[T12]],[[T12]],0x18 3591; MIPS32: slt [[T12]],[[T12]],[[T10]] 3592; MIPS32: xori [[T12]],[[T12]],0x1 3593; MIPS32: andi [[T12]],[[T12]],0xff 3594; MIPS32: sll [[T12]],[[T12]],0x8 3595; MIPS32: lui [[T10]],0xffff 3596; MIPS32: ori [[T10]],[[T10]],0xff 3597; MIPS32: and [[T11]],[[T11]],[[T10]] 3598; MIPS32: or [[T12]],[[T12]],[[T11]] 3599; MIPS32: move [[T10]],a3 3600; MIPS32: srl [[T10]],[[T10]],0x10 3601; MIPS32: andi [[T10]],[[T10]],0xff 3602; MIPS32: move [[T11]],[[T3]] 3603; MIPS32: srl [[T11]],[[T11]],0x10 3604; MIPS32: andi [[T11]],[[T11]],0xff 3605; MIPS32: sll [[T10]],[[T10]],0x18 3606; MIPS32: sll [[T11]],[[T11]],0x18 3607; MIPS32: slt [[T11]],[[T11]],[[T10]] 3608; MIPS32: xori [[T11]],[[T11]],0x1 3609; MIPS32: andi [[T11]],[[T11]],0xff 3610; MIPS32: sll [[T11]],[[T11]],0x10 3611; MIPS32: lui [[T10]],0xff00 3612; MIPS32: ori [[T10]],[[T10]],0xffff 3613; MIPS32: and [[T12]],[[T12]],[[T10]] 3614; MIPS32: or [[T11]],[[T11]],[[T12]] 3615; MIPS32: srl [[T13:.*]],a3,0x18 3616; MIPS32: srl [[T3]],[[T3]],0x18 3617; MIPS32: sll [[T13]],[[T13]],0x18 3618; MIPS32: sll [[T3]],[[T3]],0x18 3619; MIPS32: slt [[T3]],[[T3]],[[T13]] 3620; MIPS32: xori [[T3]],[[T3]],0x1 3621; MIPS32: sll [[T3]],[[T3]],0x18 3622; MIPS32: sll [[T11]],[[T11]],0x8 3623; MIPS32: srl [[T11]],[[T11]],0x8 3624; MIPS32: or [[T3]],[[T3]],[[T11]] 3625; MIPS32: move a0,[[T2]] 3626; MIPS32: move a1,[[T3]] 3627} 3628 3629define internal <16 x i1> @test_icmp_v16i8_slt(<16 x i8> %a, <16 x i8> %b) { 3630entry: 3631 %res = icmp slt <16 x i8> %a, %b 3632 ret <16 x i1> %res 3633; CHECK-LABEL: test_icmp_v16i8_slt 3634; CHECK: pcmpgtb 3635 3636; MIPS32-LABEL: test_icmp_v16i8_slt 3637; MIPS32: lw [[T0:.*]], 3638; MIPS32: lw [[T1:.*]], 3639; MIPS32: lw [[T2:.*]], 3640; MIPS32: lw [[T3:.*]], 3641; MIPS32: move [[T4:.*]],zero 3642; MIPS32: move [[T5:.*]],zero 3643; MIPS32: move [[T6:.*]],zero 3644; MIPS32: move [[T7:.*]],zero 3645; MIPS32: move [[T8:.*]],a0 3646; MIPS32: andi [[T8]],[[T8]],0xff 3647; MIPS32: move [[T9:.*]],[[T0]] 3648; MIPS32: andi [[T9]],[[T9]],0xff 3649; MIPS32: sll [[T8]],[[T8]],0x18 3650; MIPS32: sll [[T9]],[[T9]],0x18 3651; MIPS32: slt [[T8]],[[T8]],[[T9]] 3652; MIPS32: andi [[T8]],[[T8]],0xff 3653; MIPS32: srl [[T4]],[[T4]],0x8 3654; MIPS32: sll [[T4]],[[T4]],0x8 3655; MIPS32: or [[T8]],[[T8]],[[T4]] 3656; MIPS32: move [[T4]],a0 3657; MIPS32: srl [[T4]],[[T4]],0x8 3658; MIPS32: andi [[T4]],[[T4]],0xff 3659; MIPS32: move [[T9]],[[T0]] 3660; MIPS32: srl [[T9]],[[T9]],0x8 3661; MIPS32: andi [[T9]],[[T9]],0xff 3662; MIPS32: sll [[T4]],[[T4]],0x18 3663; MIPS32: sll [[T9]],[[T9]],0x18 3664; MIPS32: slt [[T4]],[[T4]],[[T9]] 3665; MIPS32: andi [[T4]],[[T4]],0xff 3666; MIPS32: sll [[T4]],[[T4]],0x8 3667; MIPS32: lui [[T9]],0xffff 3668; MIPS32: ori [[T9]],[[T9]],0xff 3669; MIPS32: and [[T8]],[[T8]],[[T9]] 3670; MIPS32: or [[T4]],[[T4]],[[T8]] 3671; MIPS32: move [[T8]],a0 3672; MIPS32: srl [[T8]],[[T8]],0x10 3673; MIPS32: andi [[T8]],[[T8]],0xff 3674; MIPS32: move [[T9]],[[T0]] 3675; MIPS32: srl [[T9]],[[T9]],0x10 3676; MIPS32: andi [[T9]],[[T9]],0xff 3677; MIPS32: sll [[T8]],[[T8]],0x18 3678; MIPS32: sll [[T9]],[[T9]],0x18 3679; MIPS32: slt [[T8]],[[T8]],[[T9]] 3680; MIPS32: andi [[T8]],[[T8]],0xff 3681; MIPS32: sll [[T8]],[[T8]],0x10 3682; MIPS32: lui [[T9]],0xff00 3683; MIPS32: ori [[T9]],[[T9]],0xffff 3684; MIPS32: and [[T4]],[[T4]],[[T9]] 3685; MIPS32: or [[T8]],[[T8]],[[T4]] 3686; MIPS32: srl [[T10:.*]],a0,0x18 3687; MIPS32: srl [[T0]],[[T0]],0x18 3688; MIPS32: sll [[T10]],[[T10]],0x18 3689; MIPS32: sll [[T0]],[[T0]],0x18 3690; MIPS32: slt [[T10]],[[T10]],[[T0]] 3691; MIPS32: sll [[T10]],[[T10]],0x18 3692; MIPS32: sll [[T8]],[[T8]],0x8 3693; MIPS32: srl [[T8]],[[T8]],0x8 3694; MIPS32: or [[T10]],[[T10]],[[T8]] 3695; MIPS32: move [[T0]],a1 3696; MIPS32: andi [[T0]],[[T0]],0xff 3697; MIPS32: move [[T4]],[[T1]] 3698; MIPS32: andi [[T4]],[[T4]],0xff 3699; MIPS32: sll [[T0]],[[T0]],0x18 3700; MIPS32: sll [[T4]],[[T4]],0x18 3701; MIPS32: slt [[T0]],[[T0]],[[T4]] 3702; MIPS32: andi [[T0]],[[T0]],0xff 3703; MIPS32: srl [[T5]],[[T5]],0x8 3704; MIPS32: sll [[T5]],[[T5]],0x8 3705; MIPS32: or [[T0]],[[T0]],[[T5]] 3706; MIPS32: move [[T4]],a1 3707; MIPS32: srl [[T4]],[[T4]],0x8 3708; MIPS32: andi [[T4]],[[T4]],0xff 3709; MIPS32: move [[T5]],[[T1]] 3710; MIPS32: srl [[T5]],[[T5]],0x8 3711; MIPS32: andi [[T5]],[[T5]],0xff 3712; MIPS32: sll [[T4]],[[T4]],0x18 3713; MIPS32: sll [[T5]],[[T5]],0x18 3714; MIPS32: slt [[T4]],[[T4]],[[T5]] 3715; MIPS32: andi [[T4]],[[T4]],0xff 3716; MIPS32: sll [[T4]],[[T4]],0x8 3717; MIPS32: lui [[T5]],0xffff 3718; MIPS32: ori [[T5]],[[T5]],0xff 3719; MIPS32: and [[T0]],[[T0]],[[T5]] 3720; MIPS32: or [[T4]],[[T4]],[[T0]] 3721; MIPS32: move [[T0]],a1 3722; MIPS32: srl [[T0]],[[T0]],0x10 3723; MIPS32: andi [[T0]],[[T0]],0xff 3724; MIPS32: move [[T5]],[[T1]] 3725; MIPS32: srl [[T5]],[[T5]],0x10 3726; MIPS32: andi [[T5]],[[T5]],0xff 3727; MIPS32: sll [[T0]],[[T0]],0x18 3728; MIPS32: sll [[T5]],[[T5]],0x18 3729; MIPS32: slt [[T0]],[[T0]],[[T5]] 3730; MIPS32: andi [[T0]],[[T0]],0xff 3731; MIPS32: sll [[T0]],[[T0]],0x10 3732; MIPS32: lui [[T5]],0xff00 3733; MIPS32: ori [[T5]],[[T5]],0xffff 3734; MIPS32: and [[T4]],[[T4]],[[T5]] 3735; MIPS32: or [[T0]],[[T0]],[[T4]] 3736; MIPS32: srl [[T11:.*]],a1,0x18 3737; MIPS32: srl [[T1]],[[T1]],0x18 3738; MIPS32: sll [[T11]],[[T11]],0x18 3739; MIPS32: sll [[T1]],[[T1]],0x18 3740; MIPS32: slt [[T11]],[[T11]],[[T1]] 3741; MIPS32: sll [[T11]],[[T11]],0x18 3742; MIPS32: sll [[T0]],[[T0]],0x8 3743; MIPS32: srl [[T0]],[[T0]],0x8 3744; MIPS32: or [[T11]],[[T11]],[[T0]] 3745; MIPS32: move [[T0]],a2 3746; MIPS32: andi [[T0]],[[T0]],0xff 3747; MIPS32: move [[T1]],[[T2]] 3748; MIPS32: andi [[T1]],[[T1]],0xff 3749; MIPS32: sll [[T0]],[[T0]],0x18 3750; MIPS32: sll [[T1]],[[T1]],0x18 3751; MIPS32: slt [[T0]],[[T0]],[[T1]] 3752; MIPS32: andi [[T0]],[[T0]],0xff 3753; MIPS32: srl [[T6]],[[T6]],0x8 3754; MIPS32: sll [[T6]],[[T6]],0x8 3755; MIPS32: or [[T0]],[[T0]],[[T6]] 3756; MIPS32: move [[T1]],a2 3757; MIPS32: srl [[T1]],[[T1]],0x8 3758; MIPS32: andi [[T1]],[[T1]],0xff 3759; MIPS32: move [[T4]],[[T2]] 3760; MIPS32: srl [[T4]],[[T4]],0x8 3761; MIPS32: andi [[T4]],[[T4]],0xff 3762; MIPS32: sll [[T1]],[[T1]],0x18 3763; MIPS32: sll [[T4]],[[T4]],0x18 3764; MIPS32: slt [[T1]],[[T1]],[[T4]] 3765; MIPS32: andi [[T1]],[[T1]],0xff 3766; MIPS32: sll [[T1]],[[T1]],0x8 3767; MIPS32: lui [[T4]],0xffff 3768; MIPS32: ori [[T4]],[[T4]],0xff 3769; MIPS32: and [[T0]],[[T0]],[[T4]] 3770; MIPS32: or [[T1]],[[T1]],[[T0]] 3771; MIPS32: move [[T0]],a2 3772; MIPS32: srl [[T0]],[[T0]],0x10 3773; MIPS32: andi [[T0]],[[T0]],0xff 3774; MIPS32: move [[T4]],[[T2]] 3775; MIPS32: srl [[T4]],[[T4]],0x10 3776; MIPS32: andi [[T4]],[[T4]],0xff 3777; MIPS32: sll [[T0]],[[T0]],0x18 3778; MIPS32: sll [[T4]],[[T4]],0x18 3779; MIPS32: slt [[T0]],[[T0]],[[T4]] 3780; MIPS32: andi [[T0]],[[T0]],0xff 3781; MIPS32: sll [[T0]],[[T0]],0x10 3782; MIPS32: lui [[T4]],0xff00 3783; MIPS32: ori [[T4]],[[T4]],0xffff 3784; MIPS32: and [[T1]],[[T1]],[[T4]] 3785; MIPS32: or [[T0]],[[T0]],[[T1]] 3786; MIPS32: srl [[T12:.*]],a2,0x18 3787; MIPS32: srl [[T2]],[[T2]],0x18 3788; MIPS32: sll [[T12]],[[T12]],0x18 3789; MIPS32: sll [[T2]],[[T2]],0x18 3790; MIPS32: slt [[T12]],[[T12]],[[T2]] 3791; MIPS32: sll [[T12]],[[T12]],0x18 3792; MIPS32: sll [[T0]],[[T0]],0x8 3793; MIPS32: srl [[T0]],[[T0]],0x8 3794; MIPS32: or [[T12]],[[T12]],[[T0]] 3795; MIPS32: move [[T0]],a3 3796; MIPS32: andi [[T0]],[[T0]],0xff 3797; MIPS32: move [[T1]],[[T3]] 3798; MIPS32: andi [[T1]],[[T1]],0xff 3799; MIPS32: sll [[T0]],[[T0]],0x18 3800; MIPS32: sll [[T1]],[[T1]],0x18 3801; MIPS32: slt [[T0]],[[T0]],[[T1]] 3802; MIPS32: andi [[T0]],[[T0]],0xff 3803; MIPS32: srl [[T7]],[[T7]],0x8 3804; MIPS32: sll [[T7]],[[T7]],0x8 3805; MIPS32: or [[T0]],[[T0]],[[T7]] 3806; MIPS32: move [[T1]],a3 3807; MIPS32: srl [[T1]],[[T1]],0x8 3808; MIPS32: andi [[T1]],[[T1]],0xff 3809; MIPS32: move [[T2]],[[T3]] 3810; MIPS32: srl [[T2]],[[T2]],0x8 3811; MIPS32: andi [[T2]],[[T2]],0xff 3812; MIPS32: sll [[T1]],[[T1]],0x18 3813; MIPS32: sll [[T2]],[[T2]],0x18 3814; MIPS32: slt [[T1]],[[T1]],[[T2]] 3815; MIPS32: andi [[T1]],[[T1]],0xff 3816; MIPS32: sll [[T1]],[[T1]],0x8 3817; MIPS32: lui [[T2]],0xffff 3818; MIPS32: ori [[T2]],[[T2]],0xff 3819; MIPS32: and [[T0]],[[T0]],[[T2]] 3820; MIPS32: or [[T1]],[[T1]],[[T0]] 3821; MIPS32: move [[T0]],a3 3822; MIPS32: srl [[T0]],[[T0]],0x10 3823; MIPS32: andi [[T0]],[[T0]],0xff 3824; MIPS32: move [[T2]],[[T3]] 3825; MIPS32: srl [[T2]],[[T2]],0x10 3826; MIPS32: andi [[T2]],[[T2]],0xff 3827; MIPS32: sll [[T0]],[[T0]],0x18 3828; MIPS32: sll [[T2]],[[T2]],0x18 3829; MIPS32: slt [[T0]],[[T0]],[[T2]] 3830; MIPS32: andi [[T0]],[[T0]],0xff 3831; MIPS32: sll [[T0]],[[T0]],0x10 3832; MIPS32: lui [[T2]],0xff00 3833; MIPS32: ori [[T2]],[[T2]],0xffff 3834; MIPS32: and [[T1]],[[T1]],[[T2]] 3835; MIPS32: or [[T0]],[[T0]],[[T1]] 3836; MIPS32: srl [[T13:.*]],a3,0x18 3837; MIPS32: srl [[T3]],[[T3]],0x18 3838; MIPS32: sll [[T13]],[[T13]],0x18 3839; MIPS32: sll [[T3]],[[T3]],0x18 3840; MIPS32: slt [[T13]],[[T13]],[[T3]] 3841; MIPS32: sll [[T13]],[[T13]],0x18 3842; MIPS32: sll [[T0]],[[T0]],0x8 3843; MIPS32: srl [[T0]],[[T0]],0x8 3844; MIPS32: or [[T13]],[[T13]],[[T0]] 3845; MIPS32: move v0,[[T10]] 3846; MIPS32: move v1,[[T11]] 3847; MIPS32: move a0,[[T12]] 3848; MIPS32: move a1,[[T13]] 3849} 3850 3851define internal <16 x i1> @test_icmp_v16i8_uge(<16 x i8> %a, <16 x i8> %b) { 3852entry: 3853 %res = icmp uge <16 x i8> %a, %b 3854 ret <16 x i1> %res 3855; CHECK-LABEL: test_icmp_v16i8_uge 3856; CHECK: pxor 3857; CHECK: pcmpgtb 3858; CHECK: pxor 3859 3860; MIPS32-LABEL: test_icmp_v16i8_uge 3861; MIPS32: lw [[T0:.*]], 3862; MIPS32: lw [[T1:.*]], 3863; MIPS32: lw [[T2:.*]], 3864; MIPS32: lw [[T3:.*]], 3865; MIPS32: move [[T4:.*]],zero 3866; MIPS32: move [[T5:.*]],zero 3867; MIPS32: move [[T6:.*]],zero 3868; MIPS32: move [[T7:.*]],zero 3869; MIPS32: move [[T8:.*]],a0 3870; MIPS32: andi [[T8]],[[T8]],0xff 3871; MIPS32: move [[T9:.*]],[[T0]] 3872; MIPS32: andi [[T9]],[[T9]],0xff 3873; MIPS32: sll [[T8]],[[T8]],0x18 3874; MIPS32: sll [[T9]],[[T9]],0x18 3875; MIPS32: sltu [[T8]],[[T8]],[[T9]] 3876; MIPS32: xori [[T8]],[[T8]],0x1 3877; MIPS32: andi [[T8]],[[T8]],0xff 3878; MIPS32: srl [[T4]],[[T4]],0x8 3879; MIPS32: sll [[T4]],[[T4]],0x8 3880; MIPS32: or [[T8]],[[T8]],[[T4]] 3881; MIPS32: move [[T4]],a0 3882; MIPS32: srl [[T4]],[[T4]],0x8 3883; MIPS32: andi [[T4]],[[T4]],0xff 3884; MIPS32: move [[T9]],[[T0]] 3885; MIPS32: srl [[T9]],[[T9]],0x8 3886; MIPS32: andi [[T9]],[[T9]],0xff 3887; MIPS32: sll [[T4]],[[T4]],0x18 3888; MIPS32: sll [[T9]],[[T9]],0x18 3889; MIPS32: sltu [[T4]],[[T4]],[[T9]] 3890; MIPS32: xori [[T4]],[[T4]],0x1 3891; MIPS32: andi [[T4]],[[T4]],0xff 3892; MIPS32: sll [[T4]],[[T4]],0x8 3893; MIPS32: lui [[T9]],0xffff 3894; MIPS32: ori [[T9]],[[T9]],0xff 3895; MIPS32: and [[T8]],[[T8]],[[T9]] 3896; MIPS32: or [[T4]],[[T4]],[[T8]] 3897; MIPS32: move [[T8]],a0 3898; MIPS32: srl [[T8]],[[T8]],0x10 3899; MIPS32: andi [[T8]],[[T8]],0xff 3900; MIPS32: move [[T9]],[[T0]] 3901; MIPS32: srl [[T9]],[[T9]],0x10 3902; MIPS32: andi [[T9]],[[T9]],0xff 3903; MIPS32: sll [[T8]],[[T8]],0x18 3904; MIPS32: sll [[T9]],[[T9]],0x18 3905; MIPS32: sltu [[T8]],[[T8]],[[T9]] 3906; MIPS32: xori [[T8]],[[T8]],0x1 3907; MIPS32: andi [[T8]],[[T8]],0xff 3908; MIPS32: sll [[T8]],[[T8]],0x10 3909; MIPS32: lui [[T9]],0xff00 3910; MIPS32: ori [[T9]],[[T9]],0xffff 3911; MIPS32: and [[T4]],[[T4]],[[T9]] 3912; MIPS32: or [[T8]],[[T8]],[[T4]] 3913; MIPS32: srl [[T10:.*]],a0,0x18 3914; MIPS32: srl [[T0]],[[T0]],0x18 3915; MIPS32: sll [[T10]],[[T10]],0x18 3916; MIPS32: sll [[T0]],[[T0]],0x18 3917; MIPS32: sltu [[T10]],[[T10]],[[T0]] 3918; MIPS32: xori [[T10]],[[T10]],0x1 3919; MIPS32: sll [[T10]],[[T10]],0x18 3920; MIPS32: sll [[T8]],[[T8]],0x8 3921; MIPS32: srl [[T8]],[[T8]],0x8 3922; MIPS32: or [[T10]],[[T10]],[[T8]] 3923; MIPS32: move [[T0]],a1 3924; MIPS32: andi [[T0]],[[T0]],0xff 3925; MIPS32: move [[T4]],[[T1]] 3926; MIPS32: andi [[T4]],[[T4]],0xff 3927; MIPS32: sll [[T0]],[[T0]],0x18 3928; MIPS32: sll [[T4]],[[T4]],0x18 3929; MIPS32: sltu [[T0]],[[T0]],[[T4]] 3930; MIPS32: xori [[T0]],[[T0]],0x1 3931; MIPS32: andi [[T0]],[[T0]],0xff 3932; MIPS32: srl [[T5]],[[T5]],0x8 3933; MIPS32: sll [[T5]],[[T5]],0x8 3934; MIPS32: or [[T0]],[[T0]],[[T5]] 3935; MIPS32: move [[T4]],a1 3936; MIPS32: srl [[T4]],[[T4]],0x8 3937; MIPS32: andi [[T4]],[[T4]],0xff 3938; MIPS32: move [[T5]],[[T1]] 3939; MIPS32: srl [[T5]],[[T5]],0x8 3940; MIPS32: andi [[T5]],[[T5]],0xff 3941; MIPS32: sll [[T4]],[[T4]],0x18 3942; MIPS32: sll [[T5]],[[T5]],0x18 3943; MIPS32: sltu [[T4]],[[T4]],[[T5]] 3944; MIPS32: xori [[T4]],[[T4]],0x1 3945; MIPS32: andi [[T4]],[[T4]],0xff 3946; MIPS32: sll [[T4]],[[T4]],0x8 3947; MIPS32: lui [[T5]],0xffff 3948; MIPS32: ori [[T5]],[[T5]],0xff 3949; MIPS32: and [[T0]],[[T0]],[[T5]] 3950; MIPS32: or [[T4]],[[T4]],[[T0]] 3951; MIPS32: move [[T0]],a1 3952; MIPS32: srl [[T0]],[[T0]],0x10 3953; MIPS32: andi [[T0]],[[T0]],0xff 3954; MIPS32: move [[T5]],[[T1]] 3955; MIPS32: srl [[T5]],[[T5]],0x10 3956; MIPS32: andi [[T5]],[[T5]],0xff 3957; MIPS32: sll [[T0]],[[T0]],0x18 3958; MIPS32: sll [[T5]],[[T5]],0x18 3959; MIPS32: sltu [[T0]],[[T0]],[[T5]] 3960; MIPS32: xori [[T0]],[[T0]],0x1 3961; MIPS32: andi [[T0]],[[T0]],0xff 3962; MIPS32: sll [[T0]],[[T0]],0x10 3963; MIPS32: lui [[T5]],0xff00 3964; MIPS32: ori [[T5]],[[T5]],0xffff 3965; MIPS32: and [[T4]],[[T4]],[[T5]] 3966; MIPS32: or [[T0]],[[T0]],[[T4]] 3967; MIPS32: srl [[T11:.*]],a1,0x18 3968; MIPS32: srl [[T1]],[[T1]],0x18 3969; MIPS32: sll [[T11]],[[T11]],0x18 3970; MIPS32: sll [[T1]],[[T1]],0x18 3971; MIPS32: sltu [[T11]],[[T11]],[[T1]] 3972; MIPS32: xori [[T11]],[[T11]],0x1 3973; MIPS32: sll [[T11]],[[T11]],0x18 3974; MIPS32: sll [[T0]],[[T0]],0x8 3975; MIPS32: srl [[T0]],[[T0]],0x8 3976; MIPS32: or [[T11]],[[T11]],[[T0]] 3977; MIPS32: move [[T0]],a2 3978; MIPS32: andi [[T0]],[[T0]],0xff 3979; MIPS32: move [[T1]],[[T2]] 3980; MIPS32: andi [[T1]],[[T1]],0xff 3981; MIPS32: sll [[T0]],[[T0]],0x18 3982; MIPS32: sll [[T1]],[[T1]],0x18 3983; MIPS32: sltu [[T0]],[[T0]],[[T1]] 3984; MIPS32: xori [[T0]],[[T0]],0x1 3985; MIPS32: andi [[T0]],[[T0]],0xff 3986; MIPS32: srl [[T6]],[[T6]],0x8 3987; MIPS32: sll [[T6]],[[T6]],0x8 3988; MIPS32: or [[T0]],[[T0]],[[T6]] 3989; MIPS32: move [[T1]],a2 3990; MIPS32: srl [[T1]],[[T1]],0x8 3991; MIPS32: andi [[T1]],[[T1]],0xff 3992; MIPS32: move [[T4]],[[T2]] 3993; MIPS32: srl [[T4]],[[T4]],0x8 3994; MIPS32: andi [[T4]],[[T4]],0xff 3995; MIPS32: sll [[T1]],[[T1]],0x18 3996; MIPS32: sll [[T4]],[[T4]],0x18 3997; MIPS32: sltu [[T1]],[[T1]],[[T4]] 3998; MIPS32: xori [[T1]],[[T1]],0x1 3999; MIPS32: andi [[T1]],[[T1]],0xff 4000; MIPS32: sll [[T1]],[[T1]],0x8 4001; MIPS32: lui [[T4]],0xffff 4002; MIPS32: ori [[T4]],[[T4]],0xff 4003; MIPS32: and [[T0]],[[T0]],[[T4]] 4004; MIPS32: or [[T1]],[[T1]],[[T0]] 4005; MIPS32: move [[T0]],a2 4006; MIPS32: srl [[T0]],[[T0]],0x10 4007; MIPS32: andi [[T0]],[[T0]],0xff 4008; MIPS32: move [[T4]],[[T2]] 4009; MIPS32: srl [[T4]],[[T4]],0x10 4010; MIPS32: andi [[T4]],[[T4]],0xff 4011; MIPS32: sll [[T0]],[[T0]],0x18 4012; MIPS32: sll [[T4]],[[T4]],0x18 4013; MIPS32: sltu [[T0]],[[T0]],[[T4]] 4014; MIPS32: xori [[T0]],[[T0]],0x1 4015; MIPS32: andi [[T0]],[[T0]],0xff 4016; MIPS32: sll [[T0]],[[T0]],0x10 4017; MIPS32: lui [[T4]],0xff00 4018; MIPS32: ori [[T4]],[[T4]],0xffff 4019; MIPS32: and [[T1]],[[T1]],[[T4]] 4020; MIPS32: or [[T0]],[[T0]],[[T1]] 4021; MIPS32: srl [[T12:.*]],a2,0x18 4022; MIPS32: srl [[T2]],[[T2]],0x18 4023; MIPS32: sll [[T12]],[[T12]],0x18 4024; MIPS32: sll [[T2]],[[T2]],0x18 4025; MIPS32: sltu [[T12]],[[T12]],[[T2]] 4026; MIPS32: xori [[T12]],[[T12]],0x1 4027; MIPS32: sll [[T12]],[[T12]],0x18 4028; MIPS32: sll [[T0]],[[T0]],0x8 4029; MIPS32: srl [[T0]],[[T0]],0x8 4030; MIPS32: or [[T12]],[[T12]],[[T0]] 4031; MIPS32: move [[T0]],a3 4032; MIPS32: andi [[T0]],[[T0]],0xff 4033; MIPS32: move [[T1]],[[T3]] 4034; MIPS32: andi [[T1]],[[T1]],0xff 4035; MIPS32: sll [[T0]],[[T0]],0x18 4036; MIPS32: sll [[T1]],[[T1]],0x18 4037; MIPS32: sltu [[T0]],[[T0]],[[T1]] 4038; MIPS32: xori [[T0]],[[T0]],0x1 4039; MIPS32: andi [[T0]],[[T0]],0xff 4040; MIPS32: srl [[T7]],[[T7]],0x8 4041; MIPS32: sll [[T7]],[[T7]],0x8 4042; MIPS32: or [[T0]],[[T0]],[[T7]] 4043; MIPS32: move [[T1]],a3 4044; MIPS32: srl [[T1]],[[T1]],0x8 4045; MIPS32: andi [[T1]],[[T1]],0xff 4046; MIPS32: move [[T2]],[[T3]] 4047; MIPS32: srl [[T2]],[[T2]],0x8 4048; MIPS32: andi [[T2]],[[T2]],0xff 4049; MIPS32: sll [[T1]],[[T1]],0x18 4050; MIPS32: sll [[T2]],[[T2]],0x18 4051; MIPS32: sltu [[T1]],[[T1]],[[T2]] 4052; MIPS32: xori [[T1]],[[T1]],0x1 4053; MIPS32: andi [[T1]],[[T1]],0xff 4054; MIPS32: sll [[T1]],[[T1]],0x8 4055; MIPS32: lui [[T2]],0xffff 4056; MIPS32: ori [[T2]],[[T2]],0xff 4057; MIPS32: and [[T0]],[[T0]],[[T2]] 4058; MIPS32: or [[T1]],[[T1]],[[T0]] 4059; MIPS32: move [[T0]],a3 4060; MIPS32: srl [[T0]],[[T0]],0x10 4061; MIPS32: andi [[T0]],[[T0]],0xff 4062; MIPS32: move [[T2]],[[T3]] 4063; MIPS32: srl [[T2]],[[T2]],0x10 4064; MIPS32: andi [[T2]],[[T2]],0xff 4065; MIPS32: sll [[T0]],[[T0]],0x18 4066; MIPS32: sll [[T2]],[[T2]],0x18 4067; MIPS32: sltu [[T0]],[[T0]],[[T2]] 4068; MIPS32: xori [[T0]],[[T0]],0x1 4069; MIPS32: andi [[T0]],[[T0]],0xff 4070; MIPS32: sll [[T0]],[[T0]],0x10 4071; MIPS32: lui [[T2]],0xff00 4072; MIPS32: ori [[T2]],[[T2]],0xffff 4073; MIPS32: and [[T1]],[[T1]],[[T2]] 4074; MIPS32: or [[T0]],[[T0]],[[T1]] 4075; MIPS32: srl [[T13:.*]],a3,0x18 4076; MIPS32: srl [[T3]],[[T3]],0x18 4077; MIPS32: sll [[T13]],[[T13]],0x18 4078; MIPS32: sll [[T3]],[[T3]],0x18 4079; MIPS32: sltu [[T13]],[[T13]],[[T3]] 4080; MIPS32: xori [[T13]],[[T13]],0x1 4081; MIPS32: sll [[T13]],[[T13]],0x18 4082; MIPS32: sll [[T0]],[[T0]],0x8 4083; MIPS32: srl [[T0]],[[T0]],0x8 4084; MIPS32: or [[T13]],[[T13]],[[T0]] 4085; MIPS32: move v0,[[T10]] 4086; MIPS32: move v1,[[T11]] 4087; MIPS32: move a0,[[T12]] 4088; MIPS32: move a1,[[T13]] 4089} 4090 4091define internal <16 x i1> @test_icmp_v16i8_ugt(<16 x i8> %a, <16 x i8> %b) { 4092entry: 4093 %res = icmp ugt <16 x i8> %a, %b 4094 ret <16 x i1> %res 4095; CHECK-LABEL: test_icmp_v16i8_ugt 4096; CHECK: pxor 4097; CHECK: pcmpgtb 4098 4099; MIPS32-LABEL: test_icmp_v16i8_ugt 4100; MIPS32: lw [[T0:.*]], 4101; MIPS32: lw [[T1:.*]], 4102; MIPS32: lw [[T2:.*]], 4103; MIPS32: lw [[T3:.*]], 4104; MIPS32: move [[T4:.*]],zero 4105; MIPS32: move [[T5:.*]],zero 4106; MIPS32: move [[T6:.*]],zero 4107; MIPS32: move [[T7:.*]],zero 4108; MIPS32: move [[T8:.*]],a0 4109; MIPS32: andi [[T8]],[[T8]],0xff 4110; MIPS32: move [[T9:.*]],[[T0]] 4111; MIPS32: andi [[T9]],[[T9]],0xff 4112; MIPS32: sll [[T8]],[[T8]],0x18 4113; MIPS32: sll [[T9]],[[T9]],0x18 4114; MIPS32: sltu [[T9]],[[T9]],[[T8]] 4115; MIPS32: andi [[T9]],[[T9]],0xff 4116; MIPS32: srl [[T4]],[[T4]],0x8 4117; MIPS32: sll [[T4]],[[T4]],0x8 4118; MIPS32: or [[T9]],[[T9]],[[T4]] 4119; MIPS32: move [[T4]],a0 4120; MIPS32: srl [[T4]],[[T4]],0x8 4121; MIPS32: andi [[T4]],[[T4]],0xff 4122; MIPS32: move [[T8]],[[T0]] 4123; MIPS32: srl [[T8]],[[T8]],0x8 4124; MIPS32: andi [[T8]],[[T8]],0xff 4125; MIPS32: sll [[T4]],[[T4]],0x18 4126; MIPS32: sll [[T8]],[[T8]],0x18 4127; MIPS32: sltu [[T8]],[[T8]],[[T4]] 4128; MIPS32: andi [[T8]],[[T8]],0xff 4129; MIPS32: sll [[T8]],[[T8]],0x8 4130; MIPS32: lui [[T4]],0xffff 4131; MIPS32: ori [[T4]],[[T4]],0xff 4132; MIPS32: and [[T9]],[[T9]],[[T4]] 4133; MIPS32: or [[T8]],[[T8]],[[T9]] 4134; MIPS32: move [[T4]],a0 4135; MIPS32: srl [[T4]],[[T4]],0x10 4136; MIPS32: andi [[T4]],[[T4]],0xff 4137; MIPS32: move [[T9]],[[T0]] 4138; MIPS32: srl [[T9]],[[T9]],0x10 4139; MIPS32: andi [[T9]],[[T9]],0xff 4140; MIPS32: sll [[T4]],[[T4]],0x18 4141; MIPS32: sll [[T9]],[[T9]],0x18 4142; MIPS32: sltu [[T9]],[[T9]],[[T4]] 4143; MIPS32: andi [[T9]],[[T9]],0xff 4144; MIPS32: sll [[T9]],[[T9]],0x10 4145; MIPS32: lui [[T4]],0xff00 4146; MIPS32: ori [[T4]],[[T4]],0xffff 4147; MIPS32: and [[T8]],[[T8]],[[T4]] 4148; MIPS32: or [[T9]],[[T9]],[[T8]] 4149; MIPS32: srl [[T10:.*]],a0,0x18 4150; MIPS32: srl [[T0]],[[T0]],0x18 4151; MIPS32: sll [[T10]],[[T10]],0x18 4152; MIPS32: sll [[T0]],[[T0]],0x18 4153; MIPS32: sltu [[T0]],[[T0]],[[T10]] 4154; MIPS32: sll [[T0]],[[T0]],0x18 4155; MIPS32: sll [[T9]],[[T9]],0x8 4156; MIPS32: srl [[T9]],[[T9]],0x8 4157; MIPS32: or v0,[[T0]],[[T9]] 4158; MIPS32: move [[T10]],a1 4159; MIPS32: andi [[T10]],[[T10]],0xff 4160; MIPS32: move [[T4]],[[T1]] 4161; MIPS32: andi [[T4]],[[T4]],0xff 4162; MIPS32: sll [[T10]],[[T10]],0x18 4163; MIPS32: sll [[T4]],[[T4]],0x18 4164; MIPS32: sltu [[T4]],[[T4]],[[T10]] 4165; MIPS32: andi [[T4]],[[T4]],0xff 4166; MIPS32: srl [[T5]],[[T5]],0x8 4167; MIPS32: sll [[T5]],[[T5]],0x8 4168; MIPS32: or [[T4]],[[T4]],[[T5]] 4169; MIPS32: move [[T10]],a1 4170; MIPS32: srl [[T10]],[[T10]],0x8 4171; MIPS32: andi [[T10]],[[T10]],0xff 4172; MIPS32: move [[T5]],[[T1]] 4173; MIPS32: srl [[T5]],[[T5]],0x8 4174; MIPS32: andi [[T5]],[[T5]],0xff 4175; MIPS32: sll [[T10]],[[T10]],0x18 4176; MIPS32: sll [[T5]],[[T5]],0x18 4177; MIPS32: sltu [[T5]],[[T5]],[[T10]] 4178; MIPS32: andi [[T5]],[[T5]],0xff 4179; MIPS32: sll [[T5]],[[T5]],0x8 4180; MIPS32: lui [[T10]],0xffff 4181; MIPS32: ori [[T10]],[[T10]],0xff 4182; MIPS32: and [[T4]],[[T4]],[[T10]] 4183; MIPS32: or [[T5]],[[T5]],[[T4]] 4184; MIPS32: move [[T10]],a1 4185; MIPS32: srl [[T10]],[[T10]],0x10 4186; MIPS32: andi [[T10]],[[T10]],0xff 4187; MIPS32: move [[T4]],[[T1]] 4188; MIPS32: srl [[T4]],[[T4]],0x10 4189; MIPS32: andi [[T4]],[[T4]],0xff 4190; MIPS32: sll [[T10]],[[T10]],0x18 4191; MIPS32: sll [[T4]],[[T4]],0x18 4192; MIPS32: sltu [[T4]],[[T4]],[[T10]] 4193; MIPS32: andi [[T4]],[[T4]],0xff 4194; MIPS32: sll [[T4]],[[T4]],0x10 4195; MIPS32: lui [[T10]],0xff00 4196; MIPS32: ori [[T10]],[[T10]],0xffff 4197; MIPS32: and [[T5]],[[T5]],[[T10]] 4198; MIPS32: or [[T4]],[[T4]],[[T5]] 4199; MIPS32: srl [[T11:.*]],a1,0x18 4200; MIPS32: srl [[T1]],[[T1]],0x18 4201; MIPS32: sll [[T11]],[[T11]],0x18 4202; MIPS32: sll [[T1]],[[T1]],0x18 4203; MIPS32: sltu [[T1]],[[T1]],[[T11]] 4204; MIPS32: sll [[T1]],[[T1]],0x18 4205; MIPS32: sll [[T4]],[[T4]],0x8 4206; MIPS32: srl [[T4]],[[T4]],0x8 4207; MIPS32: or v1,[[T1]],[[T4]] 4208; MIPS32: move [[T10]],a2 4209; MIPS32: andi [[T10]],[[T10]],0xff 4210; MIPS32: move [[T11]],[[T2]] 4211; MIPS32: andi [[T11]],[[T11]],0xff 4212; MIPS32: sll [[T10]],[[T10]],0x18 4213; MIPS32: sll [[T11]],[[T11]],0x18 4214; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4215; MIPS32: andi [[T11]],[[T11]],0xff 4216; MIPS32: srl [[T6]],[[T6]],0x8 4217; MIPS32: sll [[T6]],[[T6]],0x8 4218; MIPS32: or [[T11]],[[T11]],[[T6]] 4219; MIPS32: move [[T10]],a2 4220; MIPS32: srl [[T10]],[[T10]],0x8 4221; MIPS32: andi [[T10]],[[T10]],0xff 4222; MIPS32: move [[T4]],[[T2]] 4223; MIPS32: srl [[T4]],[[T4]],0x8 4224; MIPS32: andi [[T4]],[[T4]],0xff 4225; MIPS32: sll [[T10]],[[T10]],0x18 4226; MIPS32: sll [[T4]],[[T4]],0x18 4227; MIPS32: sltu [[T4]],[[T4]],[[T10]] 4228; MIPS32: andi [[T4]],[[T4]],0xff 4229; MIPS32: sll [[T4]],[[T4]],0x8 4230; MIPS32: lui [[T10]],0xffff 4231; MIPS32: ori [[T10]],[[T10]],0xff 4232; MIPS32: and [[T11]],[[T11]],[[T10]] 4233; MIPS32: or [[T4]],[[T4]],[[T11]] 4234; MIPS32: move [[T10]],a2 4235; MIPS32: srl [[T10]],[[T10]],0x10 4236; MIPS32: andi [[T10]],[[T10]],0xff 4237; MIPS32: move [[T11]],[[T2]] 4238; MIPS32: srl [[T11]],[[T11]],0x10 4239; MIPS32: andi [[T11]],[[T11]],0xff 4240; MIPS32: sll [[T10]],[[T10]],0x18 4241; MIPS32: sll [[T11]],[[T11]],0x18 4242; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4243; MIPS32: andi [[T11]],[[T11]],0xff 4244; MIPS32: sll [[T11]],[[T11]],0x10 4245; MIPS32: lui [[T10]],0xff00 4246; MIPS32: ori [[T10]],[[T10]],0xffff 4247; MIPS32: and [[T4]],[[T4]],[[T10]] 4248; MIPS32: or [[T11]],[[T11]],[[T4]] 4249; MIPS32: srl [[T12:.*]],a2,0x18 4250; MIPS32: srl [[T2]],[[T2]],0x18 4251; MIPS32: sll [[T12]],[[T12]],0x18 4252; MIPS32: sll [[T2]],[[T2]],0x18 4253; MIPS32: sltu [[T2]],[[T2]],[[T12]] 4254; MIPS32: sll [[T2]],[[T2]],0x18 4255; MIPS32: sll [[T11]],[[T11]],0x8 4256; MIPS32: srl [[T11]],[[T11]],0x8 4257; MIPS32: or [[T2]],[[T2]],[[T11]] 4258; MIPS32: move [[T10]],a3 4259; MIPS32: andi [[T10]],[[T10]],0xff 4260; MIPS32: move [[T11]],[[T3]] 4261; MIPS32: andi [[T11]],[[T11]],0xff 4262; MIPS32: sll [[T10]],[[T10]],0x18 4263; MIPS32: sll [[T11]],[[T11]],0x18 4264; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4265; MIPS32: andi [[T11]],[[T11]],0xff 4266; MIPS32: srl [[T7]],[[T7]],0x8 4267; MIPS32: sll [[T7]],[[T7]],0x8 4268; MIPS32: or [[T11]],[[T11]],[[T7]] 4269; MIPS32: move [[T10]],a3 4270; MIPS32: srl [[T10]],[[T10]],0x8 4271; MIPS32: andi [[T10]],[[T10]],0xff 4272; MIPS32: move [[T12]],[[T3]] 4273; MIPS32: srl [[T12]],[[T12]],0x8 4274; MIPS32: andi [[T12]],[[T12]],0xff 4275; MIPS32: sll [[T10]],[[T10]],0x18 4276; MIPS32: sll [[T12]],[[T12]],0x18 4277; MIPS32: sltu [[T12]],[[T12]],[[T10]] 4278; MIPS32: andi [[T12]],[[T12]],0xff 4279; MIPS32: sll [[T12]],[[T12]],0x8 4280; MIPS32: lui [[T10]],0xffff 4281; MIPS32: ori [[T10]],[[T10]],0xff 4282; MIPS32: and [[T11]],[[T11]],[[T10]] 4283; MIPS32: or [[T12]],[[T12]],[[T11]] 4284; MIPS32: move [[T10]],a3 4285; MIPS32: srl [[T10]],[[T10]],0x10 4286; MIPS32: andi [[T10]],[[T10]],0xff 4287; MIPS32: move [[T11]],[[T3]] 4288; MIPS32: srl [[T11]],[[T11]],0x10 4289; MIPS32: andi [[T11]],[[T11]],0xff 4290; MIPS32: sll [[T10]],[[T10]],0x18 4291; MIPS32: sll [[T11]],[[T11]],0x18 4292; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4293; MIPS32: andi [[T11]],[[T11]],0xff 4294; MIPS32: sll [[T11]],[[T11]],0x10 4295; MIPS32: lui [[T10]],0xff00 4296; MIPS32: ori [[T10]],[[T10]],0xffff 4297; MIPS32: and [[T12]],[[T12]],[[T10]] 4298; MIPS32: or [[T11]],[[T11]],[[T12]] 4299; MIPS32: srl [[T13:.*]],a3,0x18 4300; MIPS32: srl [[T3]],[[T3]],0x18 4301; MIPS32: sll [[T13]],[[T13]],0x18 4302; MIPS32: sll [[T3]],[[T3]],0x18 4303; MIPS32: sltu [[T3]],[[T3]],[[T13]] 4304; MIPS32: sll [[T3]],[[T3]],0x18 4305; MIPS32: sll [[T11]],[[T11]],0x8 4306; MIPS32: srl [[T11]],[[T11]],0x8 4307; MIPS32: or [[T3]],[[T3]],[[T11]] 4308; MIPS32: move a0,[[T2]] 4309; MIPS32: move a1,[[T3]] 4310} 4311 4312define internal <16 x i1> @test_icmp_v16i8_ule(<16 x i8> %a, <16 x i8> %b) { 4313entry: 4314 %res = icmp ule <16 x i8> %a, %b 4315 ret <16 x i1> %res 4316; CHECK-LABEL: test_icmp_v16i8_ule 4317; CHECK: pxor 4318; CHECK: pcmpgtb 4319; CHECK: pxor 4320 4321; MIPS32-LABEL: test_icmp_v16i8_ule 4322; MIPS32: lw [[T0:.*]], 4323; MIPS32: lw [[T1:.*]], 4324; MIPS32: lw [[T2:.*]], 4325; MIPS32: lw [[T3:.*]], 4326; MIPS32: move [[T4:.*]],zero 4327; MIPS32: move [[T5:.*]],zero 4328; MIPS32: move [[T6:.*]],zero 4329; MIPS32: move [[T7:.*]],zero 4330; MIPS32: move [[T8:.*]],a0 4331; MIPS32: andi [[T8]],[[T8]],0xff 4332; MIPS32: move [[T9:.*]],[[T0]] 4333; MIPS32: andi [[T9]],[[T9]],0xff 4334; MIPS32: sll [[T8]],[[T8]],0x18 4335; MIPS32: sll [[T9]],[[T9]],0x18 4336; MIPS32: sltu [[T9]],[[T9]],[[T8]] 4337; MIPS32: xori [[T9]],[[T9]],0x1 4338; MIPS32: andi [[T9]],[[T9]],0xff 4339; MIPS32: srl [[T4]],[[T4]],0x8 4340; MIPS32: sll [[T4]],[[T4]],0x8 4341; MIPS32: or [[T9]],[[T9]],[[T4]] 4342; MIPS32: move [[T4]],a0 4343; MIPS32: srl [[T4]],[[T4]],0x8 4344; MIPS32: andi [[T4]],[[T4]],0xff 4345; MIPS32: move [[T8]],[[T0]] 4346; MIPS32: srl [[T8]],[[T8]],0x8 4347; MIPS32: andi [[T8]],[[T8]],0xff 4348; MIPS32: sll [[T4]],[[T4]],0x18 4349; MIPS32: sll [[T8]],[[T8]],0x18 4350; MIPS32: sltu [[T8]],[[T8]],[[T4]] 4351; MIPS32: xori [[T8]],[[T8]],0x1 4352; MIPS32: andi [[T8]],[[T8]],0xff 4353; MIPS32: sll [[T8]],[[T8]],0x8 4354; MIPS32: lui [[T4]],0xffff 4355; MIPS32: ori [[T4]],[[T4]],0xff 4356; MIPS32: and [[T9]],[[T9]],[[T4]] 4357; MIPS32: or [[T8]],[[T8]],[[T9]] 4358; MIPS32: move [[T4]],a0 4359; MIPS32: srl [[T4]],[[T4]],0x10 4360; MIPS32: andi [[T4]],[[T4]],0xff 4361; MIPS32: move [[T9]],[[T0]] 4362; MIPS32: srl [[T9]],[[T9]],0x10 4363; MIPS32: andi [[T9]],[[T9]],0xff 4364; MIPS32: sll [[T4]],[[T4]],0x18 4365; MIPS32: sll [[T9]],[[T9]],0x18 4366; MIPS32: sltu [[T9]],[[T9]],[[T4]] 4367; MIPS32: xori [[T9]],[[T9]],0x1 4368; MIPS32: andi [[T9]],[[T9]],0xff 4369; MIPS32: sll [[T9]],[[T9]],0x10 4370; MIPS32: lui [[T4]],0xff00 4371; MIPS32: ori [[T4]],[[T4]],0xffff 4372; MIPS32: and [[T8]],[[T8]],[[T4]] 4373; MIPS32: or [[T9]],[[T9]],[[T8]] 4374; MIPS32: srl [[T10:.*]],a0,0x18 4375; MIPS32: srl [[T0]],[[T0]],0x18 4376; MIPS32: sll [[T10]],[[T10]],0x18 4377; MIPS32: sll [[T0]],[[T0]],0x18 4378; MIPS32: sltu [[T0]],[[T0]],[[T10]] 4379; MIPS32: xori [[T0]],[[T0]],0x1 4380; MIPS32: sll [[T0]],[[T0]],0x18 4381; MIPS32: sll [[T9]],[[T9]],0x8 4382; MIPS32: srl [[T9]],[[T9]],0x8 4383; MIPS32: or v0,[[T0]],[[T9]] 4384; MIPS32: move [[T10]],a1 4385; MIPS32: andi [[T10]],[[T10]],0xff 4386; MIPS32: move [[T4]],[[T1]] 4387; MIPS32: andi [[T4]],[[T4]],0xff 4388; MIPS32: sll [[T10]],[[T10]],0x18 4389; MIPS32: sll [[T4]],[[T4]],0x18 4390; MIPS32: sltu [[T4]],[[T4]],[[T10]] 4391; MIPS32: xori [[T4]],[[T4]],0x1 4392; MIPS32: andi [[T4]],[[T4]],0xff 4393; MIPS32: srl [[T5]],[[T5]],0x8 4394; MIPS32: sll [[T5]],[[T5]],0x8 4395; MIPS32: or [[T4]],[[T4]],[[T5]] 4396; MIPS32: move [[T10]],a1 4397; MIPS32: srl [[T10]],[[T10]],0x8 4398; MIPS32: andi [[T10]],[[T10]],0xff 4399; MIPS32: move [[T5]],[[T1]] 4400; MIPS32: srl [[T5]],[[T5]],0x8 4401; MIPS32: andi [[T5]],[[T5]],0xff 4402; MIPS32: sll [[T10]],[[T10]],0x18 4403; MIPS32: sll [[T5]],[[T5]],0x18 4404; MIPS32: sltu [[T5]],[[T5]],[[T10]] 4405; MIPS32: xori [[T5]],[[T5]],0x1 4406; MIPS32: andi [[T5]],[[T5]],0xff 4407; MIPS32: sll [[T5]],[[T5]],0x8 4408; MIPS32: lui [[T10]],0xffff 4409; MIPS32: ori [[T10]],[[T10]],0xff 4410; MIPS32: and [[T4]],[[T4]],[[T10]] 4411; MIPS32: or [[T5]],[[T5]],[[T4]] 4412; MIPS32: move [[T10]],a1 4413; MIPS32: srl [[T10]],[[T10]],0x10 4414; MIPS32: andi [[T10]],[[T10]],0xff 4415; MIPS32: move [[T4]],[[T1]] 4416; MIPS32: srl [[T4]],[[T4]],0x10 4417; MIPS32: andi [[T4]],[[T4]],0xff 4418; MIPS32: sll [[T10]],[[T10]],0x18 4419; MIPS32: sll [[T4]],[[T4]],0x18 4420; MIPS32: sltu [[T4]],[[T4]],[[T10]] 4421; MIPS32: xori [[T4]],[[T4]],0x1 4422; MIPS32: andi [[T4]],[[T4]],0xff 4423; MIPS32: sll [[T4]],[[T4]],0x10 4424; MIPS32: lui [[T10]],0xff00 4425; MIPS32: ori [[T10]],[[T10]],0xffff 4426; MIPS32: and [[T5]],[[T5]],[[T10]] 4427; MIPS32: or [[T4]],[[T4]],[[T5]] 4428; MIPS32: srl [[T11:.*]],a1,0x18 4429; MIPS32: srl [[T1]],[[T1]],0x18 4430; MIPS32: sll [[T11]],[[T11]],0x18 4431; MIPS32: sll [[T1]],[[T1]],0x18 4432; MIPS32: sltu [[T1]],[[T1]],[[T11]] 4433; MIPS32: xori [[T1]],[[T1]],0x1 4434; MIPS32: sll [[T1]],[[T1]],0x18 4435; MIPS32: sll [[T4]],[[T4]],0x8 4436; MIPS32: srl [[T4]],[[T4]],0x8 4437; MIPS32: or v1,[[T1]],[[T4]] 4438; MIPS32: move [[T10]],a2 4439; MIPS32: andi [[T10]],[[T10]],0xff 4440; MIPS32: move [[T11]],[[T2]] 4441; MIPS32: andi [[T11]],[[T11]],0xff 4442; MIPS32: sll [[T10]],[[T10]],0x18 4443; MIPS32: sll [[T11]],[[T11]],0x18 4444; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4445; MIPS32: xori [[T11]],[[T11]],0x1 4446; MIPS32: andi [[T11]],[[T11]],0xff 4447; MIPS32: srl [[T6]],[[T6]],0x8 4448; MIPS32: sll [[T6]],[[T6]],0x8 4449; MIPS32: or [[T11]],[[T11]],[[T6]] 4450; MIPS32: move [[T10]],a2 4451; MIPS32: srl [[T10]],[[T10]],0x8 4452; MIPS32: andi [[T10]],[[T10]],0xff 4453; MIPS32: move [[T4]],[[T2]] 4454; MIPS32: srl [[T4]],[[T4]],0x8 4455; MIPS32: andi [[T4]],[[T4]],0xff 4456; MIPS32: sll [[T10]],[[T10]],0x18 4457; MIPS32: sll [[T4]],[[T4]],0x18 4458; MIPS32: sltu [[T4]],[[T4]],[[T10]] 4459; MIPS32: xori [[T4]],[[T4]],0x1 4460; MIPS32: andi [[T4]],[[T4]],0xff 4461; MIPS32: sll [[T4]],[[T4]],0x8 4462; MIPS32: lui [[T10]],0xffff 4463; MIPS32: ori [[T10]],[[T10]],0xff 4464; MIPS32: and [[T11]],[[T11]],[[T10]] 4465; MIPS32: or [[T4]],[[T4]],[[T11]] 4466; MIPS32: move [[T10]],a2 4467; MIPS32: srl [[T10]],[[T10]],0x10 4468; MIPS32: andi [[T10]],[[T10]],0xff 4469; MIPS32: move [[T11]],[[T2]] 4470; MIPS32: srl [[T11]],[[T11]],0x10 4471; MIPS32: andi [[T11]],[[T11]],0xff 4472; MIPS32: sll [[T10]],[[T10]],0x18 4473; MIPS32: sll [[T11]],[[T11]],0x18 4474; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4475; MIPS32: xori [[T11]],[[T11]],0x1 4476; MIPS32: andi [[T11]],[[T11]],0xff 4477; MIPS32: sll [[T11]],[[T11]],0x10 4478; MIPS32: lui [[T10]],0xff00 4479; MIPS32: ori [[T10]],[[T10]],0xffff 4480; MIPS32: and [[T4]],[[T4]],[[T10]] 4481; MIPS32: or [[T11]],[[T11]],[[T4]] 4482; MIPS32: srl [[T12:.*]],a2,0x18 4483; MIPS32: srl [[T2]],[[T2]],0x18 4484; MIPS32: sll [[T12]],[[T12]],0x18 4485; MIPS32: sll [[T2]],[[T2]],0x18 4486; MIPS32: sltu [[T2]],[[T2]],[[T12]] 4487; MIPS32: xori [[T2]],[[T2]],0x1 4488; MIPS32: sll [[T2]],[[T2]],0x18 4489; MIPS32: sll [[T11]],[[T11]],0x8 4490; MIPS32: srl [[T11]],[[T11]],0x8 4491; MIPS32: or [[T2]],[[T2]],[[T11]] 4492; MIPS32: move [[T10]],a3 4493; MIPS32: andi [[T10]],[[T10]],0xff 4494; MIPS32: move [[T11]],[[T3]] 4495; MIPS32: andi [[T11]],[[T11]],0xff 4496; MIPS32: sll [[T10]],[[T10]],0x18 4497; MIPS32: sll [[T11]],[[T11]],0x18 4498; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4499; MIPS32: xori [[T11]],[[T11]],0x1 4500; MIPS32: andi [[T11]],[[T11]],0xff 4501; MIPS32: srl [[T7]],[[T7]],0x8 4502; MIPS32: sll [[T7]],[[T7]],0x8 4503; MIPS32: or [[T11]],[[T11]],[[T7]] 4504; MIPS32: move [[T10]],a3 4505; MIPS32: srl [[T10]],[[T10]],0x8 4506; MIPS32: andi [[T10]],[[T10]],0xff 4507; MIPS32: move [[T12]],[[T3]] 4508; MIPS32: srl [[T12]],[[T12]],0x8 4509; MIPS32: andi [[T12]],[[T12]],0xff 4510; MIPS32: sll [[T10]],[[T10]],0x18 4511; MIPS32: sll [[T12]],[[T12]],0x18 4512; MIPS32: sltu [[T12]],[[T12]],[[T10]] 4513; MIPS32: xori [[T12]],[[T12]],0x1 4514; MIPS32: andi [[T12]],[[T12]],0xff 4515; MIPS32: sll [[T12]],[[T12]],0x8 4516; MIPS32: lui [[T10]],0xffff 4517; MIPS32: ori [[T10]],[[T10]],0xff 4518; MIPS32: and [[T11]],[[T11]],[[T10]] 4519; MIPS32: or [[T12]],[[T12]],[[T11]] 4520; MIPS32: move [[T10]],a3 4521; MIPS32: srl [[T10]],[[T10]],0x10 4522; MIPS32: andi [[T10]],[[T10]],0xff 4523; MIPS32: move [[T11]],[[T3]] 4524; MIPS32: srl [[T11]],[[T11]],0x10 4525; MIPS32: andi [[T11]],[[T11]],0xff 4526; MIPS32: sll [[T10]],[[T10]],0x18 4527; MIPS32: sll [[T11]],[[T11]],0x18 4528; MIPS32: sltu [[T11]],[[T11]],[[T10]] 4529; MIPS32: xori [[T11]],[[T11]],0x1 4530; MIPS32: andi [[T11]],[[T11]],0xff 4531; MIPS32: sll [[T11]],[[T11]],0x10 4532; MIPS32: lui [[T10]],0xff00 4533; MIPS32: ori [[T10]],[[T10]],0xffff 4534; MIPS32: and [[T12]],[[T12]],[[T10]] 4535; MIPS32: or [[T11]],[[T11]],[[T12]] 4536; MIPS32: srl [[T13:.*]],a3,0x18 4537; MIPS32: srl [[T3]],[[T3]],0x18 4538; MIPS32: sll [[T13]],[[T13]],0x18 4539; MIPS32: sll [[T3]],[[T3]],0x18 4540; MIPS32: sltu [[T3]],[[T3]],[[T13]] 4541; MIPS32: xori [[T3]],[[T3]],0x1 4542; MIPS32: sll [[T3]],[[T3]],0x18 4543; MIPS32: sll [[T11]],[[T11]],0x8 4544; MIPS32: srl [[T11]],[[T11]],0x8 4545; MIPS32: or [[T3]],[[T3]],[[T11]] 4546; MIPS32: move a0,[[T2]] 4547; MIPS32: move a1,[[T3]] 4548} 4549 4550define internal <16 x i1> @test_icmp_v16i8_ult(<16 x i8> %a, <16 x i8> %b) { 4551entry: 4552 %res = icmp ult <16 x i8> %a, %b 4553 ret <16 x i1> %res 4554; CHECK-LABEL: test_icmp_v16i8_ult 4555; CHECK: pxor 4556; CHECK: pcmpgtb 4557 4558; MIPS32-LABEL: test_icmp_v16i8_ult 4559; MIPS32: lw [[T0:.*]], 4560; MIPS32: lw [[T1:.*]], 4561; MIPS32: lw [[T2:.*]], 4562; MIPS32: lw [[T3:.*]], 4563; MIPS32: move [[T4:.*]],zero 4564; MIPS32: move [[T5:.*]],zero 4565; MIPS32: move [[T6:.*]],zero 4566; MIPS32: move [[T7:.*]],zero 4567; MIPS32: move [[T8:.*]],a0 4568; MIPS32: andi [[T8]],[[T8]],0xff 4569; MIPS32: move [[T9:.*]],[[T0]] 4570; MIPS32: andi [[T9]],[[T9]],0xff 4571; MIPS32: sll [[T8]],[[T8]],0x18 4572; MIPS32: sll [[T9]],[[T9]],0x18 4573; MIPS32: sltu [[T8]],[[T8]],[[T9]] 4574; MIPS32: andi [[T8]],[[T8]],0xff 4575; MIPS32: srl [[T4]],[[T4]],0x8 4576; MIPS32: sll [[T4]],[[T4]],0x8 4577; MIPS32: or [[T8]],[[T8]],[[T4]] 4578; MIPS32: move [[T4]],a0 4579; MIPS32: srl [[T4]],[[T4]],0x8 4580; MIPS32: andi [[T4]],[[T4]],0xff 4581; MIPS32: move [[T9]],[[T0]] 4582; MIPS32: srl [[T9]],[[T9]],0x8 4583; MIPS32: andi [[T9]],[[T9]],0xff 4584; MIPS32: sll [[T4]],[[T4]],0x18 4585; MIPS32: sll [[T9]],[[T9]],0x18 4586; MIPS32: sltu [[T4]],[[T4]],[[T9]] 4587; MIPS32: andi [[T4]],[[T4]],0xff 4588; MIPS32: sll [[T4]],[[T4]],0x8 4589; MIPS32: lui [[T9]],0xffff 4590; MIPS32: ori [[T9]],[[T9]],0xff 4591; MIPS32: and [[T8]],[[T8]],[[T9]] 4592; MIPS32: or [[T4]],[[T4]],[[T8]] 4593; MIPS32: move [[T8]],a0 4594; MIPS32: srl [[T8]],[[T8]],0x10 4595; MIPS32: andi [[T8]],[[T8]],0xff 4596; MIPS32: move [[T9]],[[T0]] 4597; MIPS32: srl [[T9]],[[T9]],0x10 4598; MIPS32: andi [[T9]],[[T9]],0xff 4599; MIPS32: sll [[T8]],[[T8]],0x18 4600; MIPS32: sll [[T9]],[[T9]],0x18 4601; MIPS32: sltu [[T8]],[[T8]],[[T9]] 4602; MIPS32: andi [[T8]],[[T8]],0xff 4603; MIPS32: sll [[T8]],[[T8]],0x10 4604; MIPS32: lui [[T9]],0xff00 4605; MIPS32: ori [[T9]],[[T9]],0xffff 4606; MIPS32: and [[T4]],[[T4]],[[T9]] 4607; MIPS32: or [[T8]],[[T8]],[[T4]] 4608; MIPS32: srl [[T10:.*]],a0,0x18 4609; MIPS32: srl [[T0]],[[T0]],0x18 4610; MIPS32: sll [[T10]],[[T10]],0x18 4611; MIPS32: sll [[T0]],[[T0]],0x18 4612; MIPS32: sltu [[T10]],[[T10]],[[T0]] 4613; MIPS32: sll [[T10]],[[T10]],0x18 4614; MIPS32: sll [[T8]],[[T8]],0x8 4615; MIPS32: srl [[T8]],[[T8]],0x8 4616; MIPS32: or [[T10]],[[T10]],[[T8]] 4617; MIPS32: move [[T0]],a1 4618; MIPS32: andi [[T0]],[[T0]],0xff 4619; MIPS32: move [[T4]],[[T1]] 4620; MIPS32: andi [[T4]],[[T4]],0xff 4621; MIPS32: sll [[T0]],[[T0]],0x18 4622; MIPS32: sll [[T4]],[[T4]],0x18 4623; MIPS32: sltu [[T0]],[[T0]],[[T4]] 4624; MIPS32: andi [[T0]],[[T0]],0xff 4625; MIPS32: srl [[T5]],[[T5]],0x8 4626; MIPS32: sll [[T5]],[[T5]],0x8 4627; MIPS32: or [[T0]],[[T0]],[[T5]] 4628; MIPS32: move [[T4]],a1 4629; MIPS32: srl [[T4]],[[T4]],0x8 4630; MIPS32: andi [[T4]],[[T4]],0xff 4631; MIPS32: move [[T5]],[[T1]] 4632; MIPS32: srl [[T5]],[[T5]],0x8 4633; MIPS32: andi [[T5]],[[T5]],0xff 4634; MIPS32: sll [[T4]],[[T4]],0x18 4635; MIPS32: sll [[T5]],[[T5]],0x18 4636; MIPS32: sltu [[T4]],[[T4]],[[T5]] 4637; MIPS32: andi [[T4]],[[T4]],0xff 4638; MIPS32: sll [[T4]],[[T4]],0x8 4639; MIPS32: lui [[T5]],0xffff 4640; MIPS32: ori [[T5]],[[T5]],0xff 4641; MIPS32: and [[T0]],[[T0]],[[T5]] 4642; MIPS32: or [[T4]],[[T4]],[[T0]] 4643; MIPS32: move [[T0]],a1 4644; MIPS32: srl [[T0]],[[T0]],0x10 4645; MIPS32: andi [[T0]],[[T0]],0xff 4646; MIPS32: move [[T5]],[[T1]] 4647; MIPS32: srl [[T5]],[[T5]],0x10 4648; MIPS32: andi [[T5]],[[T5]],0xff 4649; MIPS32: sll [[T0]],[[T0]],0x18 4650; MIPS32: sll [[T5]],[[T5]],0x18 4651; MIPS32: sltu [[T0]],[[T0]],[[T5]] 4652; MIPS32: andi [[T0]],[[T0]],0xff 4653; MIPS32: sll [[T0]],[[T0]],0x10 4654; MIPS32: lui [[T5]],0xff00 4655; MIPS32: ori [[T5]],[[T5]],0xffff 4656; MIPS32: and [[T4]],[[T4]],[[T5]] 4657; MIPS32: or [[T0]],[[T0]],[[T4]] 4658; MIPS32: srl [[T11:.*]],a1,0x18 4659; MIPS32: srl [[T1]],[[T1]],0x18 4660; MIPS32: sll [[T11]],[[T11]],0x18 4661; MIPS32: sll [[T1]],[[T1]],0x18 4662; MIPS32: sltu [[T11]],[[T11]],[[T1]] 4663; MIPS32: sll [[T11]],[[T11]],0x18 4664; MIPS32: sll [[T0]],[[T0]],0x8 4665; MIPS32: srl [[T0]],[[T0]],0x8 4666; MIPS32: or [[T11]],[[T11]],[[T0]] 4667; MIPS32: move [[T0]],a2 4668; MIPS32: andi [[T0]],[[T0]],0xff 4669; MIPS32: move [[T1]],[[T2]] 4670; MIPS32: andi [[T1]],[[T1]],0xff 4671; MIPS32: sll [[T0]],[[T0]],0x18 4672; MIPS32: sll [[T1]],[[T1]],0x18 4673; MIPS32: sltu [[T0]],[[T0]],[[T1]] 4674; MIPS32: andi [[T0]],[[T0]],0xff 4675; MIPS32: srl [[T6]],[[T6]],0x8 4676; MIPS32: sll [[T6]],[[T6]],0x8 4677; MIPS32: or [[T0]],[[T0]],[[T6]] 4678; MIPS32: move [[T1]],a2 4679; MIPS32: srl [[T1]],[[T1]],0x8 4680; MIPS32: andi [[T1]],[[T1]],0xff 4681; MIPS32: move [[T4]],[[T2]] 4682; MIPS32: srl [[T4]],[[T4]],0x8 4683; MIPS32: andi [[T4]],[[T4]],0xff 4684; MIPS32: sll [[T1]],[[T1]],0x18 4685; MIPS32: sll [[T4]],[[T4]],0x18 4686; MIPS32: sltu [[T1]],[[T1]],[[T4]] 4687; MIPS32: andi [[T1]],[[T1]],0xff 4688; MIPS32: sll [[T1]],[[T1]],0x8 4689; MIPS32: lui [[T4]],0xffff 4690; MIPS32: ori [[T4]],[[T4]],0xff 4691; MIPS32: and [[T0]],[[T0]],[[T4]] 4692; MIPS32: or [[T1]],[[T1]],[[T0]] 4693; MIPS32: move [[T0]],a2 4694; MIPS32: srl [[T0]],[[T0]],0x10 4695; MIPS32: andi [[T0]],[[T0]],0xff 4696; MIPS32: move [[T4]],[[T2]] 4697; MIPS32: srl [[T4]],[[T4]],0x10 4698; MIPS32: andi [[T4]],[[T4]],0xff 4699; MIPS32: sll [[T0]],[[T0]],0x18 4700; MIPS32: sll [[T4]],[[T4]],0x18 4701; MIPS32: sltu [[T0]],[[T0]],[[T4]] 4702; MIPS32: andi [[T0]],[[T0]],0xff 4703; MIPS32: sll [[T0]],[[T0]],0x10 4704; MIPS32: lui [[T4]],0xff00 4705; MIPS32: ori [[T4]],[[T4]],0xffff 4706; MIPS32: and [[T1]],[[T1]],[[T4]] 4707; MIPS32: or [[T0]],[[T0]],[[T1]] 4708; MIPS32: srl [[T12:.*]],a2,0x18 4709; MIPS32: srl [[T2]],[[T2]],0x18 4710; MIPS32: sll [[T12]],[[T12]],0x18 4711; MIPS32: sll [[T2]],[[T2]],0x18 4712; MIPS32: sltu [[T12]],[[T12]],[[T2]] 4713; MIPS32: sll [[T12]],[[T12]],0x18 4714; MIPS32: sll [[T0]],[[T0]],0x8 4715; MIPS32: srl [[T0]],[[T0]],0x8 4716; MIPS32: or [[T12]],[[T12]],[[T0]] 4717; MIPS32: move [[T0]],a3 4718; MIPS32: andi [[T0]],[[T0]],0xff 4719; MIPS32: move [[T1]],[[T3]] 4720; MIPS32: andi [[T1]],[[T1]],0xff 4721; MIPS32: sll [[T0]],[[T0]],0x18 4722; MIPS32: sll [[T1]],[[T1]],0x18 4723; MIPS32: sltu [[T0]],[[T0]],[[T1]] 4724; MIPS32: andi [[T0]],[[T0]],0xff 4725; MIPS32: srl [[T7]],[[T7]],0x8 4726; MIPS32: sll [[T7]],[[T7]],0x8 4727; MIPS32: or [[T0]],[[T0]],[[T7]] 4728; MIPS32: move [[T1]],a3 4729; MIPS32: srl [[T1]],[[T1]],0x8 4730; MIPS32: andi [[T1]],[[T1]],0xff 4731; MIPS32: move [[T2]],[[T3]] 4732; MIPS32: srl [[T2]],[[T2]],0x8 4733; MIPS32: andi [[T2]],[[T2]],0xff 4734; MIPS32: sll [[T1]],[[T1]],0x18 4735; MIPS32: sll [[T2]],[[T2]],0x18 4736; MIPS32: sltu [[T1]],[[T1]],[[T2]] 4737; MIPS32: andi [[T1]],[[T1]],0xff 4738; MIPS32: sll [[T1]],[[T1]],0x8 4739; MIPS32: lui [[T2]],0xffff 4740; MIPS32: ori [[T2]],[[T2]],0xff 4741; MIPS32: and [[T0]],[[T0]],[[T2]] 4742; MIPS32: or [[T1]],[[T1]],[[T0]] 4743; MIPS32: move [[T0]],a3 4744; MIPS32: srl [[T0]],[[T0]],0x10 4745; MIPS32: andi [[T0]],[[T0]],0xff 4746; MIPS32: move [[T2]],[[T3]] 4747; MIPS32: srl [[T2]],[[T2]],0x10 4748; MIPS32: andi [[T2]],[[T2]],0xff 4749; MIPS32: sll [[T0]],[[T0]],0x18 4750; MIPS32: sll [[T2]],[[T2]],0x18 4751; MIPS32: sltu [[T0]],[[T0]],[[T2]] 4752; MIPS32: andi [[T0]],[[T0]],0xff 4753; MIPS32: sll [[T0]],[[T0]],0x10 4754; MIPS32: lui [[T2]],0xff00 4755; MIPS32: ori [[T2]],[[T2]],0xffff 4756; MIPS32: and [[T1]],[[T1]],[[T2]] 4757; MIPS32: or [[T0]],[[T0]],[[T1]] 4758; MIPS32: srl [[T13:.*]],a3,0x18 4759; MIPS32: srl [[T3]],[[T3]],0x18 4760; MIPS32: sll [[T13]],[[T13]],0x18 4761; MIPS32: sll [[T3]],[[T3]],0x18 4762; MIPS32: sltu [[T13]],[[T13]],[[T3]] 4763; MIPS32: sll [[T13]],[[T13]],0x18 4764; MIPS32: sll [[T0]],[[T0]],0x8 4765; MIPS32: srl [[T0]],[[T0]],0x8 4766; MIPS32: or [[T13]],[[T13]],[[T0]] 4767; MIPS32: move v0,[[T10]] 4768; MIPS32: move v1,[[T11]] 4769; MIPS32: move a0,[[T12]] 4770; MIPS32: move a1,[[T13]] 4771} 4772 4773define internal <16 x i1> @test_icmp_v16i1_eq(<16 x i1> %a, <16 x i1> %b) { 4774entry: 4775 %res = icmp eq <16 x i1> %a, %b 4776 ret <16 x i1> %res 4777; CHECK-LABEL: test_icmp_v16i1_eq 4778; CHECK: pcmpeqb 4779 4780; MIPS32-LABEL: test_icmp_v16i1_eq 4781; MIPS32: lw [[T0:.*]], 4782; MIPS32: lw [[T1:.*]], 4783; MIPS32: lw [[T2:.*]], 4784; MIPS32: lw [[T3:.*]], 4785; MIPS32: move [[T4:.*]],zero 4786; MIPS32: move [[T5:.*]],zero 4787; MIPS32: move [[T6:.*]],zero 4788; MIPS32: move [[T7:.*]],zero 4789; MIPS32: move [[T8:.*]],a0 4790; MIPS32: andi [[T8]],[[T8]],0xff 4791; MIPS32: andi [[T8]],[[T8]],0x1 4792; MIPS32: move [[T9:.*]],[[T0]] 4793; MIPS32: andi [[T9]],[[T9]],0xff 4794; MIPS32: andi [[T9]],[[T9]],0x1 4795; MIPS32: sll [[T8]],[[T8]],0x1f 4796; MIPS32: sll [[T9]],[[T9]],0x1f 4797; MIPS32: xor [[T8]],[[T8]],[[T9]] 4798; MIPS32: sltiu [[T8]],[[T8]],1 4799; MIPS32: andi [[T8]],[[T8]],0xff 4800; MIPS32: srl [[T4]],[[T4]],0x8 4801; MIPS32: sll [[T4]],[[T4]],0x8 4802; MIPS32: or [[T8]],[[T8]],[[T4]] 4803; MIPS32: move [[T4]],a0 4804; MIPS32: srl [[T4]],[[T4]],0x8 4805; MIPS32: andi [[T4]],[[T4]],0xff 4806; MIPS32: andi [[T4]],[[T4]],0x1 4807; MIPS32: move [[T9]],[[T0]] 4808; MIPS32: srl [[T9]],[[T9]],0x8 4809; MIPS32: andi [[T9]],[[T9]],0xff 4810; MIPS32: andi [[T9]],[[T9]],0x1 4811; MIPS32: sll [[T4]],[[T4]],0x1f 4812; MIPS32: sll [[T9]],[[T9]],0x1f 4813; MIPS32: xor [[T4]],[[T4]],[[T9]] 4814; MIPS32: sltiu [[T4]],[[T4]],1 4815; MIPS32: andi [[T4]],[[T4]],0xff 4816; MIPS32: sll [[T4]],[[T4]],0x8 4817; MIPS32: lui [[T9]],0xffff 4818; MIPS32: ori [[T9]],[[T9]],0xff 4819; MIPS32: and [[T8]],[[T8]],[[T9]] 4820; MIPS32: or [[T4]],[[T4]],[[T8]] 4821; MIPS32: move [[T8]],a0 4822; MIPS32: srl [[T8]],[[T8]],0x10 4823; MIPS32: andi [[T8]],[[T8]],0xff 4824; MIPS32: andi [[T8]],[[T8]],0x1 4825; MIPS32: move [[T9]],[[T0]] 4826; MIPS32: srl [[T9]],[[T9]],0x10 4827; MIPS32: andi [[T9]],[[T9]],0xff 4828; MIPS32: andi [[T9]],[[T9]],0x1 4829; MIPS32: sll [[T8]],[[T8]],0x1f 4830; MIPS32: sll [[T9]],[[T9]],0x1f 4831; MIPS32: xor [[T8]],[[T8]],[[T9]] 4832; MIPS32: sltiu [[T8]],[[T8]],1 4833; MIPS32: andi [[T8]],[[T8]],0xff 4834; MIPS32: sll [[T8]],[[T8]],0x10 4835; MIPS32: lui [[T9]],0xff00 4836; MIPS32: ori [[T9]],[[T9]],0xffff 4837; MIPS32: and [[T4]],[[T4]],[[T9]] 4838; MIPS32: or [[T8]],[[T8]],[[T4]] 4839; MIPS32: srl [[T10:.*]],a0,0x18 4840; MIPS32: andi [[T10]],[[T10]],0x1 4841; MIPS32: srl [[T0]],[[T0]],0x18 4842; MIPS32: andi [[T0]],[[T0]],0x1 4843; MIPS32: sll [[T10]],[[T10]],0x1f 4844; MIPS32: sll [[T0]],[[T0]],0x1f 4845; MIPS32: xor [[T10]],[[T10]],[[T0]] 4846; MIPS32: sltiu [[T10]],[[T10]],1 4847; MIPS32: sll [[T10]],[[T10]],0x18 4848; MIPS32: sll [[T8]],[[T8]],0x8 4849; MIPS32: srl [[T8]],[[T8]],0x8 4850; MIPS32: or [[T10]],[[T10]],[[T8]] 4851; MIPS32: move [[T0]],a1 4852; MIPS32: andi [[T0]],[[T0]],0xff 4853; MIPS32: andi [[T0]],[[T0]],0x1 4854; MIPS32: move [[T4]],[[T1]] 4855; MIPS32: andi [[T4]],[[T4]],0xff 4856; MIPS32: andi [[T4]],[[T4]],0x1 4857; MIPS32: sll [[T0]],[[T0]],0x1f 4858; MIPS32: sll [[T4]],[[T4]],0x1f 4859; MIPS32: xor [[T0]],[[T0]],[[T4]] 4860; MIPS32: sltiu [[T0]],[[T0]],1 4861; MIPS32: andi [[T0]],[[T0]],0xff 4862; MIPS32: srl [[T5]],[[T5]],0x8 4863; MIPS32: sll [[T5]],[[T5]],0x8 4864; MIPS32: or [[T0]],[[T0]],[[T5]] 4865; MIPS32: move [[T4]],a1 4866; MIPS32: srl [[T4]],[[T4]],0x8 4867; MIPS32: andi [[T4]],[[T4]],0xff 4868; MIPS32: andi [[T4]],[[T4]],0x1 4869; MIPS32: move [[T5]],[[T1]] 4870; MIPS32: srl [[T5]],[[T5]],0x8 4871; MIPS32: andi [[T5]],[[T5]],0xff 4872; MIPS32: andi [[T5]],[[T5]],0x1 4873; MIPS32: sll [[T4]],[[T4]],0x1f 4874; MIPS32: sll [[T5]],[[T5]],0x1f 4875; MIPS32: xor [[T4]],[[T4]],[[T5]] 4876; MIPS32: sltiu [[T4]],[[T4]],1 4877; MIPS32: andi [[T4]],[[T4]],0xff 4878; MIPS32: sll [[T4]],[[T4]],0x8 4879; MIPS32: lui [[T5]],0xffff 4880; MIPS32: ori [[T5]],[[T5]],0xff 4881; MIPS32: and [[T0]],[[T0]],[[T5]] 4882; MIPS32: or [[T4]],[[T4]],[[T0]] 4883; MIPS32: move [[T0]],a1 4884; MIPS32: srl [[T0]],[[T0]],0x10 4885; MIPS32: andi [[T0]],[[T0]],0xff 4886; MIPS32: andi [[T0]],[[T0]],0x1 4887; MIPS32: move [[T5]],[[T1]] 4888; MIPS32: srl [[T5]],[[T5]],0x10 4889; MIPS32: andi [[T5]],[[T5]],0xff 4890; MIPS32: andi [[T5]],[[T5]],0x1 4891; MIPS32: sll [[T0]],[[T0]],0x1f 4892; MIPS32: sll [[T5]],[[T5]],0x1f 4893; MIPS32: xor [[T0]],[[T0]],[[T5]] 4894; MIPS32: sltiu [[T0]],[[T0]],1 4895; MIPS32: andi [[T0]],[[T0]],0xff 4896; MIPS32: sll [[T0]],[[T0]],0x10 4897; MIPS32: lui [[T5]],0xff00 4898; MIPS32: ori [[T5]],[[T5]],0xffff 4899; MIPS32: and [[T4]],[[T4]],[[T5]] 4900; MIPS32: or [[T0]],[[T0]],[[T4]] 4901; MIPS32: srl [[T11:.*]],a1,0x18 4902; MIPS32: andi [[T11]],[[T11]],0x1 4903; MIPS32: srl [[T1]],[[T1]],0x18 4904; MIPS32: andi [[T1]],[[T1]],0x1 4905; MIPS32: sll [[T11]],[[T11]],0x1f 4906; MIPS32: sll [[T1]],[[T1]],0x1f 4907; MIPS32: xor [[T11]],[[T11]],[[T1]] 4908; MIPS32: sltiu [[T11]],[[T11]],1 4909; MIPS32: sll [[T11]],[[T11]],0x18 4910; MIPS32: sll [[T0]],[[T0]],0x8 4911; MIPS32: srl [[T0]],[[T0]],0x8 4912; MIPS32: or [[T11]],[[T11]],[[T0]] 4913; MIPS32: move [[T0]],a2 4914; MIPS32: andi [[T0]],[[T0]],0xff 4915; MIPS32: andi [[T0]],[[T0]],0x1 4916; MIPS32: move [[T1]],[[T2]] 4917; MIPS32: andi [[T1]],[[T1]],0xff 4918; MIPS32: andi [[T1]],[[T1]],0x1 4919; MIPS32: sll [[T0]],[[T0]],0x1f 4920; MIPS32: sll [[T1]],[[T1]],0x1f 4921; MIPS32: xor [[T0]],[[T0]],[[T1]] 4922; MIPS32: sltiu [[T0]],[[T0]],1 4923; MIPS32: andi [[T0]],[[T0]],0xff 4924; MIPS32: srl [[T6]],[[T6]],0x8 4925; MIPS32: sll [[T6]],[[T6]],0x8 4926; MIPS32: or [[T0]],[[T0]],[[T6]] 4927; MIPS32: move [[T1]],a2 4928; MIPS32: srl [[T1]],[[T1]],0x8 4929; MIPS32: andi [[T1]],[[T1]],0xff 4930; MIPS32: andi [[T1]],[[T1]],0x1 4931; MIPS32: move [[T4]],[[T2]] 4932; MIPS32: srl [[T4]],[[T4]],0x8 4933; MIPS32: andi [[T4]],[[T4]],0xff 4934; MIPS32: andi [[T4]],[[T4]],0x1 4935; MIPS32: sll [[T1]],[[T1]],0x1f 4936; MIPS32: sll [[T4]],[[T4]],0x1f 4937; MIPS32: xor [[T1]],[[T1]],[[T4]] 4938; MIPS32: sltiu [[T1]],[[T1]],1 4939; MIPS32: andi [[T1]],[[T1]],0xff 4940; MIPS32: sll [[T1]],[[T1]],0x8 4941; MIPS32: lui [[T4]],0xffff 4942; MIPS32: ori [[T4]],[[T4]],0xff 4943; MIPS32: and [[T0]],[[T0]],[[T4]] 4944; MIPS32: or [[T1]],[[T1]],[[T0]] 4945; MIPS32: move [[T0]],a2 4946; MIPS32: srl [[T0]],[[T0]],0x10 4947; MIPS32: andi [[T0]],[[T0]],0xff 4948; MIPS32: andi [[T0]],[[T0]],0x1 4949; MIPS32: move [[T4]],[[T2]] 4950; MIPS32: srl [[T4]],[[T4]],0x10 4951; MIPS32: andi [[T4]],[[T4]],0xff 4952; MIPS32: andi [[T4]],[[T4]],0x1 4953; MIPS32: sll [[T0]],[[T0]],0x1f 4954; MIPS32: sll [[T4]],[[T4]],0x1f 4955; MIPS32: xor [[T0]],[[T0]],[[T4]] 4956; MIPS32: sltiu [[T0]],[[T0]],1 4957; MIPS32: andi [[T0]],[[T0]],0xff 4958; MIPS32: sll [[T0]],[[T0]],0x10 4959; MIPS32: lui [[T4]],0xff00 4960; MIPS32: ori [[T4]],[[T4]],0xffff 4961; MIPS32: and [[T1]],[[T1]],[[T4]] 4962; MIPS32: or [[T0]],[[T0]],[[T1]] 4963; MIPS32: srl [[T12:.*]],a2,0x18 4964; MIPS32: andi [[T12]],[[T12]],0x1 4965; MIPS32: srl [[T2]],[[T2]],0x18 4966; MIPS32: andi [[T2]],[[T2]],0x1 4967; MIPS32: sll [[T12]],[[T12]],0x1f 4968; MIPS32: sll [[T2]],[[T2]],0x1f 4969; MIPS32: xor [[T12]],[[T12]],[[T2]] 4970; MIPS32: sltiu [[T12]],[[T12]],1 4971; MIPS32: sll [[T12]],[[T12]],0x18 4972; MIPS32: sll [[T0]],[[T0]],0x8 4973; MIPS32: srl [[T0]],[[T0]],0x8 4974; MIPS32: or [[T12]],[[T12]],[[T0]] 4975; MIPS32: move [[T0]],a3 4976; MIPS32: andi [[T0]],[[T0]],0xff 4977; MIPS32: andi [[T0]],[[T0]],0x1 4978; MIPS32: move [[T1]],[[T3]] 4979; MIPS32: andi [[T1]],[[T1]],0xff 4980; MIPS32: andi [[T1]],[[T1]],0x1 4981; MIPS32: sll [[T0]],[[T0]],0x1f 4982; MIPS32: sll [[T1]],[[T1]],0x1f 4983; MIPS32: xor [[T0]],[[T0]],[[T1]] 4984; MIPS32: sltiu [[T0]],[[T0]],1 4985; MIPS32: andi [[T0]],[[T0]],0xff 4986; MIPS32: srl [[T7]],[[T7]],0x8 4987; MIPS32: sll [[T7]],[[T7]],0x8 4988; MIPS32: or [[T0]],[[T0]],[[T7]] 4989; MIPS32: move [[T1]],a3 4990; MIPS32: srl [[T1]],[[T1]],0x8 4991; MIPS32: andi [[T1]],[[T1]],0xff 4992; MIPS32: andi [[T1]],[[T1]],0x1 4993; MIPS32: move [[T2]],[[T3]] 4994; MIPS32: srl [[T2]],[[T2]],0x8 4995; MIPS32: andi [[T2]],[[T2]],0xff 4996; MIPS32: andi [[T2]],[[T2]],0x1 4997; MIPS32: sll [[T1]],[[T1]],0x1f 4998; MIPS32: sll [[T2]],[[T2]],0x1f 4999; MIPS32: xor [[T1]],[[T1]],[[T2]] 5000; MIPS32: sltiu [[T1]],[[T1]],1 5001; MIPS32: andi [[T1]],[[T1]],0xff 5002; MIPS32: sll [[T1]],[[T1]],0x8 5003; MIPS32: lui [[T2]],0xffff 5004; MIPS32: ori [[T2]],[[T2]],0xff 5005; MIPS32: and [[T0]],[[T0]],[[T2]] 5006; MIPS32: or [[T1]],[[T1]],[[T0]] 5007; MIPS32: move [[T0]],a3 5008; MIPS32: srl [[T0]],[[T0]],0x10 5009; MIPS32: andi [[T0]],[[T0]],0xff 5010; MIPS32: andi [[T0]],[[T0]],0x1 5011; MIPS32: move [[T2]],[[T3]] 5012; MIPS32: srl [[T2]],[[T2]],0x10 5013; MIPS32: andi [[T2]],[[T2]],0xff 5014; MIPS32: andi [[T2]],[[T2]],0x1 5015; MIPS32: sll [[T0]],[[T0]],0x1f 5016; MIPS32: sll [[T2]],[[T2]],0x1f 5017; MIPS32: xor [[T0]],[[T0]],[[T2]] 5018; MIPS32: sltiu [[T0]],[[T0]],1 5019; MIPS32: andi [[T0]],[[T0]],0xff 5020; MIPS32: sll [[T0]],[[T0]],0x10 5021; MIPS32: lui [[T2]],0xff00 5022; MIPS32: ori [[T2]],[[T2]],0xffff 5023; MIPS32: and [[T1]],[[T1]],[[T2]] 5024; MIPS32: or [[T0]],[[T0]],[[T1]] 5025; MIPS32: srl [[T13:.*]],a3,0x18 5026; MIPS32: andi [[T13]],[[T13]],0x1 5027; MIPS32: srl [[T3]],[[T3]],0x18 5028; MIPS32: andi [[T3]],[[T3]],0x1 5029; MIPS32: sll [[T13]],[[T13]],0x1f 5030; MIPS32: sll [[T3]],[[T3]],0x1f 5031; MIPS32: xor [[T13]],[[T13]],[[T3]] 5032; MIPS32: sltiu [[T13]],[[T13]],1 5033; MIPS32: sll [[T13]],[[T13]],0x18 5034; MIPS32: sll [[T0]],[[T0]],0x8 5035; MIPS32: srl [[T0]],[[T0]],0x8 5036; MIPS32: or [[T13]],[[T13]],[[T0]] 5037; MIPS32: move v0,[[T10]] 5038; MIPS32: move v1,[[T11]] 5039; MIPS32: move a0,[[T12]] 5040; MIPS32: move a1,[[T13]] 5041} 5042 5043define internal <16 x i1> @test_icmp_v16i1_ne(<16 x i1> %a, <16 x i1> %b) { 5044entry: 5045 %res = icmp ne <16 x i1> %a, %b 5046 ret <16 x i1> %res 5047; CHECK-LABEL: test_icmp_v16i1_ne 5048; CHECK: pcmpeqb 5049; CHECK: pxor 5050 5051; MIPS32-LABEL: test_icmp_v16i1_ne 5052; MIPS32: lw [[T0:.*]], 5053; MIPS32: lw [[T1:.*]], 5054; MIPS32: lw [[T2:.*]], 5055; MIPS32: lw [[T3:.*]], 5056; MIPS32: move [[T4:.*]],zero 5057; MIPS32: move [[T5:.*]],zero 5058; MIPS32: move [[T6:.*]],zero 5059; MIPS32: move [[T7:.*]],zero 5060; MIPS32: move [[T8:.*]],a0 5061; MIPS32: andi [[T8]],[[T8]],0xff 5062; MIPS32: andi [[T8]],[[T8]],0x1 5063; MIPS32: move [[T9:.*]],[[T0]] 5064; MIPS32: andi [[T9]],[[T9]],0xff 5065; MIPS32: andi [[T9]],[[T9]],0x1 5066; MIPS32: sll [[T8]],[[T8]],0x1f 5067; MIPS32: sll [[T9]],[[T9]],0x1f 5068; MIPS32: xor [[T8]],[[T8]],[[T9]] 5069; MIPS32: sltu [[T8]],zero,[[T8]] 5070; MIPS32: andi [[T8]],[[T8]],0xff 5071; MIPS32: srl [[T4]],[[T4]],0x8 5072; MIPS32: sll [[T4]],[[T4]],0x8 5073; MIPS32: or [[T8]],[[T8]],[[T4]] 5074; MIPS32: move [[T4]],a0 5075; MIPS32: srl [[T4]],[[T4]],0x8 5076; MIPS32: andi [[T4]],[[T4]],0xff 5077; MIPS32: andi [[T4]],[[T4]],0x1 5078; MIPS32: move [[T9]],[[T0]] 5079; MIPS32: srl [[T9]],[[T9]],0x8 5080; MIPS32: andi [[T9]],[[T9]],0xff 5081; MIPS32: andi [[T9]],[[T9]],0x1 5082; MIPS32: sll [[T4]],[[T4]],0x1f 5083; MIPS32: sll [[T9]],[[T9]],0x1f 5084; MIPS32: xor [[T4]],[[T4]],[[T9]] 5085; MIPS32: sltu [[T4]],zero,[[T4]] 5086; MIPS32: andi [[T4]],[[T4]],0xff 5087; MIPS32: sll [[T4]],[[T4]],0x8 5088; MIPS32: lui [[T9]],0xffff 5089; MIPS32: ori [[T9]],[[T9]],0xff 5090; MIPS32: and [[T8]],[[T8]],[[T9]] 5091; MIPS32: or [[T4]],[[T4]],[[T8]] 5092; MIPS32: move [[T8]],a0 5093; MIPS32: srl [[T8]],[[T8]],0x10 5094; MIPS32: andi [[T8]],[[T8]],0xff 5095; MIPS32: andi [[T8]],[[T8]],0x1 5096; MIPS32: move [[T9]],[[T0]] 5097; MIPS32: srl [[T9]],[[T9]],0x10 5098; MIPS32: andi [[T9]],[[T9]],0xff 5099; MIPS32: andi [[T9]],[[T9]],0x1 5100; MIPS32: sll [[T8]],[[T8]],0x1f 5101; MIPS32: sll [[T9]],[[T9]],0x1f 5102; MIPS32: xor [[T8]],[[T8]],[[T9]] 5103; MIPS32: sltu [[T8]],zero,[[T8]] 5104; MIPS32: andi [[T8]],[[T8]],0xff 5105; MIPS32: sll [[T8]],[[T8]],0x10 5106; MIPS32: lui [[T9]],0xff00 5107; MIPS32: ori [[T9]],[[T9]],0xffff 5108; MIPS32: and [[T4]],[[T4]],[[T9]] 5109; MIPS32: or [[T8]],[[T8]],[[T4]] 5110; MIPS32: srl [[T10:.*]],a0,0x18 5111; MIPS32: andi [[T10]],[[T10]],0x1 5112; MIPS32: srl [[T0]],[[T0]],0x18 5113; MIPS32: andi [[T0]],[[T0]],0x1 5114; MIPS32: sll [[T10]],[[T10]],0x1f 5115; MIPS32: sll [[T0]],[[T0]],0x1f 5116; MIPS32: xor [[T10]],[[T10]],[[T0]] 5117; MIPS32: sltu [[T10]],zero,[[T10]] 5118; MIPS32: sll [[T10]],[[T10]],0x18 5119; MIPS32: sll [[T8]],[[T8]],0x8 5120; MIPS32: srl [[T8]],[[T8]],0x8 5121; MIPS32: or [[T10]],[[T10]],[[T8]] 5122; MIPS32: move [[T0]],a1 5123; MIPS32: andi [[T0]],[[T0]],0xff 5124; MIPS32: andi [[T0]],[[T0]],0x1 5125; MIPS32: move [[T4]],[[T1]] 5126; MIPS32: andi [[T4]],[[T4]],0xff 5127; MIPS32: andi [[T4]],[[T4]],0x1 5128; MIPS32: sll [[T0]],[[T0]],0x1f 5129; MIPS32: sll [[T4]],[[T4]],0x1f 5130; MIPS32: xor [[T0]],[[T0]],[[T4]] 5131; MIPS32: sltu [[T0]],zero,[[T0]] 5132; MIPS32: andi [[T0]],[[T0]],0xff 5133; MIPS32: srl [[T5]],[[T5]],0x8 5134; MIPS32: sll [[T5]],[[T5]],0x8 5135; MIPS32: or [[T0]],[[T0]],[[T5]] 5136; MIPS32: move [[T4]],a1 5137; MIPS32: srl [[T4]],[[T4]],0x8 5138; MIPS32: andi [[T4]],[[T4]],0xff 5139; MIPS32: andi [[T4]],[[T4]],0x1 5140; MIPS32: move [[T5]],[[T1]] 5141; MIPS32: srl [[T5]],[[T5]],0x8 5142; MIPS32: andi [[T5]],[[T5]],0xff 5143; MIPS32: andi [[T5]],[[T5]],0x1 5144; MIPS32: sll [[T4]],[[T4]],0x1f 5145; MIPS32: sll [[T5]],[[T5]],0x1f 5146; MIPS32: xor [[T4]],[[T4]],[[T5]] 5147; MIPS32: sltu [[T4]],zero,[[T4]] 5148; MIPS32: andi [[T4]],[[T4]],0xff 5149; MIPS32: sll [[T4]],[[T4]],0x8 5150; MIPS32: lui [[T5]],0xffff 5151; MIPS32: ori [[T5]],[[T5]],0xff 5152; MIPS32: and [[T0]],[[T0]],[[T5]] 5153; MIPS32: or [[T4]],[[T4]],[[T0]] 5154; MIPS32: move [[T0]],a1 5155; MIPS32: srl [[T0]],[[T0]],0x10 5156; MIPS32: andi [[T0]],[[T0]],0xff 5157; MIPS32: andi [[T0]],[[T0]],0x1 5158; MIPS32: move [[T5]],[[T1]] 5159; MIPS32: srl [[T5]],[[T5]],0x10 5160; MIPS32: andi [[T5]],[[T5]],0xff 5161; MIPS32: andi [[T5]],[[T5]],0x1 5162; MIPS32: sll [[T0]],[[T0]],0x1f 5163; MIPS32: sll [[T5]],[[T5]],0x1f 5164; MIPS32: xor [[T0]],[[T0]],[[T5]] 5165; MIPS32: sltu [[T0]],zero,[[T0]] 5166; MIPS32: andi [[T0]],[[T0]],0xff 5167; MIPS32: sll [[T0]],[[T0]],0x10 5168; MIPS32: lui [[T5]],0xff00 5169; MIPS32: ori [[T5]],[[T5]],0xffff 5170; MIPS32: and [[T4]],[[T4]],[[T5]] 5171; MIPS32: or [[T0]],[[T0]],[[T4]] 5172; MIPS32: srl [[T11:.*]],a1,0x18 5173; MIPS32: andi [[T11]],[[T11]],0x1 5174; MIPS32: srl [[T1]],[[T1]],0x18 5175; MIPS32: andi [[T1]],[[T1]],0x1 5176; MIPS32: sll [[T11]],[[T11]],0x1f 5177; MIPS32: sll [[T1]],[[T1]],0x1f 5178; MIPS32: xor [[T11]],[[T11]],[[T1]] 5179; MIPS32: sltu [[T11]],zero,[[T11]] 5180; MIPS32: sll [[T11]],[[T11]],0x18 5181; MIPS32: sll [[T0]],[[T0]],0x8 5182; MIPS32: srl [[T0]],[[T0]],0x8 5183; MIPS32: or [[T11]],[[T11]],[[T0]] 5184; MIPS32: move [[T0]],a2 5185; MIPS32: andi [[T0]],[[T0]],0xff 5186; MIPS32: andi [[T0]],[[T0]],0x1 5187; MIPS32: move [[T1]],[[T2]] 5188; MIPS32: andi [[T1]],[[T1]],0xff 5189; MIPS32: andi [[T1]],[[T1]],0x1 5190; MIPS32: sll [[T0]],[[T0]],0x1f 5191; MIPS32: sll [[T1]],[[T1]],0x1f 5192; MIPS32: xor [[T0]],[[T0]],[[T1]] 5193; MIPS32: sltu [[T0]],zero,[[T0]] 5194; MIPS32: andi [[T0]],[[T0]],0xff 5195; MIPS32: srl [[T6]],[[T6]],0x8 5196; MIPS32: sll [[T6]],[[T6]],0x8 5197; MIPS32: or [[T0]],[[T0]],[[T6]] 5198; MIPS32: move [[T1]],a2 5199; MIPS32: srl [[T1]],[[T1]],0x8 5200; MIPS32: andi [[T1]],[[T1]],0xff 5201; MIPS32: andi [[T1]],[[T1]],0x1 5202; MIPS32: move [[T4]],[[T2]] 5203; MIPS32: srl [[T4]],[[T4]],0x8 5204; MIPS32: andi [[T4]],[[T4]],0xff 5205; MIPS32: andi [[T4]],[[T4]],0x1 5206; MIPS32: sll [[T1]],[[T1]],0x1f 5207; MIPS32: sll [[T4]],[[T4]],0x1f 5208; MIPS32: xor [[T1]],[[T1]],[[T4]] 5209; MIPS32: sltu [[T1]],zero,[[T1]] 5210; MIPS32: andi [[T1]],[[T1]],0xff 5211; MIPS32: sll [[T1]],[[T1]],0x8 5212; MIPS32: lui [[T4]],0xffff 5213; MIPS32: ori [[T4]],[[T4]],0xff 5214; MIPS32: and [[T0]],[[T0]],[[T4]] 5215; MIPS32: or [[T1]],[[T1]],[[T0]] 5216; MIPS32: move [[T0]],a2 5217; MIPS32: srl [[T0]],[[T0]],0x10 5218; MIPS32: andi [[T0]],[[T0]],0xff 5219; MIPS32: andi [[T0]],[[T0]],0x1 5220; MIPS32: move [[T4]],[[T2]] 5221; MIPS32: srl [[T4]],[[T4]],0x10 5222; MIPS32: andi [[T4]],[[T4]],0xff 5223; MIPS32: andi [[T4]],[[T4]],0x1 5224; MIPS32: sll [[T0]],[[T0]],0x1f 5225; MIPS32: sll [[T4]],[[T4]],0x1f 5226; MIPS32: xor [[T0]],[[T0]],[[T4]] 5227; MIPS32: sltu [[T0]],zero,[[T0]] 5228; MIPS32: andi [[T0]],[[T0]],0xff 5229; MIPS32: sll [[T0]],[[T0]],0x10 5230; MIPS32: lui [[T4]],0xff00 5231; MIPS32: ori [[T4]],[[T4]],0xffff 5232; MIPS32: and [[T1]],[[T1]],[[T4]] 5233; MIPS32: or [[T0]],[[T0]],[[T1]] 5234; MIPS32: srl [[T12:.*]],a2,0x18 5235; MIPS32: andi [[T12]],[[T12]],0x1 5236; MIPS32: srl [[T2]],[[T2]],0x18 5237; MIPS32: andi [[T2]],[[T2]],0x1 5238; MIPS32: sll [[T12]],[[T12]],0x1f 5239; MIPS32: sll [[T2]],[[T2]],0x1f 5240; MIPS32: xor [[T12]],[[T12]],[[T2]] 5241; MIPS32: sltu [[T12]],zero,[[T12]] 5242; MIPS32: sll [[T12]],[[T12]],0x18 5243; MIPS32: sll [[T0]],[[T0]],0x8 5244; MIPS32: srl [[T0]],[[T0]],0x8 5245; MIPS32: or [[T12]],[[T12]],[[T0]] 5246; MIPS32: move [[T0]],a3 5247; MIPS32: andi [[T0]],[[T0]],0xff 5248; MIPS32: andi [[T0]],[[T0]],0x1 5249; MIPS32: move [[T1]],[[T3]] 5250; MIPS32: andi [[T1]],[[T1]],0xff 5251; MIPS32: andi [[T1]],[[T1]],0x1 5252; MIPS32: sll [[T0]],[[T0]],0x1f 5253; MIPS32: sll [[T1]],[[T1]],0x1f 5254; MIPS32: xor [[T0]],[[T0]],[[T1]] 5255; MIPS32: sltu [[T0]],zero,[[T0]] 5256; MIPS32: andi [[T0]],[[T0]],0xff 5257; MIPS32: srl [[T7]],[[T7]],0x8 5258; MIPS32: sll [[T7]],[[T7]],0x8 5259; MIPS32: or [[T0]],[[T0]],[[T7]] 5260; MIPS32: move [[T1]],a3 5261; MIPS32: srl [[T1]],[[T1]],0x8 5262; MIPS32: andi [[T1]],[[T1]],0xff 5263; MIPS32: andi [[T1]],[[T1]],0x1 5264; MIPS32: move [[T2]],[[T3]] 5265; MIPS32: srl [[T2]],[[T2]],0x8 5266; MIPS32: andi [[T2]],[[T2]],0xff 5267; MIPS32: andi [[T2]],[[T2]],0x1 5268; MIPS32: sll [[T1]],[[T1]],0x1f 5269; MIPS32: sll [[T2]],[[T2]],0x1f 5270; MIPS32: xor [[T1]],[[T1]],[[T2]] 5271; MIPS32: sltu [[T1]],zero,[[T1]] 5272; MIPS32: andi [[T1]],[[T1]],0xff 5273; MIPS32: sll [[T1]],[[T1]],0x8 5274; MIPS32: lui [[T2]],0xffff 5275; MIPS32: ori [[T2]],[[T2]],0xff 5276; MIPS32: and [[T0]],[[T0]],[[T2]] 5277; MIPS32: or [[T1]],[[T1]],[[T0]] 5278; MIPS32: move [[T0]],a3 5279; MIPS32: srl [[T0]],[[T0]],0x10 5280; MIPS32: andi [[T0]],[[T0]],0xff 5281; MIPS32: andi [[T0]],[[T0]],0x1 5282; MIPS32: move [[T2]],[[T3]] 5283; MIPS32: srl [[T2]],[[T2]],0x10 5284; MIPS32: andi [[T2]],[[T2]],0xff 5285; MIPS32: andi [[T2]],[[T2]],0x1 5286; MIPS32: sll [[T0]],[[T0]],0x1f 5287; MIPS32: sll [[T2]],[[T2]],0x1f 5288; MIPS32: xor [[T0]],[[T0]],[[T2]] 5289; MIPS32: sltu [[T0]],zero,[[T0]] 5290; MIPS32: andi [[T0]],[[T0]],0xff 5291; MIPS32: sll [[T0]],[[T0]],0x10 5292; MIPS32: lui [[T2]],0xff00 5293; MIPS32: ori [[T2]],[[T2]],0xffff 5294; MIPS32: and [[T1]],[[T1]],[[T2]] 5295; MIPS32: or [[T0]],[[T0]],[[T1]] 5296; MIPS32: srl [[T13:.*]],a3,0x18 5297; MIPS32: andi [[T13]],[[T13]],0x1 5298; MIPS32: srl [[T3]],[[T3]],0x18 5299; MIPS32: andi [[T3]],[[T3]],0x1 5300; MIPS32: sll [[T13]],[[T13]],0x1f 5301; MIPS32: sll [[T3]],[[T3]],0x1f 5302; MIPS32: xor [[T13]],[[T13]],[[T3]] 5303; MIPS32: sltu [[T13]],zero,[[T13]] 5304; MIPS32: sll [[T13]],[[T13]],0x18 5305; MIPS32: sll [[T0]],[[T0]],0x8 5306; MIPS32: srl [[T0]],[[T0]],0x8 5307; MIPS32: or [[T13]],[[T13]],[[T0]] 5308; MIPS32: move v0,[[T10]] 5309; MIPS32: move v1,[[T11]] 5310; MIPS32: move a0,[[T12]] 5311; MIPS32: move a1,[[T13]] 5312} 5313 5314define internal <16 x i1> @test_icmp_v16i1_sgt(<16 x i1> %a, <16 x i1> %b) { 5315entry: 5316 %res = icmp sgt <16 x i1> %a, %b 5317 ret <16 x i1> %res 5318; CHECK-LABEL: test_icmp_v16i1_sgt 5319; CHECK: pcmpgtb 5320 5321; MIPS32-LABEL: test_icmp_v16i1_sgt 5322; MIPS32: lw [[T0:.*]], 5323; MIPS32: lw [[T1:.*]], 5324; MIPS32: lw [[T2:.*]], 5325; MIPS32: lw [[T3:.*]], 5326; MIPS32: move [[T4:.*]],zero 5327; MIPS32: move [[T5:.*]],zero 5328; MIPS32: move [[T6:.*]],zero 5329; MIPS32: move [[T7:.*]],zero 5330; MIPS32: move [[T8:.*]],a0 5331; MIPS32: andi [[T8]],[[T8]],0xff 5332; MIPS32: andi [[T8]],[[T8]],0x1 5333; MIPS32: move [[T9:.*]],[[T0]] 5334; MIPS32: andi [[T9]],[[T9]],0xff 5335; MIPS32: andi [[T9]],[[T9]],0x1 5336; MIPS32: sll [[T8]],[[T8]],0x1f 5337; MIPS32: sll [[T9]],[[T9]],0x1f 5338; MIPS32: slt [[T9]],[[T9]],[[T8]] 5339; MIPS32: andi [[T9]],[[T9]],0xff 5340; MIPS32: srl [[T4]],[[T4]],0x8 5341; MIPS32: sll [[T4]],[[T4]],0x8 5342; MIPS32: or [[T9]],[[T9]],[[T4]] 5343; MIPS32: move [[T4]],a0 5344; MIPS32: srl [[T4]],[[T4]],0x8 5345; MIPS32: andi [[T4]],[[T4]],0xff 5346; MIPS32: andi [[T4]],[[T4]],0x1 5347; MIPS32: move [[T8]],[[T0]] 5348; MIPS32: srl [[T8]],[[T8]],0x8 5349; MIPS32: andi [[T8]],[[T8]],0xff 5350; MIPS32: andi [[T8]],[[T8]],0x1 5351; MIPS32: sll [[T4]],[[T4]],0x1f 5352; MIPS32: sll [[T8]],[[T8]],0x1f 5353; MIPS32: slt [[T8]],[[T8]],[[T4]] 5354; MIPS32: andi [[T8]],[[T8]],0xff 5355; MIPS32: sll [[T8]],[[T8]],0x8 5356; MIPS32: lui [[T4]],0xffff 5357; MIPS32: ori [[T4]],[[T4]],0xff 5358; MIPS32: and [[T9]],[[T9]],[[T4]] 5359; MIPS32: or [[T8]],[[T8]],[[T9]] 5360; MIPS32: move [[T4]],a0 5361; MIPS32: srl [[T4]],[[T4]],0x10 5362; MIPS32: andi [[T4]],[[T4]],0xff 5363; MIPS32: andi [[T4]],[[T4]],0x1 5364; MIPS32: move [[T9]],[[T0]] 5365; MIPS32: srl [[T9]],[[T9]],0x10 5366; MIPS32: andi [[T9]],[[T9]],0xff 5367; MIPS32: andi [[T9]],[[T9]],0x1 5368; MIPS32: sll [[T4]],[[T4]],0x1f 5369; MIPS32: sll [[T9]],[[T9]],0x1f 5370; MIPS32: slt [[T9]],[[T9]],[[T4]] 5371; MIPS32: andi [[T9]],[[T9]],0xff 5372; MIPS32: sll [[T9]],[[T9]],0x10 5373; MIPS32: lui [[T4]],0xff00 5374; MIPS32: ori [[T4]],[[T4]],0xffff 5375; MIPS32: and [[T8]],[[T8]],[[T4]] 5376; MIPS32: or [[T9]],[[T9]],[[T8]] 5377; MIPS32: srl [[T10:.*]],a0,0x18 5378; MIPS32: andi [[T10]],[[T10]],0x1 5379; MIPS32: srl [[T0]],[[T0]],0x18 5380; MIPS32: andi [[T0]],[[T0]],0x1 5381; MIPS32: sll [[T10]],[[T10]],0x1f 5382; MIPS32: sll [[T0]],[[T0]],0x1f 5383; MIPS32: slt [[T0]],[[T0]],[[T10]] 5384; MIPS32: sll [[T0]],[[T0]],0x18 5385; MIPS32: sll [[T9]],[[T9]],0x8 5386; MIPS32: srl [[T9]],[[T9]],0x8 5387; MIPS32: or v0,[[T0]],[[T9]] 5388; MIPS32: move [[T10]],a1 5389; MIPS32: andi [[T10]],[[T10]],0xff 5390; MIPS32: andi [[T10]],[[T10]],0x1 5391; MIPS32: move [[T4]],[[T1]] 5392; MIPS32: andi [[T4]],[[T4]],0xff 5393; MIPS32: andi [[T4]],[[T4]],0x1 5394; MIPS32: sll [[T10]],[[T10]],0x1f 5395; MIPS32: sll [[T4]],[[T4]],0x1f 5396; MIPS32: slt [[T4]],[[T4]],[[T10]] 5397; MIPS32: andi [[T4]],[[T4]],0xff 5398; MIPS32: srl [[T5]],[[T5]],0x8 5399; MIPS32: sll [[T5]],[[T5]],0x8 5400; MIPS32: or [[T4]],[[T4]],[[T5]] 5401; MIPS32: move [[T10]],a1 5402; MIPS32: srl [[T10]],[[T10]],0x8 5403; MIPS32: andi [[T10]],[[T10]],0xff 5404; MIPS32: andi [[T10]],[[T10]],0x1 5405; MIPS32: move [[T5]],[[T1]] 5406; MIPS32: srl [[T5]],[[T5]],0x8 5407; MIPS32: andi [[T5]],[[T5]],0xff 5408; MIPS32: andi [[T5]],[[T5]],0x1 5409; MIPS32: sll [[T10]],[[T10]],0x1f 5410; MIPS32: sll [[T5]],[[T5]],0x1f 5411; MIPS32: slt [[T5]],[[T5]],[[T10]] 5412; MIPS32: andi [[T5]],[[T5]],0xff 5413; MIPS32: sll [[T5]],[[T5]],0x8 5414; MIPS32: lui [[T10]],0xffff 5415; MIPS32: ori [[T10]],[[T10]],0xff 5416; MIPS32: and [[T4]],[[T4]],[[T10]] 5417; MIPS32: or [[T5]],[[T5]],[[T4]] 5418; MIPS32: move [[T10]],a1 5419; MIPS32: srl [[T10]],[[T10]],0x10 5420; MIPS32: andi [[T10]],[[T10]],0xff 5421; MIPS32: andi [[T10]],[[T10]],0x1 5422; MIPS32: move [[T4]],[[T1]] 5423; MIPS32: srl [[T4]],[[T4]],0x10 5424; MIPS32: andi [[T4]],[[T4]],0xff 5425; MIPS32: andi [[T4]],[[T4]],0x1 5426; MIPS32: sll [[T10]],[[T10]],0x1f 5427; MIPS32: sll [[T4]],[[T4]],0x1f 5428; MIPS32: slt [[T4]],[[T4]],[[T10]] 5429; MIPS32: andi [[T4]],[[T4]],0xff 5430; MIPS32: sll [[T4]],[[T4]],0x10 5431; MIPS32: lui [[T10]],0xff00 5432; MIPS32: ori [[T10]],[[T10]],0xffff 5433; MIPS32: and [[T5]],[[T5]],[[T10]] 5434; MIPS32: or [[T4]],[[T4]],[[T5]] 5435; MIPS32: srl [[T11:.*]],a1,0x18 5436; MIPS32: andi [[T11]],[[T11]],0x1 5437; MIPS32: srl [[T1]],[[T1]],0x18 5438; MIPS32: andi [[T1]],[[T1]],0x1 5439; MIPS32: sll [[T11]],[[T11]],0x1f 5440; MIPS32: sll [[T1]],[[T1]],0x1f 5441; MIPS32: slt [[T1]],[[T1]],[[T11]] 5442; MIPS32: sll [[T1]],[[T1]],0x18 5443; MIPS32: sll [[T4]],[[T4]],0x8 5444; MIPS32: srl [[T4]],[[T4]],0x8 5445; MIPS32: or v1,[[T1]],[[T4]] 5446; MIPS32: move [[T10]],a2 5447; MIPS32: andi [[T10]],[[T10]],0xff 5448; MIPS32: andi [[T10]],[[T10]],0x1 5449; MIPS32: move [[T11]],[[T2]] 5450; MIPS32: andi [[T11]],[[T11]],0xff 5451; MIPS32: andi [[T11]],[[T11]],0x1 5452; MIPS32: sll [[T10]],[[T10]],0x1f 5453; MIPS32: sll [[T11]],[[T11]],0x1f 5454; MIPS32: slt [[T11]],[[T11]],[[T10]] 5455; MIPS32: andi [[T11]],[[T11]],0xff 5456; MIPS32: srl [[T6]],[[T6]],0x8 5457; MIPS32: sll [[T6]],[[T6]],0x8 5458; MIPS32: or [[T11]],[[T11]],[[T6]] 5459; MIPS32: move [[T10]],a2 5460; MIPS32: srl [[T10]],[[T10]],0x8 5461; MIPS32: andi [[T10]],[[T10]],0xff 5462; MIPS32: andi [[T10]],[[T10]],0x1 5463; MIPS32: move [[T4]],[[T2]] 5464; MIPS32: srl [[T4]],[[T4]],0x8 5465; MIPS32: andi [[T4]],[[T4]],0xff 5466; MIPS32: andi [[T4]],[[T4]],0x1 5467; MIPS32: sll [[T10]],[[T10]],0x1f 5468; MIPS32: sll [[T4]],[[T4]],0x1f 5469; MIPS32: slt [[T4]],[[T4]],[[T10]] 5470; MIPS32: andi [[T4]],[[T4]],0xff 5471; MIPS32: sll [[T4]],[[T4]],0x8 5472; MIPS32: lui [[T10]],0xffff 5473; MIPS32: ori [[T10]],[[T10]],0xff 5474; MIPS32: and [[T11]],[[T11]],[[T10]] 5475; MIPS32: or [[T4]],[[T4]],[[T11]] 5476; MIPS32: move [[T10]],a2 5477; MIPS32: srl [[T10]],[[T10]],0x10 5478; MIPS32: andi [[T10]],[[T10]],0xff 5479; MIPS32: andi [[T10]],[[T10]],0x1 5480; MIPS32: move [[T11]],[[T2]] 5481; MIPS32: srl [[T11]],[[T11]],0x10 5482; MIPS32: andi [[T11]],[[T11]],0xff 5483; MIPS32: andi [[T11]],[[T11]],0x1 5484; MIPS32: sll [[T10]],[[T10]],0x1f 5485; MIPS32: sll [[T11]],[[T11]],0x1f 5486; MIPS32: slt [[T11]],[[T11]],[[T10]] 5487; MIPS32: andi [[T11]],[[T11]],0xff 5488; MIPS32: sll [[T11]],[[T11]],0x10 5489; MIPS32: lui [[T10]],0xff00 5490; MIPS32: ori [[T10]],[[T10]],0xffff 5491; MIPS32: and [[T4]],[[T4]],[[T10]] 5492; MIPS32: or [[T11]],[[T11]],[[T4]] 5493; MIPS32: srl [[T12:.*]],a2,0x18 5494; MIPS32: andi [[T12]],[[T12]],0x1 5495; MIPS32: srl [[T2]],[[T2]],0x18 5496; MIPS32: andi [[T2]],[[T2]],0x1 5497; MIPS32: sll [[T12]],[[T12]],0x1f 5498; MIPS32: sll [[T2]],[[T2]],0x1f 5499; MIPS32: slt [[T2]],[[T2]],[[T12]] 5500; MIPS32: sll [[T2]],[[T2]],0x18 5501; MIPS32: sll [[T11]],[[T11]],0x8 5502; MIPS32: srl [[T11]],[[T11]],0x8 5503; MIPS32: or [[T2]],[[T2]],[[T11]] 5504; MIPS32: move [[T10]],a3 5505; MIPS32: andi [[T10]],[[T10]],0xff 5506; MIPS32: andi [[T10]],[[T10]],0x1 5507; MIPS32: move [[T11]],[[T3]] 5508; MIPS32: andi [[T11]],[[T11]],0xff 5509; MIPS32: andi [[T11]],[[T11]],0x1 5510; MIPS32: sll [[T10]],[[T10]],0x1f 5511; MIPS32: sll [[T11]],[[T11]],0x1f 5512; MIPS32: slt [[T11]],[[T11]],[[T10]] 5513; MIPS32: andi [[T11]],[[T11]],0xff 5514; MIPS32: srl [[T7]],[[T7]],0x8 5515; MIPS32: sll [[T7]],[[T7]],0x8 5516; MIPS32: or [[T11]],[[T11]],[[T7]] 5517; MIPS32: move [[T10]],a3 5518; MIPS32: srl [[T10]],[[T10]],0x8 5519; MIPS32: andi [[T10]],[[T10]],0xff 5520; MIPS32: andi [[T10]],[[T10]],0x1 5521; MIPS32: move [[T12]],[[T3]] 5522; MIPS32: srl [[T12]],[[T12]],0x8 5523; MIPS32: andi [[T12]],[[T12]],0xff 5524; MIPS32: andi [[T12]],[[T12]],0x1 5525; MIPS32: sll [[T10]],[[T10]],0x1f 5526; MIPS32: sll [[T12]],[[T12]],0x1f 5527; MIPS32: slt [[T12]],[[T12]],[[T10]] 5528; MIPS32: andi [[T12]],[[T12]],0xff 5529; MIPS32: sll [[T12]],[[T12]],0x8 5530; MIPS32: lui [[T10]],0xffff 5531; MIPS32: ori [[T10]],[[T10]],0xff 5532; MIPS32: and [[T11]],[[T11]],[[T10]] 5533; MIPS32: or [[T12]],[[T12]],[[T11]] 5534; MIPS32: move [[T10]],a3 5535; MIPS32: srl [[T10]],[[T10]],0x10 5536; MIPS32: andi [[T10]],[[T10]],0xff 5537; MIPS32: andi [[T10]],[[T10]],0x1 5538; MIPS32: move [[T11]],[[T3]] 5539; MIPS32: srl [[T11]],[[T11]],0x10 5540; MIPS32: andi [[T11]],[[T11]],0xff 5541; MIPS32: andi [[T11]],[[T11]],0x1 5542; MIPS32: sll [[T10]],[[T10]],0x1f 5543; MIPS32: sll [[T11]],[[T11]],0x1f 5544; MIPS32: slt [[T11]],[[T11]],[[T10]] 5545; MIPS32: andi [[T11]],[[T11]],0xff 5546; MIPS32: sll [[T11]],[[T11]],0x10 5547; MIPS32: lui [[T10]],0xff00 5548; MIPS32: ori [[T10]],[[T10]],0xffff 5549; MIPS32: and [[T12]],[[T12]],[[T10]] 5550; MIPS32: or [[T11]],[[T11]],[[T12]] 5551; MIPS32: srl [[T13:.*]],a3,0x18 5552; MIPS32: andi [[T13]],[[T13]],0x1 5553; MIPS32: srl [[T3]],[[T3]],0x18 5554; MIPS32: andi [[T3]],[[T3]],0x1 5555; MIPS32: sll [[T13]],[[T13]],0x1f 5556; MIPS32: sll [[T3]],[[T3]],0x1f 5557; MIPS32: slt [[T3]],[[T3]],[[T13]] 5558; MIPS32: sll [[T3]],[[T3]],0x18 5559; MIPS32: sll [[T11]],[[T11]],0x8 5560; MIPS32: srl [[T11]],[[T11]],0x8 5561; MIPS32: or [[T3]],[[T3]],[[T11]] 5562; MIPS32: move a0,[[T2]] 5563; MIPS32: move a1,[[T3]] 5564} 5565 5566define internal <16 x i1> @test_icmp_v16i1_sle(<16 x i1> %a, <16 x i1> %b) { 5567entry: 5568 %res = icmp sle <16 x i1> %a, %b 5569 ret <16 x i1> %res 5570; CHECK-LABEL: test_icmp_v16i1_sle 5571; CHECK: pcmpgtb 5572; CHECK: pxor 5573 5574; MIPS32-LABEL: test_icmp_v16i1_sle 5575; MIPS32: lw [[T0:.*]], 5576; MIPS32: lw [[T1:.*]], 5577; MIPS32: lw [[T2:.*]], 5578; MIPS32: lw [[T3:.*]], 5579; MIPS32: move [[T4:.*]],zero 5580; MIPS32: move [[T5:.*]],zero 5581; MIPS32: move [[T6:.*]],zero 5582; MIPS32: move [[T7:.*]],zero 5583; MIPS32: move [[T8:.*]],a0 5584; MIPS32: andi [[T8]],[[T8]],0xff 5585; MIPS32: andi [[T8]],[[T8]],0x1 5586; MIPS32: move [[T9:.*]],[[T0]] 5587; MIPS32: andi [[T9]],[[T9]],0xff 5588; MIPS32: andi [[T9]],[[T9]],0x1 5589; MIPS32: sll [[T8]],[[T8]],0x1f 5590; MIPS32: sll [[T9]],[[T9]],0x1f 5591; MIPS32: slt [[T9]],[[T9]],[[T8]] 5592; MIPS32: xori [[T9]],[[T9]],0x1 5593; MIPS32: andi [[T9]],[[T9]],0xff 5594; MIPS32: srl [[T4]],[[T4]],0x8 5595; MIPS32: sll [[T4]],[[T4]],0x8 5596; MIPS32: or [[T9]],[[T9]],[[T4]] 5597; MIPS32: move [[T4]],a0 5598; MIPS32: srl [[T4]],[[T4]],0x8 5599; MIPS32: andi [[T4]],[[T4]],0xff 5600; MIPS32: andi [[T4]],[[T4]],0x1 5601; MIPS32: move [[T8]],[[T0]] 5602; MIPS32: srl [[T8]],[[T8]],0x8 5603; MIPS32: andi [[T8]],[[T8]],0xff 5604; MIPS32: andi [[T8]],[[T8]],0x1 5605; MIPS32: sll [[T4]],[[T4]],0x1f 5606; MIPS32: sll [[T8]],[[T8]],0x1f 5607; MIPS32: slt [[T8]],[[T8]],[[T4]] 5608; MIPS32: xori [[T8]],[[T8]],0x1 5609; MIPS32: andi [[T8]],[[T8]],0xff 5610; MIPS32: sll [[T8]],[[T8]],0x8 5611; MIPS32: lui [[T4]],0xffff 5612; MIPS32: ori [[T4]],[[T4]],0xff 5613; MIPS32: and [[T9]],[[T9]],[[T4]] 5614; MIPS32: or [[T8]],[[T8]],[[T9]] 5615; MIPS32: move [[T4]],a0 5616; MIPS32: srl [[T4]],[[T4]],0x10 5617; MIPS32: andi [[T4]],[[T4]],0xff 5618; MIPS32: andi [[T4]],[[T4]],0x1 5619; MIPS32: move [[T9]],[[T0]] 5620; MIPS32: srl [[T9]],[[T9]],0x10 5621; MIPS32: andi [[T9]],[[T9]],0xff 5622; MIPS32: andi [[T9]],[[T9]],0x1 5623; MIPS32: sll [[T4]],[[T4]],0x1f 5624; MIPS32: sll [[T9]],[[T9]],0x1f 5625; MIPS32: slt [[T9]],[[T9]],[[T4]] 5626; MIPS32: xori [[T9]],[[T9]],0x1 5627; MIPS32: andi [[T9]],[[T9]],0xff 5628; MIPS32: sll [[T9]],[[T9]],0x10 5629; MIPS32: lui [[T4]],0xff00 5630; MIPS32: ori [[T4]],[[T4]],0xffff 5631; MIPS32: and [[T8]],[[T8]],[[T4]] 5632; MIPS32: or [[T9]],[[T9]],[[T8]] 5633; MIPS32: srl [[T10:.*]],a0,0x18 5634; MIPS32: andi [[T10]],[[T10]],0x1 5635; MIPS32: srl [[T0]],[[T0]],0x18 5636; MIPS32: andi [[T0]],[[T0]],0x1 5637; MIPS32: sll [[T10]],[[T10]],0x1f 5638; MIPS32: sll [[T0]],[[T0]],0x1f 5639; MIPS32: slt [[T0]],[[T0]],[[T10]] 5640; MIPS32: xori [[T0]],[[T0]],0x1 5641; MIPS32: sll [[T0]],[[T0]],0x18 5642; MIPS32: sll [[T9]],[[T9]],0x8 5643; MIPS32: srl [[T9]],[[T9]],0x8 5644; MIPS32: or v0,[[T0]],[[T9]] 5645; MIPS32: move [[T10]],a1 5646; MIPS32: andi [[T10]],[[T10]],0xff 5647; MIPS32: andi [[T10]],[[T10]],0x1 5648; MIPS32: move [[T4]],[[T1]] 5649; MIPS32: andi [[T4]],[[T4]],0xff 5650; MIPS32: andi [[T4]],[[T4]],0x1 5651; MIPS32: sll [[T10]],[[T10]],0x1f 5652; MIPS32: sll [[T4]],[[T4]],0x1f 5653; MIPS32: slt [[T4]],[[T4]],[[T10]] 5654; MIPS32: xori [[T4]],[[T4]],0x1 5655; MIPS32: andi [[T4]],[[T4]],0xff 5656; MIPS32: srl [[T5]],[[T5]],0x8 5657; MIPS32: sll [[T5]],[[T5]],0x8 5658; MIPS32: or [[T4]],[[T4]],[[T5]] 5659; MIPS32: move [[T10]],a1 5660; MIPS32: srl [[T10]],[[T10]],0x8 5661; MIPS32: andi [[T10]],[[T10]],0xff 5662; MIPS32: andi [[T10]],[[T10]],0x1 5663; MIPS32: move [[T5]],[[T1]] 5664; MIPS32: srl [[T5]],[[T5]],0x8 5665; MIPS32: andi [[T5]],[[T5]],0xff 5666; MIPS32: andi [[T5]],[[T5]],0x1 5667; MIPS32: sll [[T10]],[[T10]],0x1f 5668; MIPS32: sll [[T5]],[[T5]],0x1f 5669; MIPS32: slt [[T5]],[[T5]],[[T10]] 5670; MIPS32: xori [[T5]],[[T5]],0x1 5671; MIPS32: andi [[T5]],[[T5]],0xff 5672; MIPS32: sll [[T5]],[[T5]],0x8 5673; MIPS32: lui [[T10]],0xffff 5674; MIPS32: ori [[T10]],[[T10]],0xff 5675; MIPS32: and [[T4]],[[T4]],[[T10]] 5676; MIPS32: or [[T5]],[[T5]],[[T4]] 5677; MIPS32: move [[T10]],a1 5678; MIPS32: srl [[T10]],[[T10]],0x10 5679; MIPS32: andi [[T10]],[[T10]],0xff 5680; MIPS32: andi [[T10]],[[T10]],0x1 5681; MIPS32: move [[T4]],[[T1]] 5682; MIPS32: srl [[T4]],[[T4]],0x10 5683; MIPS32: andi [[T4]],[[T4]],0xff 5684; MIPS32: andi [[T4]],[[T4]],0x1 5685; MIPS32: sll [[T10]],[[T10]],0x1f 5686; MIPS32: sll [[T4]],[[T4]],0x1f 5687; MIPS32: slt [[T4]],[[T4]],[[T10]] 5688; MIPS32: xori [[T4]],[[T4]],0x1 5689; MIPS32: andi [[T4]],[[T4]],0xff 5690; MIPS32: sll [[T4]],[[T4]],0x10 5691; MIPS32: lui [[T10]],0xff00 5692; MIPS32: ori [[T10]],[[T10]],0xffff 5693; MIPS32: and [[T5]],[[T5]],[[T10]] 5694; MIPS32: or [[T4]],[[T4]],[[T5]] 5695; MIPS32: srl [[T11:.*]],a1,0x18 5696; MIPS32: andi [[T11]],[[T11]],0x1 5697; MIPS32: srl [[T1]],[[T1]],0x18 5698; MIPS32: andi [[T1]],[[T1]],0x1 5699; MIPS32: sll [[T11]],[[T11]],0x1f 5700; MIPS32: sll [[T1]],[[T1]],0x1f 5701; MIPS32: slt [[T1]],[[T1]],[[T11]] 5702; MIPS32: xori [[T1]],[[T1]],0x1 5703; MIPS32: sll [[T1]],[[T1]],0x18 5704; MIPS32: sll [[T4]],[[T4]],0x8 5705; MIPS32: srl [[T4]],[[T4]],0x8 5706; MIPS32: or v1,[[T1]],[[T4]] 5707; MIPS32: move [[T10]],a2 5708; MIPS32: andi [[T10]],[[T10]],0xff 5709; MIPS32: andi [[T10]],[[T10]],0x1 5710; MIPS32: move [[T11]],[[T2]] 5711; MIPS32: andi [[T11]],[[T11]],0xff 5712; MIPS32: andi [[T11]],[[T11]],0x1 5713; MIPS32: sll [[T10]],[[T10]],0x1f 5714; MIPS32: sll [[T11]],[[T11]],0x1f 5715; MIPS32: slt [[T11]],[[T11]],[[T10]] 5716; MIPS32: xori [[T11]],[[T11]],0x1 5717; MIPS32: andi [[T11]],[[T11]],0xff 5718; MIPS32: srl [[T6]],[[T6]],0x8 5719; MIPS32: sll [[T6]],[[T6]],0x8 5720; MIPS32: or [[T11]],[[T11]],[[T6]] 5721; MIPS32: move [[T10]],a2 5722; MIPS32: srl [[T10]],[[T10]],0x8 5723; MIPS32: andi [[T10]],[[T10]],0xff 5724; MIPS32: andi [[T10]],[[T10]],0x1 5725; MIPS32: move [[T4]],[[T2]] 5726; MIPS32: srl [[T4]],[[T4]],0x8 5727; MIPS32: andi [[T4]],[[T4]],0xff 5728; MIPS32: andi [[T4]],[[T4]],0x1 5729; MIPS32: sll [[T10]],[[T10]],0x1f 5730; MIPS32: sll [[T4]],[[T4]],0x1f 5731; MIPS32: slt [[T4]],[[T4]],[[T10]] 5732; MIPS32: xori [[T4]],[[T4]],0x1 5733; MIPS32: andi [[T4]],[[T4]],0xff 5734; MIPS32: sll [[T4]],[[T4]],0x8 5735; MIPS32: lui [[T10]],0xffff 5736; MIPS32: ori [[T10]],[[T10]],0xff 5737; MIPS32: and [[T11]],[[T11]],[[T10]] 5738; MIPS32: or [[T4]],[[T4]],[[T11]] 5739; MIPS32: move [[T10]],a2 5740; MIPS32: srl [[T10]],[[T10]],0x10 5741; MIPS32: andi [[T10]],[[T10]],0xff 5742; MIPS32: andi [[T10]],[[T10]],0x1 5743; MIPS32: move [[T11]],[[T2]] 5744; MIPS32: srl [[T11]],[[T11]],0x10 5745; MIPS32: andi [[T11]],[[T11]],0xff 5746; MIPS32: andi [[T11]],[[T11]],0x1 5747; MIPS32: sll [[T10]],[[T10]],0x1f 5748; MIPS32: sll [[T11]],[[T11]],0x1f 5749; MIPS32: slt [[T11]],[[T11]],[[T10]] 5750; MIPS32: xori [[T11]],[[T11]],0x1 5751; MIPS32: andi [[T11]],[[T11]],0xff 5752; MIPS32: sll [[T11]],[[T11]],0x10 5753; MIPS32: lui [[T10]],0xff00 5754; MIPS32: ori [[T10]],[[T10]],0xffff 5755; MIPS32: and [[T4]],[[T4]],[[T10]] 5756; MIPS32: or [[T11]],[[T11]],[[T4]] 5757; MIPS32: srl [[T12:.*]],a2,0x18 5758; MIPS32: andi [[T12]],[[T12]],0x1 5759; MIPS32: srl [[T2]],[[T2]],0x18 5760; MIPS32: andi [[T2]],[[T2]],0x1 5761; MIPS32: sll [[T12]],[[T12]],0x1f 5762; MIPS32: sll [[T2]],[[T2]],0x1f 5763; MIPS32: slt [[T2]],[[T2]],[[T12]] 5764; MIPS32: xori [[T2]],[[T2]],0x1 5765; MIPS32: sll [[T2]],[[T2]],0x18 5766; MIPS32: sll [[T11]],[[T11]],0x8 5767; MIPS32: srl [[T11]],[[T11]],0x8 5768; MIPS32: or [[T2]],[[T2]],[[T11]] 5769; MIPS32: move [[T10]],a3 5770; MIPS32: andi [[T10]],[[T10]],0xff 5771; MIPS32: andi [[T10]],[[T10]],0x1 5772; MIPS32: move [[T11]],[[T3]] 5773; MIPS32: andi [[T11]],[[T11]],0xff 5774; MIPS32: andi [[T11]],[[T11]],0x1 5775; MIPS32: sll [[T10]],[[T10]],0x1f 5776; MIPS32: sll [[T11]],[[T11]],0x1f 5777; MIPS32: slt [[T11]],[[T11]],[[T10]] 5778; MIPS32: xori [[T11]],[[T11]],0x1 5779; MIPS32: andi [[T11]],[[T11]],0xff 5780; MIPS32: srl [[T7]],[[T7]],0x8 5781; MIPS32: sll [[T7]],[[T7]],0x8 5782; MIPS32: or [[T11]],[[T11]],[[T7]] 5783; MIPS32: move [[T10]],a3 5784; MIPS32: srl [[T10]],[[T10]],0x8 5785; MIPS32: andi [[T10]],[[T10]],0xff 5786; MIPS32: andi [[T10]],[[T10]],0x1 5787; MIPS32: move [[T12]],[[T3]] 5788; MIPS32: srl [[T12]],[[T12]],0x8 5789; MIPS32: andi [[T12]],[[T12]],0xff 5790; MIPS32: andi [[T12]],[[T12]],0x1 5791; MIPS32: sll [[T10]],[[T10]],0x1f 5792; MIPS32: sll [[T12]],[[T12]],0x1f 5793; MIPS32: slt [[T12]],[[T12]],[[T10]] 5794; MIPS32: xori [[T12]],[[T12]],0x1 5795; MIPS32: andi [[T12]],[[T12]],0xff 5796; MIPS32: sll [[T12]],[[T12]],0x8 5797; MIPS32: lui [[T10]],0xffff 5798; MIPS32: ori [[T10]],[[T10]],0xff 5799; MIPS32: and [[T11]],[[T11]],[[T10]] 5800; MIPS32: or [[T12]],[[T12]],[[T11]] 5801; MIPS32: move [[T10]],a3 5802; MIPS32: srl [[T10]],[[T10]],0x10 5803; MIPS32: andi [[T10]],[[T10]],0xff 5804; MIPS32: andi [[T10]],[[T10]],0x1 5805; MIPS32: move [[T11]],[[T3]] 5806; MIPS32: srl [[T11]],[[T11]],0x10 5807; MIPS32: andi [[T11]],[[T11]],0xff 5808; MIPS32: andi [[T11]],[[T11]],0x1 5809; MIPS32: sll [[T10]],[[T10]],0x1f 5810; MIPS32: sll [[T11]],[[T11]],0x1f 5811; MIPS32: slt [[T11]],[[T11]],[[T10]] 5812; MIPS32: xori [[T11]],[[T11]],0x1 5813; MIPS32: andi [[T11]],[[T11]],0xff 5814; MIPS32: sll [[T11]],[[T11]],0x10 5815; MIPS32: lui [[T10]],0xff00 5816; MIPS32: ori [[T10]],[[T10]],0xffff 5817; MIPS32: and [[T12]],[[T12]],[[T10]] 5818; MIPS32: or [[T11]],[[T11]],[[T12]] 5819; MIPS32: srl [[T13:.*]],a3,0x18 5820; MIPS32: andi [[T13]],[[T13]],0x1 5821; MIPS32: srl [[T3]],[[T3]],0x18 5822; MIPS32: andi [[T3]],[[T3]],0x1 5823; MIPS32: sll [[T13]],[[T13]],0x1f 5824; MIPS32: sll [[T3]],[[T3]],0x1f 5825; MIPS32: slt [[T3]],[[T3]],[[T13]] 5826; MIPS32: xori [[T3]],[[T3]],0x1 5827; MIPS32: sll [[T3]],[[T3]],0x18 5828; MIPS32: sll [[T11]],[[T11]],0x8 5829; MIPS32: srl [[T11]],[[T11]],0x8 5830; MIPS32: or [[T3]],[[T3]],[[T11]] 5831; MIPS32: move a0,[[T2]] 5832; MIPS32: move a1,[[T3]] 5833} 5834 5835define internal <16 x i1> @test_icmp_v16i1_slt(<16 x i1> %a, <16 x i1> %b) { 5836entry: 5837 %res = icmp slt <16 x i1> %a, %b 5838 ret <16 x i1> %res 5839; CHECK-LABEL: test_icmp_v16i1_slt 5840; CHECK: pcmpgtb 5841 5842; MIPS32-LABEL: test_icmp_v16i1_slt 5843; MIPS32: lw [[T0:.*]], 5844; MIPS32: lw [[T1:.*]], 5845; MIPS32: lw [[T2:.*]], 5846; MIPS32: lw [[T3:.*]], 5847; MIPS32: move [[T4:.*]],zero 5848; MIPS32: move [[T5:.*]],zero 5849; MIPS32: move [[T6:.*]],zero 5850; MIPS32: move [[T7:.*]],zero 5851; MIPS32: move [[T8:.*]],a0 5852; MIPS32: andi [[T8]],[[T8]],0xff 5853; MIPS32: andi [[T8]],[[T8]],0x1 5854; MIPS32: move [[T9:.*]],[[T0]] 5855; MIPS32: andi [[T9]],[[T9]],0xff 5856; MIPS32: andi [[T9]],[[T9]],0x1 5857; MIPS32: sll [[T8]],[[T8]],0x1f 5858; MIPS32: sll [[T9]],[[T9]],0x1f 5859; MIPS32: slt [[T8]],[[T8]],[[T9]] 5860; MIPS32: andi [[T8]],[[T8]],0xff 5861; MIPS32: srl [[T4]],[[T4]],0x8 5862; MIPS32: sll [[T4]],[[T4]],0x8 5863; MIPS32: or [[T8]],[[T8]],[[T4]] 5864; MIPS32: move [[T4]],a0 5865; MIPS32: srl [[T4]],[[T4]],0x8 5866; MIPS32: andi [[T4]],[[T4]],0xff 5867; MIPS32: andi [[T4]],[[T4]],0x1 5868; MIPS32: move [[T9]],[[T0]] 5869; MIPS32: srl [[T9]],[[T9]],0x8 5870; MIPS32: andi [[T9]],[[T9]],0xff 5871; MIPS32: andi [[T9]],[[T9]],0x1 5872; MIPS32: sll [[T4]],[[T4]],0x1f 5873; MIPS32: sll [[T9]],[[T9]],0x1f 5874; MIPS32: slt [[T4]],[[T4]],[[T9]] 5875; MIPS32: andi [[T4]],[[T4]],0xff 5876; MIPS32: sll [[T4]],[[T4]],0x8 5877; MIPS32: lui [[T9]],0xffff 5878; MIPS32: ori [[T9]],[[T9]],0xff 5879; MIPS32: and [[T8]],[[T8]],[[T9]] 5880; MIPS32: or [[T4]],[[T4]],[[T8]] 5881; MIPS32: move [[T8]],a0 5882; MIPS32: srl [[T8]],[[T8]],0x10 5883; MIPS32: andi [[T8]],[[T8]],0xff 5884; MIPS32: andi [[T8]],[[T8]],0x1 5885; MIPS32: move [[T9]],[[T0]] 5886; MIPS32: srl [[T9]],[[T9]],0x10 5887; MIPS32: andi [[T9]],[[T9]],0xff 5888; MIPS32: andi [[T9]],[[T9]],0x1 5889; MIPS32: sll [[T8]],[[T8]],0x1f 5890; MIPS32: sll [[T9]],[[T9]],0x1f 5891; MIPS32: slt [[T8]],[[T8]],[[T9]] 5892; MIPS32: andi [[T8]],[[T8]],0xff 5893; MIPS32: sll [[T8]],[[T8]],0x10 5894; MIPS32: lui [[T9]],0xff00 5895; MIPS32: ori [[T9]],[[T9]],0xffff 5896; MIPS32: and [[T4]],[[T4]],[[T9]] 5897; MIPS32: or [[T8]],[[T8]],[[T4]] 5898; MIPS32: srl [[T10:.*]],a0,0x18 5899; MIPS32: andi [[T10]],[[T10]],0x1 5900; MIPS32: srl [[T0]],[[T0]],0x18 5901; MIPS32: andi [[T0]],[[T0]],0x1 5902; MIPS32: sll [[T10]],[[T10]],0x1f 5903; MIPS32: sll [[T0]],[[T0]],0x1f 5904; MIPS32: slt [[T10]],[[T10]],[[T0]] 5905; MIPS32: sll [[T10]],[[T10]],0x18 5906; MIPS32: sll [[T8]],[[T8]],0x8 5907; MIPS32: srl [[T8]],[[T8]],0x8 5908; MIPS32: or [[T10]],[[T10]],[[T8]] 5909; MIPS32: move [[T0]],a1 5910; MIPS32: andi [[T0]],[[T0]],0xff 5911; MIPS32: andi [[T0]],[[T0]],0x1 5912; MIPS32: move [[T4]],[[T1]] 5913; MIPS32: andi [[T4]],[[T4]],0xff 5914; MIPS32: andi [[T4]],[[T4]],0x1 5915; MIPS32: sll [[T0]],[[T0]],0x1f 5916; MIPS32: sll [[T4]],[[T4]],0x1f 5917; MIPS32: slt [[T0]],[[T0]],[[T4]] 5918; MIPS32: andi [[T0]],[[T0]],0xff 5919; MIPS32: srl [[T5]],[[T5]],0x8 5920; MIPS32: sll [[T5]],[[T5]],0x8 5921; MIPS32: or [[T0]],[[T0]],[[T5]] 5922; MIPS32: move [[T4]],a1 5923; MIPS32: srl [[T4]],[[T4]],0x8 5924; MIPS32: andi [[T4]],[[T4]],0xff 5925; MIPS32: andi [[T4]],[[T4]],0x1 5926; MIPS32: move [[T5]],[[T1]] 5927; MIPS32: srl [[T5]],[[T5]],0x8 5928; MIPS32: andi [[T5]],[[T5]],0xff 5929; MIPS32: andi [[T5]],[[T5]],0x1 5930; MIPS32: sll [[T4]],[[T4]],0x1f 5931; MIPS32: sll [[T5]],[[T5]],0x1f 5932; MIPS32: slt [[T4]],[[T4]],[[T5]] 5933; MIPS32: andi [[T4]],[[T4]],0xff 5934; MIPS32: sll [[T4]],[[T4]],0x8 5935; MIPS32: lui [[T5]],0xffff 5936; MIPS32: ori [[T5]],[[T5]],0xff 5937; MIPS32: and [[T0]],[[T0]],[[T5]] 5938; MIPS32: or [[T4]],[[T4]],[[T0]] 5939; MIPS32: move [[T0]],a1 5940; MIPS32: srl [[T0]],[[T0]],0x10 5941; MIPS32: andi [[T0]],[[T0]],0xff 5942; MIPS32: andi [[T0]],[[T0]],0x1 5943; MIPS32: move [[T5]],[[T1]] 5944; MIPS32: srl [[T5]],[[T5]],0x10 5945; MIPS32: andi [[T5]],[[T5]],0xff 5946; MIPS32: andi [[T5]],[[T5]],0x1 5947; MIPS32: sll [[T0]],[[T0]],0x1f 5948; MIPS32: sll [[T5]],[[T5]],0x1f 5949; MIPS32: slt [[T0]],[[T0]],[[T5]] 5950; MIPS32: andi [[T0]],[[T0]],0xff 5951; MIPS32: sll [[T0]],[[T0]],0x10 5952; MIPS32: lui [[T5]],0xff00 5953; MIPS32: ori [[T5]],[[T5]],0xffff 5954; MIPS32: and [[T4]],[[T4]],[[T5]] 5955; MIPS32: or [[T0]],[[T0]],[[T4]] 5956; MIPS32: srl [[T11:.*]],a1,0x18 5957; MIPS32: andi [[T11]],[[T11]],0x1 5958; MIPS32: srl [[T1]],[[T1]],0x18 5959; MIPS32: andi [[T1]],[[T1]],0x1 5960; MIPS32: sll [[T11]],[[T11]],0x1f 5961; MIPS32: sll [[T1]],[[T1]],0x1f 5962; MIPS32: slt [[T11]],[[T11]],[[T1]] 5963; MIPS32: sll [[T11]],[[T11]],0x18 5964; MIPS32: sll [[T0]],[[T0]],0x8 5965; MIPS32: srl [[T0]],[[T0]],0x8 5966; MIPS32: or [[T11]],[[T11]],[[T0]] 5967; MIPS32: move [[T0]],a2 5968; MIPS32: andi [[T0]],[[T0]],0xff 5969; MIPS32: andi [[T0]],[[T0]],0x1 5970; MIPS32: move [[T1]],[[T2]] 5971; MIPS32: andi [[T1]],[[T1]],0xff 5972; MIPS32: andi [[T1]],[[T1]],0x1 5973; MIPS32: sll [[T0]],[[T0]],0x1f 5974; MIPS32: sll [[T1]],[[T1]],0x1f 5975; MIPS32: slt [[T0]],[[T0]],[[T1]] 5976; MIPS32: andi [[T0]],[[T0]],0xff 5977; MIPS32: srl [[T6]],[[T6]],0x8 5978; MIPS32: sll [[T6]],[[T6]],0x8 5979; MIPS32: or [[T0]],[[T0]],[[T6]] 5980; MIPS32: move [[T1]],a2 5981; MIPS32: srl [[T1]],[[T1]],0x8 5982; MIPS32: andi [[T1]],[[T1]],0xff 5983; MIPS32: andi [[T1]],[[T1]],0x1 5984; MIPS32: move [[T4]],[[T2]] 5985; MIPS32: srl [[T4]],[[T4]],0x8 5986; MIPS32: andi [[T4]],[[T4]],0xff 5987; MIPS32: andi [[T4]],[[T4]],0x1 5988; MIPS32: sll [[T1]],[[T1]],0x1f 5989; MIPS32: sll [[T4]],[[T4]],0x1f 5990; MIPS32: slt [[T1]],[[T1]],[[T4]] 5991; MIPS32: andi [[T1]],[[T1]],0xff 5992; MIPS32: sll [[T1]],[[T1]],0x8 5993; MIPS32: lui [[T4]],0xffff 5994; MIPS32: ori [[T4]],[[T4]],0xff 5995; MIPS32: and [[T0]],[[T0]],[[T4]] 5996; MIPS32: or [[T1]],[[T1]],[[T0]] 5997; MIPS32: move [[T0]],a2 5998; MIPS32: srl [[T0]],[[T0]],0x10 5999; MIPS32: andi [[T0]],[[T0]],0xff 6000; MIPS32: andi [[T0]],[[T0]],0x1 6001; MIPS32: move [[T4]],[[T2]] 6002; MIPS32: srl [[T4]],[[T4]],0x10 6003; MIPS32: andi [[T4]],[[T4]],0xff 6004; MIPS32: andi [[T4]],[[T4]],0x1 6005; MIPS32: sll [[T0]],[[T0]],0x1f 6006; MIPS32: sll [[T4]],[[T4]],0x1f 6007; MIPS32: slt [[T0]],[[T0]],[[T4]] 6008; MIPS32: andi [[T0]],[[T0]],0xff 6009; MIPS32: sll [[T0]],[[T0]],0x10 6010; MIPS32: lui [[T4]],0xff00 6011; MIPS32: ori [[T4]],[[T4]],0xffff 6012; MIPS32: and [[T1]],[[T1]],[[T4]] 6013; MIPS32: or [[T0]],[[T0]],[[T1]] 6014; MIPS32: srl [[T12:.*]],a2,0x18 6015; MIPS32: andi [[T12]],[[T12]],0x1 6016; MIPS32: srl [[T2]],[[T2]],0x18 6017; MIPS32: andi [[T2]],[[T2]],0x1 6018; MIPS32: sll [[T12]],[[T12]],0x1f 6019; MIPS32: sll [[T2]],[[T2]],0x1f 6020; MIPS32: slt [[T12]],[[T12]],[[T2]] 6021; MIPS32: sll [[T12]],[[T12]],0x18 6022; MIPS32: sll [[T0]],[[T0]],0x8 6023; MIPS32: srl [[T0]],[[T0]],0x8 6024; MIPS32: or [[T12]],[[T12]],[[T0]] 6025; MIPS32: move [[T0]],a3 6026; MIPS32: andi [[T0]],[[T0]],0xff 6027; MIPS32: andi [[T0]],[[T0]],0x1 6028; MIPS32: move [[T1]],[[T3]] 6029; MIPS32: andi [[T1]],[[T1]],0xff 6030; MIPS32: andi [[T1]],[[T1]],0x1 6031; MIPS32: sll [[T0]],[[T0]],0x1f 6032; MIPS32: sll [[T1]],[[T1]],0x1f 6033; MIPS32: slt [[T0]],[[T0]],[[T1]] 6034; MIPS32: andi [[T0]],[[T0]],0xff 6035; MIPS32: srl [[T7]],[[T7]],0x8 6036; MIPS32: sll [[T7]],[[T7]],0x8 6037; MIPS32: or [[T0]],[[T0]],[[T7]] 6038; MIPS32: move [[T1]],a3 6039; MIPS32: srl [[T1]],[[T1]],0x8 6040; MIPS32: andi [[T1]],[[T1]],0xff 6041; MIPS32: andi [[T1]],[[T1]],0x1 6042; MIPS32: move [[T2]],[[T3]] 6043; MIPS32: srl [[T2]],[[T2]],0x8 6044; MIPS32: andi [[T2]],[[T2]],0xff 6045; MIPS32: andi [[T2]],[[T2]],0x1 6046; MIPS32: sll [[T1]],[[T1]],0x1f 6047; MIPS32: sll [[T2]],[[T2]],0x1f 6048; MIPS32: slt [[T1]],[[T1]],[[T2]] 6049; MIPS32: andi [[T1]],[[T1]],0xff 6050; MIPS32: sll [[T1]],[[T1]],0x8 6051; MIPS32: lui [[T2]],0xffff 6052; MIPS32: ori [[T2]],[[T2]],0xff 6053; MIPS32: and [[T0]],[[T0]],[[T2]] 6054; MIPS32: or [[T1]],[[T1]],[[T0]] 6055; MIPS32: move [[T0]],a3 6056; MIPS32: srl [[T0]],[[T0]],0x10 6057; MIPS32: andi [[T0]],[[T0]],0xff 6058; MIPS32: andi [[T0]],[[T0]],0x1 6059; MIPS32: move [[T2]],[[T3]] 6060; MIPS32: srl [[T2]],[[T2]],0x10 6061; MIPS32: andi [[T2]],[[T2]],0xff 6062; MIPS32: andi [[T2]],[[T2]],0x1 6063; MIPS32: sll [[T0]],[[T0]],0x1f 6064; MIPS32: sll [[T2]],[[T2]],0x1f 6065; MIPS32: slt [[T0]],[[T0]],[[T2]] 6066; MIPS32: andi [[T0]],[[T0]],0xff 6067; MIPS32: sll [[T0]],[[T0]],0x10 6068; MIPS32: lui [[T2]],0xff00 6069; MIPS32: ori [[T2]],[[T2]],0xffff 6070; MIPS32: and [[T1]],[[T1]],[[T2]] 6071; MIPS32: or [[T0]],[[T0]],[[T1]] 6072; MIPS32: srl [[T13:.*]],a3,0x18 6073; MIPS32: andi [[T13]],[[T13]],0x1 6074; MIPS32: srl [[T3]],[[T3]],0x18 6075; MIPS32: andi [[T3]],[[T3]],0x1 6076; MIPS32: sll [[T13]],[[T13]],0x1f 6077; MIPS32: sll [[T3]],[[T3]],0x1f 6078; MIPS32: slt [[T13]],[[T13]],[[T3]] 6079; MIPS32: sll [[T13]],[[T13]],0x18 6080; MIPS32: sll [[T0]],[[T0]],0x8 6081; MIPS32: srl [[T0]],[[T0]],0x8 6082; MIPS32: or [[T13]],[[T13]],[[T0]] 6083; MIPS32: move v0,[[T10]] 6084; MIPS32: move v1,[[T11]] 6085; MIPS32: move a0,[[T12]] 6086; MIPS32: move a1,[[T13]] 6087} 6088 6089define internal <16 x i1> @test_icmp_v16i1_uge(<16 x i1> %a, <16 x i1> %b) { 6090entry: 6091 %res = icmp uge <16 x i1> %a, %b 6092 ret <16 x i1> %res 6093; CHECK-LABEL: test_icmp_v16i1_uge 6094; CHECK: pxor 6095; CHECK: pcmpgtb 6096; CHECK: pxor 6097 6098; MIPS32-LABEL: test_icmp_v16i1_uge 6099; MIPS32: lw [[T0:.*]], 6100; MIPS32: lw [[T1:.*]], 6101; MIPS32: lw [[T2:.*]], 6102; MIPS32: lw [[T3:.*]], 6103; MIPS32: move [[T4:.*]],zero 6104; MIPS32: move [[T5:.*]],zero 6105; MIPS32: move [[T6:.*]],zero 6106; MIPS32: move [[T7:.*]],zero 6107; MIPS32: move [[T8:.*]],a0 6108; MIPS32: andi [[T8]],[[T8]],0xff 6109; MIPS32: andi [[T8]],[[T8]],0x1 6110; MIPS32: move [[T9:.*]],[[T0]] 6111; MIPS32: andi [[T9]],[[T9]],0xff 6112; MIPS32: andi [[T9]],[[T9]],0x1 6113; MIPS32: sll [[T8]],[[T8]],0x1f 6114; MIPS32: sll [[T9]],[[T9]],0x1f 6115; MIPS32: sltu [[T8]],[[T8]],[[T9]] 6116; MIPS32: xori [[T8]],[[T8]],0x1 6117; MIPS32: andi [[T8]],[[T8]],0xff 6118; MIPS32: srl [[T4]],[[T4]],0x8 6119; MIPS32: sll [[T4]],[[T4]],0x8 6120; MIPS32: or [[T8]],[[T8]],[[T4]] 6121; MIPS32: move [[T4]],a0 6122; MIPS32: srl [[T4]],[[T4]],0x8 6123; MIPS32: andi [[T4]],[[T4]],0xff 6124; MIPS32: andi [[T4]],[[T4]],0x1 6125; MIPS32: move [[T9]],[[T0]] 6126; MIPS32: srl [[T9]],[[T9]],0x8 6127; MIPS32: andi [[T9]],[[T9]],0xff 6128; MIPS32: andi [[T9]],[[T9]],0x1 6129; MIPS32: sll [[T4]],[[T4]],0x1f 6130; MIPS32: sll [[T9]],[[T9]],0x1f 6131; MIPS32: sltu [[T4]],[[T4]],[[T9]] 6132; MIPS32: xori [[T4]],[[T4]],0x1 6133; MIPS32: andi [[T4]],[[T4]],0xff 6134; MIPS32: sll [[T4]],[[T4]],0x8 6135; MIPS32: lui [[T9]],0xffff 6136; MIPS32: ori [[T9]],[[T9]],0xff 6137; MIPS32: and [[T8]],[[T8]],[[T9]] 6138; MIPS32: or [[T4]],[[T4]],[[T8]] 6139; MIPS32: move [[T8]],a0 6140; MIPS32: srl [[T8]],[[T8]],0x10 6141; MIPS32: andi [[T8]],[[T8]],0xff 6142; MIPS32: andi [[T8]],[[T8]],0x1 6143; MIPS32: move [[T9]],[[T0]] 6144; MIPS32: srl [[T9]],[[T9]],0x10 6145; MIPS32: andi [[T9]],[[T9]],0xff 6146; MIPS32: andi [[T9]],[[T9]],0x1 6147; MIPS32: sll [[T8]],[[T8]],0x1f 6148; MIPS32: sll [[T9]],[[T9]],0x1f 6149; MIPS32: sltu [[T8]],[[T8]],[[T9]] 6150; MIPS32: xori [[T8]],[[T8]],0x1 6151; MIPS32: andi [[T8]],[[T8]],0xff 6152; MIPS32: sll [[T8]],[[T8]],0x10 6153; MIPS32: lui [[T9]],0xff00 6154; MIPS32: ori [[T9]],[[T9]],0xffff 6155; MIPS32: and [[T4]],[[T4]],[[T9]] 6156; MIPS32: or [[T8]],[[T8]],[[T4]] 6157; MIPS32: srl [[T10:.*]],a0,0x18 6158; MIPS32: andi [[T10]],[[T10]],0x1 6159; MIPS32: srl [[T0]],[[T0]],0x18 6160; MIPS32: andi [[T0]],[[T0]],0x1 6161; MIPS32: sll [[T10]],[[T10]],0x1f 6162; MIPS32: sll [[T0]],[[T0]],0x1f 6163; MIPS32: sltu [[T10]],[[T10]],[[T0]] 6164; MIPS32: xori [[T10]],[[T10]],0x1 6165; MIPS32: sll [[T10]],[[T10]],0x18 6166; MIPS32: sll [[T8]],[[T8]],0x8 6167; MIPS32: srl [[T8]],[[T8]],0x8 6168; MIPS32: or [[T10]],[[T10]],[[T8]] 6169; MIPS32: move [[T0]],a1 6170; MIPS32: andi [[T0]],[[T0]],0xff 6171; MIPS32: andi [[T0]],[[T0]],0x1 6172; MIPS32: move [[T4]],[[T1]] 6173; MIPS32: andi [[T4]],[[T4]],0xff 6174; MIPS32: andi [[T4]],[[T4]],0x1 6175; MIPS32: sll [[T0]],[[T0]],0x1f 6176; MIPS32: sll [[T4]],[[T4]],0x1f 6177; MIPS32: sltu [[T0]],[[T0]],[[T4]] 6178; MIPS32: xori [[T0]],[[T0]],0x1 6179; MIPS32: andi [[T0]],[[T0]],0xff 6180; MIPS32: srl [[T5]],[[T5]],0x8 6181; MIPS32: sll [[T5]],[[T5]],0x8 6182; MIPS32: or [[T0]],[[T0]],[[T5]] 6183; MIPS32: move [[T4]],a1 6184; MIPS32: srl [[T4]],[[T4]],0x8 6185; MIPS32: andi [[T4]],[[T4]],0xff 6186; MIPS32: andi [[T4]],[[T4]],0x1 6187; MIPS32: move [[T5]],[[T1]] 6188; MIPS32: srl [[T5]],[[T5]],0x8 6189; MIPS32: andi [[T5]],[[T5]],0xff 6190; MIPS32: andi [[T5]],[[T5]],0x1 6191; MIPS32: sll [[T4]],[[T4]],0x1f 6192; MIPS32: sll [[T5]],[[T5]],0x1f 6193; MIPS32: sltu [[T4]],[[T4]],[[T5]] 6194; MIPS32: xori [[T4]],[[T4]],0x1 6195; MIPS32: andi [[T4]],[[T4]],0xff 6196; MIPS32: sll [[T4]],[[T4]],0x8 6197; MIPS32: lui [[T5]],0xffff 6198; MIPS32: ori [[T5]],[[T5]],0xff 6199; MIPS32: and [[T0]],[[T0]],[[T5]] 6200; MIPS32: or [[T4]],[[T4]],[[T0]] 6201; MIPS32: move [[T0]],a1 6202; MIPS32: srl [[T0]],[[T0]],0x10 6203; MIPS32: andi [[T0]],[[T0]],0xff 6204; MIPS32: andi [[T0]],[[T0]],0x1 6205; MIPS32: move [[T5]],[[T1]] 6206; MIPS32: srl [[T5]],[[T5]],0x10 6207; MIPS32: andi [[T5]],[[T5]],0xff 6208; MIPS32: andi [[T5]],[[T5]],0x1 6209; MIPS32: sll [[T0]],[[T0]],0x1f 6210; MIPS32: sll [[T5]],[[T5]],0x1f 6211; MIPS32: sltu [[T0]],[[T0]],[[T5]] 6212; MIPS32: xori [[T0]],[[T0]],0x1 6213; MIPS32: andi [[T0]],[[T0]],0xff 6214; MIPS32: sll [[T0]],[[T0]],0x10 6215; MIPS32: lui [[T5]],0xff00 6216; MIPS32: ori [[T5]],[[T5]],0xffff 6217; MIPS32: and [[T4]],[[T4]],[[T5]] 6218; MIPS32: or [[T0]],[[T0]],[[T4]] 6219; MIPS32: srl [[T11:.*]],a1,0x18 6220; MIPS32: andi [[T11]],[[T11]],0x1 6221; MIPS32: srl [[T1]],[[T1]],0x18 6222; MIPS32: andi [[T1]],[[T1]],0x1 6223; MIPS32: sll [[T11]],[[T11]],0x1f 6224; MIPS32: sll [[T1]],[[T1]],0x1f 6225; MIPS32: sltu [[T11]],[[T11]],[[T1]] 6226; MIPS32: xori [[T11]],[[T11]],0x1 6227; MIPS32: sll [[T11]],[[T11]],0x18 6228; MIPS32: sll [[T0]],[[T0]],0x8 6229; MIPS32: srl [[T0]],[[T0]],0x8 6230; MIPS32: or [[T11]],[[T11]],[[T0]] 6231; MIPS32: move [[T0]],a2 6232; MIPS32: andi [[T0]],[[T0]],0xff 6233; MIPS32: andi [[T0]],[[T0]],0x1 6234; MIPS32: move [[T1]],[[T2]] 6235; MIPS32: andi [[T1]],[[T1]],0xff 6236; MIPS32: andi [[T1]],[[T1]],0x1 6237; MIPS32: sll [[T0]],[[T0]],0x1f 6238; MIPS32: sll [[T1]],[[T1]],0x1f 6239; MIPS32: sltu [[T0]],[[T0]],[[T1]] 6240; MIPS32: xori [[T0]],[[T0]],0x1 6241; MIPS32: andi [[T0]],[[T0]],0xff 6242; MIPS32: srl [[T6]],[[T6]],0x8 6243; MIPS32: sll [[T6]],[[T6]],0x8 6244; MIPS32: or [[T0]],[[T0]],[[T6]] 6245; MIPS32: move [[T1]],a2 6246; MIPS32: srl [[T1]],[[T1]],0x8 6247; MIPS32: andi [[T1]],[[T1]],0xff 6248; MIPS32: andi [[T1]],[[T1]],0x1 6249; MIPS32: move [[T4]],[[T2]] 6250; MIPS32: srl [[T4]],[[T4]],0x8 6251; MIPS32: andi [[T4]],[[T4]],0xff 6252; MIPS32: andi [[T4]],[[T4]],0x1 6253; MIPS32: sll [[T1]],[[T1]],0x1f 6254; MIPS32: sll [[T4]],[[T4]],0x1f 6255; MIPS32: sltu [[T1]],[[T1]],[[T4]] 6256; MIPS32: xori [[T1]],[[T1]],0x1 6257; MIPS32: andi [[T1]],[[T1]],0xff 6258; MIPS32: sll [[T1]],[[T1]],0x8 6259; MIPS32: lui [[T4]],0xffff 6260; MIPS32: ori [[T4]],[[T4]],0xff 6261; MIPS32: and [[T0]],[[T0]],[[T4]] 6262; MIPS32: or [[T1]],[[T1]],[[T0]] 6263; MIPS32: move [[T0]],a2 6264; MIPS32: srl [[T0]],[[T0]],0x10 6265; MIPS32: andi [[T0]],[[T0]],0xff 6266; MIPS32: andi [[T0]],[[T0]],0x1 6267; MIPS32: move [[T4]],[[T2]] 6268; MIPS32: srl [[T4]],[[T4]],0x10 6269; MIPS32: andi [[T4]],[[T4]],0xff 6270; MIPS32: andi [[T4]],[[T4]],0x1 6271; MIPS32: sll [[T0]],[[T0]],0x1f 6272; MIPS32: sll [[T4]],[[T4]],0x1f 6273; MIPS32: sltu [[T0]],[[T0]],[[T4]] 6274; MIPS32: xori [[T0]],[[T0]],0x1 6275; MIPS32: andi [[T0]],[[T0]],0xff 6276; MIPS32: sll [[T0]],[[T0]],0x10 6277; MIPS32: lui [[T4]],0xff00 6278; MIPS32: ori [[T4]],[[T4]],0xffff 6279; MIPS32: and [[T1]],[[T1]],[[T4]] 6280; MIPS32: or [[T0]],[[T0]],[[T1]] 6281; MIPS32: srl [[T12:.*]],a2,0x18 6282; MIPS32: andi [[T12]],[[T12]],0x1 6283; MIPS32: srl [[T2]],[[T2]],0x18 6284; MIPS32: andi [[T2]],[[T2]],0x1 6285; MIPS32: sll [[T12]],[[T12]],0x1f 6286; MIPS32: sll [[T2]],[[T2]],0x1f 6287; MIPS32: sltu [[T12]],[[T12]],[[T2]] 6288; MIPS32: xori [[T12]],[[T12]],0x1 6289; MIPS32: sll [[T12]],[[T12]],0x18 6290; MIPS32: sll [[T0]],[[T0]],0x8 6291; MIPS32: srl [[T0]],[[T0]],0x8 6292; MIPS32: or [[T12]],[[T12]],[[T0]] 6293; MIPS32: move [[T0]],a3 6294; MIPS32: andi [[T0]],[[T0]],0xff 6295; MIPS32: andi [[T0]],[[T0]],0x1 6296; MIPS32: move [[T1]],[[T3]] 6297; MIPS32: andi [[T1]],[[T1]],0xff 6298; MIPS32: andi [[T1]],[[T1]],0x1 6299; MIPS32: sll [[T0]],[[T0]],0x1f 6300; MIPS32: sll [[T1]],[[T1]],0x1f 6301; MIPS32: sltu [[T0]],[[T0]],[[T1]] 6302; MIPS32: xori [[T0]],[[T0]],0x1 6303; MIPS32: andi [[T0]],[[T0]],0xff 6304; MIPS32: srl [[T7]],[[T7]],0x8 6305; MIPS32: sll [[T7]],[[T7]],0x8 6306; MIPS32: or [[T0]],[[T0]],[[T7]] 6307; MIPS32: move [[T1]],a3 6308; MIPS32: srl [[T1]],[[T1]],0x8 6309; MIPS32: andi [[T1]],[[T1]],0xff 6310; MIPS32: andi [[T1]],[[T1]],0x1 6311; MIPS32: move [[T2]],[[T3]] 6312; MIPS32: srl [[T2]],[[T2]],0x8 6313; MIPS32: andi [[T2]],[[T2]],0xff 6314; MIPS32: andi [[T2]],[[T2]],0x1 6315; MIPS32: sll [[T1]],[[T1]],0x1f 6316; MIPS32: sll [[T2]],[[T2]],0x1f 6317; MIPS32: sltu [[T1]],[[T1]],[[T2]] 6318; MIPS32: xori [[T1]],[[T1]],0x1 6319; MIPS32: andi [[T1]],[[T1]],0xff 6320; MIPS32: sll [[T1]],[[T1]],0x8 6321; MIPS32: lui [[T2]],0xffff 6322; MIPS32: ori [[T2]],[[T2]],0xff 6323; MIPS32: and [[T0]],[[T0]],[[T2]] 6324; MIPS32: or [[T1]],[[T1]],[[T0]] 6325; MIPS32: move [[T0]],a3 6326; MIPS32: srl [[T0]],[[T0]],0x10 6327; MIPS32: andi [[T0]],[[T0]],0xff 6328; MIPS32: andi [[T0]],[[T0]],0x1 6329; MIPS32: move [[T2]],[[T3]] 6330; MIPS32: srl [[T2]],[[T2]],0x10 6331; MIPS32: andi [[T2]],[[T2]],0xff 6332; MIPS32: andi [[T2]],[[T2]],0x1 6333; MIPS32: sll [[T0]],[[T0]],0x1f 6334; MIPS32: sll [[T2]],[[T2]],0x1f 6335; MIPS32: sltu [[T0]],[[T0]],[[T2]] 6336; MIPS32: xori [[T0]],[[T0]],0x1 6337; MIPS32: andi [[T0]],[[T0]],0xff 6338; MIPS32: sll [[T0]],[[T0]],0x10 6339; MIPS32: lui [[T2]],0xff00 6340; MIPS32: ori [[T2]],[[T2]],0xffff 6341; MIPS32: and [[T1]],[[T1]],[[T2]] 6342; MIPS32: or [[T0]],[[T0]],[[T1]] 6343; MIPS32: srl [[T13:.*]],a3,0x18 6344; MIPS32: andi [[T13]],[[T13]],0x1 6345; MIPS32: srl [[T3]],[[T3]],0x18 6346; MIPS32: andi [[T3]],[[T3]],0x1 6347; MIPS32: sll [[T13]],[[T13]],0x1f 6348; MIPS32: sll [[T3]],[[T3]],0x1f 6349; MIPS32: sltu [[T13]],[[T13]],[[T3]] 6350; MIPS32: xori [[T13]],[[T13]],0x1 6351; MIPS32: sll [[T13]],[[T13]],0x18 6352; MIPS32: sll [[T0]],[[T0]],0x8 6353; MIPS32: srl [[T0]],[[T0]],0x8 6354; MIPS32: or [[T13]],[[T13]],[[T0]] 6355; MIPS32: move v0,[[T10]] 6356; MIPS32: move v1,[[T11]] 6357; MIPS32: move a0,[[T12]] 6358; MIPS32: move a1,[[T13]] 6359} 6360 6361define internal <16 x i1> @test_icmp_v16i1_ugt(<16 x i1> %a, <16 x i1> %b) { 6362entry: 6363 %res = icmp ugt <16 x i1> %a, %b 6364 ret <16 x i1> %res 6365; CHECK-LABEL: test_icmp_v16i1_ugt 6366; CHECK: pxor 6367; CHECK: pcmpgtb 6368 6369; MIPS32-LABEL: test_icmp_v16i1_ugt 6370; MIPS32: lw [[T0:.*]], 6371; MIPS32: lw [[T1:.*]], 6372; MIPS32: lw [[T2:.*]], 6373; MIPS32: lw [[T3:.*]], 6374; MIPS32: move [[T4:.*]],zero 6375; MIPS32: move [[T5:.*]],zero 6376; MIPS32: move [[T6:.*]],zero 6377; MIPS32: move [[T7:.*]],zero 6378; MIPS32: move [[T8:.*]],a0 6379; MIPS32: andi [[T8]],[[T8]],0xff 6380; MIPS32: andi [[T8]],[[T8]],0x1 6381; MIPS32: move [[T9:.*]],[[T0]] 6382; MIPS32: andi [[T9]],[[T9]],0xff 6383; MIPS32: andi [[T9]],[[T9]],0x1 6384; MIPS32: sll [[T8]],[[T8]],0x1f 6385; MIPS32: sll [[T9]],[[T9]],0x1f 6386; MIPS32: sltu [[T9]],[[T9]],[[T8]] 6387; MIPS32: andi [[T9]],[[T9]],0xff 6388; MIPS32: srl [[T4]],[[T4]],0x8 6389; MIPS32: sll [[T4]],[[T4]],0x8 6390; MIPS32: or [[T9]],[[T9]],[[T4]] 6391; MIPS32: move [[T4]],a0 6392; MIPS32: srl [[T4]],[[T4]],0x8 6393; MIPS32: andi [[T4]],[[T4]],0xff 6394; MIPS32: andi [[T4]],[[T4]],0x1 6395; MIPS32: move [[T8]],[[T0]] 6396; MIPS32: srl [[T8]],[[T8]],0x8 6397; MIPS32: andi [[T8]],[[T8]],0xff 6398; MIPS32: andi [[T8]],[[T8]],0x1 6399; MIPS32: sll [[T4]],[[T4]],0x1f 6400; MIPS32: sll [[T8]],[[T8]],0x1f 6401; MIPS32: sltu [[T8]],[[T8]],[[T4]] 6402; MIPS32: andi [[T8]],[[T8]],0xff 6403; MIPS32: sll [[T8]],[[T8]],0x8 6404; MIPS32: lui [[T4]],0xffff 6405; MIPS32: ori [[T4]],[[T4]],0xff 6406; MIPS32: and [[T9]],[[T9]],[[T4]] 6407; MIPS32: or [[T8]],[[T8]],[[T9]] 6408; MIPS32: move [[T4]],a0 6409; MIPS32: srl [[T4]],[[T4]],0x10 6410; MIPS32: andi [[T4]],[[T4]],0xff 6411; MIPS32: andi [[T4]],[[T4]],0x1 6412; MIPS32: move [[T9]],[[T0]] 6413; MIPS32: srl [[T9]],[[T9]],0x10 6414; MIPS32: andi [[T9]],[[T9]],0xff 6415; MIPS32: andi [[T9]],[[T9]],0x1 6416; MIPS32: sll [[T4]],[[T4]],0x1f 6417; MIPS32: sll [[T9]],[[T9]],0x1f 6418; MIPS32: sltu [[T9]],[[T9]],[[T4]] 6419; MIPS32: andi [[T9]],[[T9]],0xff 6420; MIPS32: sll [[T9]],[[T9]],0x10 6421; MIPS32: lui [[T4]],0xff00 6422; MIPS32: ori [[T4]],[[T4]],0xffff 6423; MIPS32: and [[T8]],[[T8]],[[T4]] 6424; MIPS32: or [[T9]],[[T9]],[[T8]] 6425; MIPS32: srl [[T10:.*]],a0,0x18 6426; MIPS32: andi [[T10]],[[T10]],0x1 6427; MIPS32: srl [[T0]],[[T0]],0x18 6428; MIPS32: andi [[T0]],[[T0]],0x1 6429; MIPS32: sll [[T10]],[[T10]],0x1f 6430; MIPS32: sll [[T0]],[[T0]],0x1f 6431; MIPS32: sltu [[T0]],[[T0]],[[T10]] 6432; MIPS32: sll [[T0]],[[T0]],0x18 6433; MIPS32: sll [[T9]],[[T9]],0x8 6434; MIPS32: srl [[T9]],[[T9]],0x8 6435; MIPS32: or v0,[[T0]],[[T9]] 6436; MIPS32: move [[T10]],a1 6437; MIPS32: andi [[T10]],[[T10]],0xff 6438; MIPS32: andi [[T10]],[[T10]],0x1 6439; MIPS32: move [[T4]],[[T1]] 6440; MIPS32: andi [[T4]],[[T4]],0xff 6441; MIPS32: andi [[T4]],[[T4]],0x1 6442; MIPS32: sll [[T10]],[[T10]],0x1f 6443; MIPS32: sll [[T4]],[[T4]],0x1f 6444; MIPS32: sltu [[T4]],[[T4]],[[T10]] 6445; MIPS32: andi [[T4]],[[T4]],0xff 6446; MIPS32: srl [[T5]],[[T5]],0x8 6447; MIPS32: sll [[T5]],[[T5]],0x8 6448; MIPS32: or [[T4]],[[T4]],[[T5]] 6449; MIPS32: move [[T10]],a1 6450; MIPS32: srl [[T10]],[[T10]],0x8 6451; MIPS32: andi [[T10]],[[T10]],0xff 6452; MIPS32: andi [[T10]],[[T10]],0x1 6453; MIPS32: move [[T5]],[[T1]] 6454; MIPS32: srl [[T5]],[[T5]],0x8 6455; MIPS32: andi [[T5]],[[T5]],0xff 6456; MIPS32: andi [[T5]],[[T5]],0x1 6457; MIPS32: sll [[T10]],[[T10]],0x1f 6458; MIPS32: sll [[T5]],[[T5]],0x1f 6459; MIPS32: sltu [[T5]],[[T5]],[[T10]] 6460; MIPS32: andi [[T5]],[[T5]],0xff 6461; MIPS32: sll [[T5]],[[T5]],0x8 6462; MIPS32: lui [[T10]],0xffff 6463; MIPS32: ori [[T10]],[[T10]],0xff 6464; MIPS32: and [[T4]],[[T4]],[[T10]] 6465; MIPS32: or [[T5]],[[T5]],[[T4]] 6466; MIPS32: move [[T10]],a1 6467; MIPS32: srl [[T10]],[[T10]],0x10 6468; MIPS32: andi [[T10]],[[T10]],0xff 6469; MIPS32: andi [[T10]],[[T10]],0x1 6470; MIPS32: move [[T4]],[[T1]] 6471; MIPS32: srl [[T4]],[[T4]],0x10 6472; MIPS32: andi [[T4]],[[T4]],0xff 6473; MIPS32: andi [[T4]],[[T4]],0x1 6474; MIPS32: sll [[T10]],[[T10]],0x1f 6475; MIPS32: sll [[T4]],[[T4]],0x1f 6476; MIPS32: sltu [[T4]],[[T4]],[[T10]] 6477; MIPS32: andi [[T4]],[[T4]],0xff 6478; MIPS32: sll [[T4]],[[T4]],0x10 6479; MIPS32: lui [[T10]],0xff00 6480; MIPS32: ori [[T10]],[[T10]],0xffff 6481; MIPS32: and [[T5]],[[T5]],[[T10]] 6482; MIPS32: or [[T4]],[[T4]],[[T5]] 6483; MIPS32: srl [[T11:.*]],a1,0x18 6484; MIPS32: andi [[T11]],[[T11]],0x1 6485; MIPS32: srl [[T1]],[[T1]],0x18 6486; MIPS32: andi [[T1]],[[T1]],0x1 6487; MIPS32: sll [[T11]],[[T11]],0x1f 6488; MIPS32: sll [[T1]],[[T1]],0x1f 6489; MIPS32: sltu [[T1]],[[T1]],[[T11]] 6490; MIPS32: sll [[T1]],[[T1]],0x18 6491; MIPS32: sll [[T4]],[[T4]],0x8 6492; MIPS32: srl [[T4]],[[T4]],0x8 6493; MIPS32: or v1,[[T1]],[[T4]] 6494; MIPS32: move [[T10]],a2 6495; MIPS32: andi [[T10]],[[T10]],0xff 6496; MIPS32: andi [[T10]],[[T10]],0x1 6497; MIPS32: move [[T11]],[[T2]] 6498; MIPS32: andi [[T11]],[[T11]],0xff 6499; MIPS32: andi [[T11]],[[T11]],0x1 6500; MIPS32: sll [[T10]],[[T10]],0x1f 6501; MIPS32: sll [[T11]],[[T11]],0x1f 6502; MIPS32: sltu [[T11]],[[T11]],[[T10]] 6503; MIPS32: andi [[T11]],[[T11]],0xff 6504; MIPS32: srl [[T6]],[[T6]],0x8 6505; MIPS32: sll [[T6]],[[T6]],0x8 6506; MIPS32: or [[T11]],[[T11]],[[T6]] 6507; MIPS32: move [[T10]],a2 6508; MIPS32: srl [[T10]],[[T10]],0x8 6509; MIPS32: andi [[T10]],[[T10]],0xff 6510; MIPS32: andi [[T10]],[[T10]],0x1 6511; MIPS32: move [[T4]],[[T2]] 6512; MIPS32: srl [[T4]],[[T4]],0x8 6513; MIPS32: andi [[T4]],[[T4]],0xff 6514; MIPS32: andi [[T4]],[[T4]],0x1 6515; MIPS32: sll [[T10]],[[T10]],0x1f 6516; MIPS32: sll [[T4]],[[T4]],0x1f 6517; MIPS32: sltu [[T4]],[[T4]],[[T10]] 6518; MIPS32: andi [[T4]],[[T4]],0xff 6519; MIPS32: sll [[T4]],[[T4]],0x8 6520; MIPS32: lui [[T10]],0xffff 6521; MIPS32: ori [[T10]],[[T10]],0xff 6522; MIPS32: and [[T11]],[[T11]],[[T10]] 6523; MIPS32: or [[T4]],[[T4]],[[T11]] 6524; MIPS32: move [[T10]],a2 6525; MIPS32: srl [[T10]],[[T10]],0x10 6526; MIPS32: andi [[T10]],[[T10]],0xff 6527; MIPS32: andi [[T10]],[[T10]],0x1 6528; MIPS32: move [[T11]],[[T2]] 6529; MIPS32: srl [[T11]],[[T11]],0x10 6530; MIPS32: andi [[T11]],[[T11]],0xff 6531; MIPS32: andi [[T11]],[[T11]],0x1 6532; MIPS32: sll [[T10]],[[T10]],0x1f 6533; MIPS32: sll [[T11]],[[T11]],0x1f 6534; MIPS32: sltu [[T11]],[[T11]],[[T10]] 6535; MIPS32: andi [[T11]],[[T11]],0xff 6536; MIPS32: sll [[T11]],[[T11]],0x10 6537; MIPS32: lui [[T10]],0xff00 6538; MIPS32: ori [[T10]],[[T10]],0xffff 6539; MIPS32: and [[T4]],[[T4]],[[T10]] 6540; MIPS32: or [[T11]],[[T11]],[[T4]] 6541; MIPS32: srl [[T12:.*]],a2,0x18 6542; MIPS32: andi [[T12]],[[T12]],0x1 6543; MIPS32: srl [[T2]],[[T2]],0x18 6544; MIPS32: andi [[T2]],[[T2]],0x1 6545; MIPS32: sll [[T12]],[[T12]],0x1f 6546; MIPS32: sll [[T2]],[[T2]],0x1f 6547; MIPS32: sltu [[T2]],[[T2]],[[T12]] 6548; MIPS32: sll [[T2]],[[T2]],0x18 6549; MIPS32: sll [[T11]],[[T11]],0x8 6550; MIPS32: srl [[T11]],[[T11]],0x8 6551; MIPS32: or [[T2]],[[T2]],[[T11]] 6552; MIPS32: move [[T10]],a3 6553; MIPS32: andi [[T10]],[[T10]],0xff 6554; MIPS32: andi [[T10]],[[T10]],0x1 6555; MIPS32: move [[T11]],[[T3]] 6556; MIPS32: andi [[T11]],[[T11]],0xff 6557; MIPS32: andi [[T11]],[[T11]],0x1 6558; MIPS32: sll [[T10]],[[T10]],0x1f 6559; MIPS32: sll [[T11]],[[T11]],0x1f 6560; MIPS32: sltu [[T11]],[[T11]],[[T10]] 6561; MIPS32: andi [[T11]],[[T11]],0xff 6562; MIPS32: srl [[T7]],[[T7]],0x8 6563; MIPS32: sll [[T7]],[[T7]],0x8 6564; MIPS32: or [[T11]],[[T11]],[[T7]] 6565; MIPS32: move [[T10]],a3 6566; MIPS32: srl [[T10]],[[T10]],0x8 6567; MIPS32: andi [[T10]],[[T10]],0xff 6568; MIPS32: andi [[T10]],[[T10]],0x1 6569; MIPS32: move [[T12]],[[T3]] 6570; MIPS32: srl [[T12]],[[T12]],0x8 6571; MIPS32: andi [[T12]],[[T12]],0xff 6572; MIPS32: andi [[T12]],[[T12]],0x1 6573; MIPS32: sll [[T10]],[[T10]],0x1f 6574; MIPS32: sll [[T12]],[[T12]],0x1f 6575; MIPS32: sltu [[T12]],[[T12]],[[T10]] 6576; MIPS32: andi [[T12]],[[T12]],0xff 6577; MIPS32: sll [[T12]],[[T12]],0x8 6578; MIPS32: lui [[T10]],0xffff 6579; MIPS32: ori [[T10]],[[T10]],0xff 6580; MIPS32: and [[T11]],[[T11]],[[T10]] 6581; MIPS32: or [[T12]],[[T12]],[[T11]] 6582; MIPS32: move [[T10]],a3 6583; MIPS32: srl [[T10]],[[T10]],0x10 6584; MIPS32: andi [[T10]],[[T10]],0xff 6585; MIPS32: andi [[T10]],[[T10]],0x1 6586; MIPS32: move [[T11]],[[T3]] 6587; MIPS32: srl [[T11]],[[T11]],0x10 6588; MIPS32: andi [[T11]],[[T11]],0xff 6589; MIPS32: andi [[T11]],[[T11]],0x1 6590; MIPS32: sll [[T10]],[[T10]],0x1f 6591; MIPS32: sll [[T11]],[[T11]],0x1f 6592; MIPS32: sltu [[T11]],[[T11]],[[T10]] 6593; MIPS32: andi [[T11]],[[T11]],0xff 6594; MIPS32: sll [[T11]],[[T11]],0x10 6595; MIPS32: lui [[T10]],0xff00 6596; MIPS32: ori [[T10]],[[T10]],0xffff 6597; MIPS32: and [[T12]],[[T12]],[[T10]] 6598; MIPS32: or [[T11]],[[T11]],[[T12]] 6599; MIPS32: srl [[T13:.*]],a3,0x18 6600; MIPS32: andi [[T13]],[[T13]],0x1 6601; MIPS32: srl [[T3]],[[T3]],0x18 6602; MIPS32: andi [[T3]],[[T3]],0x1 6603; MIPS32: sll [[T13]],[[T13]],0x1f 6604; MIPS32: sll [[T3]],[[T3]],0x1f 6605; MIPS32: sltu [[T3]],[[T3]],[[T13]] 6606; MIPS32: sll [[T3]],[[T3]],0x18 6607; MIPS32: sll [[T11]],[[T11]],0x8 6608; MIPS32: srl [[T11]],[[T11]],0x8 6609; MIPS32: or [[T3]],[[T3]],[[T11]] 6610; MIPS32: move a0,[[T2]] 6611; MIPS32: move a1,[[T3]] 6612} 6613 6614define internal <16 x i1> @test_icmp_v16i1_ule(<16 x i1> %a, <16 x i1> %b) { 6615entry: 6616 %res = icmp ule <16 x i1> %a, %b 6617 ret <16 x i1> %res 6618; CHECK-LABEL: test_icmp_v16i1_ule 6619; CHECK: pxor 6620; CHECK: pcmpgtb 6621; CHECK: pxor 6622 6623; MIPS32-LABEL: test_icmp_v16i1_ule 6624; MIPS32: lw [[T0:.*]], 6625; MIPS32: lw [[T1:.*]], 6626; MIPS32: lw [[T2:.*]], 6627; MIPS32: lw [[T3:.*]], 6628; MIPS32: move [[T4:.*]],zero 6629; MIPS32: move [[T5:.*]],zero 6630; MIPS32: move [[T6:.*]],zero 6631; MIPS32: move [[T7:.*]],zero 6632; MIPS32: move [[T8:.*]],a0 6633; MIPS32: andi [[T8]],[[T8]],0xff 6634; MIPS32: andi [[T8]],[[T8]],0x1 6635; MIPS32: move [[T9:.*]],[[T0]] 6636; MIPS32: andi [[T9]],[[T9]],0xff 6637; MIPS32: andi [[T9]],[[T9]],0x1 6638; MIPS32: sll [[T8]],[[T8]],0x1f 6639; MIPS32: sll [[T9]],[[T9]],0x1f 6640; MIPS32: sltu [[T9]],[[T9]],[[T8]] 6641; MIPS32: xori [[T9]],[[T9]],0x1 6642; MIPS32: andi [[T9]],[[T9]],0xff 6643; MIPS32: srl [[T4]],[[T4]],0x8 6644; MIPS32: sll [[T4]],[[T4]],0x8 6645; MIPS32: or [[T9]],[[T9]],[[T4]] 6646; MIPS32: move [[T4]],a0 6647; MIPS32: srl [[T4]],[[T4]],0x8 6648; MIPS32: andi [[T4]],[[T4]],0xff 6649; MIPS32: andi [[T4]],[[T4]],0x1 6650; MIPS32: move [[T8]],[[T0]] 6651; MIPS32: srl [[T8]],[[T8]],0x8 6652; MIPS32: andi [[T8]],[[T8]],0xff 6653; MIPS32: andi [[T8]],[[T8]],0x1 6654; MIPS32: sll [[T4]],[[T4]],0x1f 6655; MIPS32: sll [[T8]],[[T8]],0x1f 6656; MIPS32: sltu [[T8]],[[T8]],[[T4]] 6657; MIPS32: xori [[T8]],[[T8]],0x1 6658; MIPS32: andi [[T8]],[[T8]],0xff 6659; MIPS32: sll [[T8]],[[T8]],0x8 6660; MIPS32: lui [[T4]],0xffff 6661; MIPS32: ori [[T4]],[[T4]],0xff 6662; MIPS32: and [[T9]],[[T9]],[[T4]] 6663; MIPS32: or [[T8]],[[T8]],[[T9]] 6664; MIPS32: move [[T4]],a0 6665; MIPS32: srl [[T4]],[[T4]],0x10 6666; MIPS32: andi [[T4]],[[T4]],0xff 6667; MIPS32: andi [[T4]],[[T4]],0x1 6668; MIPS32: move [[T9]],[[T0]] 6669; MIPS32: srl [[T9]],[[T9]],0x10 6670; MIPS32: andi [[T9]],[[T9]],0xff 6671; MIPS32: andi [[T9]],[[T9]],0x1 6672; MIPS32: sll [[T4]],[[T4]],0x1f 6673; MIPS32: sll [[T9]],[[T9]],0x1f 6674; MIPS32: sltu [[T9]],[[T9]],[[T4]] 6675; MIPS32: xori [[T9]],[[T9]],0x1 6676; MIPS32: andi [[T9]],[[T9]],0xff 6677; MIPS32: sll [[T9]],[[T9]],0x10 6678; MIPS32: lui [[T4]],0xff00 6679; MIPS32: ori [[T4]],[[T4]],0xffff 6680; MIPS32: and [[T8]],[[T8]],[[T4]] 6681; MIPS32: or [[T9]],[[T9]],[[T8]] 6682; MIPS32: srl [[T10:.*]],a0,0x18 6683; MIPS32: andi [[T10]],[[T10]],0x1 6684; MIPS32: srl [[T0]],[[T0]],0x18 6685; MIPS32: andi [[T0]],[[T0]],0x1 6686; MIPS32: sll [[T10]],[[T10]],0x1f 6687; MIPS32: sll [[T0]],[[T0]],0x1f 6688; MIPS32: sltu [[T0]],[[T0]],[[T10]] 6689; MIPS32: xori [[T0]],[[T0]],0x1 6690; MIPS32: sll [[T0]],[[T0]],0x18 6691; MIPS32: sll [[T9]],[[T9]],0x8 6692; MIPS32: srl [[T9]],[[T9]],0x8 6693; MIPS32: or v0,[[T0]],[[T9]] 6694; MIPS32: move [[T10]],a1 6695; MIPS32: andi [[T10]],[[T10]],0xff 6696; MIPS32: andi [[T10]],[[T10]],0x1 6697; MIPS32: move [[T4]],[[T1]] 6698; MIPS32: andi [[T4]],[[T4]],0xff 6699; MIPS32: andi [[T4]],[[T4]],0x1 6700; MIPS32: sll [[T10]],[[T10]],0x1f 6701; MIPS32: sll [[T4]],[[T4]],0x1f 6702; MIPS32: sltu [[T4]],[[T4]],[[T10]] 6703; MIPS32: xori [[T4]],[[T4]],0x1 6704; MIPS32: andi [[T4]],[[T4]],0xff 6705; MIPS32: srl [[T5]],[[T5]],0x8 6706; MIPS32: sll [[T5]],[[T5]],0x8 6707; MIPS32: or [[T4]],[[T4]],[[T5]] 6708; MIPS32: move [[T10]],a1 6709; MIPS32: srl [[T10]],[[T10]],0x8 6710; MIPS32: andi [[T10]],[[T10]],0xff 6711; MIPS32: andi [[T10]],[[T10]],0x1 6712; MIPS32: move [[T5]],[[T1]] 6713; MIPS32: srl [[T5]],[[T5]],0x8 6714; MIPS32: andi [[T5]],[[T5]],0xff 6715; MIPS32: andi [[T5]],[[T5]],0x1 6716; MIPS32: sll [[T10]],[[T10]],0x1f 6717; MIPS32: sll [[T5]],[[T5]],0x1f 6718; MIPS32: sltu [[T5]],[[T5]],[[T10]] 6719; MIPS32: xori [[T5]],[[T5]],0x1 6720; MIPS32: andi [[T5]],[[T5]],0xff 6721; MIPS32: sll [[T5]],[[T5]],0x8 6722; MIPS32: lui [[T10]],0xffff 6723; MIPS32: ori [[T10]],[[T10]],0xff 6724; MIPS32: and [[T4]],[[T4]],[[T10]] 6725; MIPS32: or [[T5]],[[T5]],[[T4]] 6726; MIPS32: move [[T10]],a1 6727; MIPS32: srl [[T10]],[[T10]],0x10 6728; MIPS32: andi [[T10]],[[T10]],0xff 6729; MIPS32: andi [[T10]],[[T10]],0x1 6730; MIPS32: move [[T4]],[[T1]] 6731; MIPS32: srl [[T4]],[[T4]],0x10 6732; MIPS32: andi [[T4]],[[T4]],0xff 6733; MIPS32: andi [[T4]],[[T4]],0x1 6734; MIPS32: sll [[T10]],[[T10]],0x1f 6735; MIPS32: sll [[T4]],[[T4]],0x1f 6736; MIPS32: sltu [[T4]],[[T4]],[[T10]] 6737; MIPS32: xori [[T4]],[[T4]],0x1 6738; MIPS32: andi [[T4]],[[T4]],0xff 6739; MIPS32: sll [[T4]],[[T4]],0x10 6740; MIPS32: lui [[T10]],0xff00 6741; MIPS32: ori [[T10]],[[T10]],0xffff 6742; MIPS32: and [[T5]],[[T5]],[[T10]] 6743; MIPS32: or [[T4]],[[T4]],[[T5]] 6744; MIPS32: srl [[T11:.*]],a1,0x18 6745; MIPS32: andi [[T11]],[[T11]],0x1 6746; MIPS32: srl [[T1]],[[T1]],0x18 6747; MIPS32: andi [[T1]],[[T1]],0x1 6748; MIPS32: sll [[T11]],[[T11]],0x1f 6749; MIPS32: sll [[T1]],[[T1]],0x1f 6750; MIPS32: sltu [[T1]],[[T1]],[[T11]] 6751; MIPS32: xori [[T1]],[[T1]],0x1 6752; MIPS32: sll [[T1]],[[T1]],0x18 6753; MIPS32: sll [[T4]],[[T4]],0x8 6754; MIPS32: srl [[T4]],[[T4]],0x8 6755; MIPS32: or v1,[[T1]],[[T4]] 6756; MIPS32: move [[T10]],a2 6757; MIPS32: andi [[T10]],[[T10]],0xff 6758; MIPS32: andi [[T10]],[[T10]],0x1 6759; MIPS32: move [[T11]],[[T2]] 6760; MIPS32: andi [[T11]],[[T11]],0xff 6761; MIPS32: andi [[T11]],[[T11]],0x1 6762; MIPS32: sll [[T10]],[[T10]],0x1f 6763; MIPS32: sll [[T11]],[[T11]],0x1f 6764; MIPS32: sltu [[T11]],[[T11]],[[T10]] 6765; MIPS32: xori [[T11]],[[T11]],0x1 6766; MIPS32: andi [[T11]],[[T11]],0xff 6767; MIPS32: srl [[T6]],[[T6]],0x8 6768; MIPS32: sll [[T6]],[[T6]],0x8 6769; MIPS32: or [[T11]],[[T11]],[[T6]] 6770; MIPS32: move [[T10]],a2 6771; MIPS32: srl [[T10]],[[T10]],0x8 6772; MIPS32: andi [[T10]],[[T10]],0xff 6773; MIPS32: andi [[T10]],[[T10]],0x1 6774; MIPS32: move [[T4]],[[T2]] 6775; MIPS32: srl [[T4]],[[T4]],0x8 6776; MIPS32: andi [[T4]],[[T4]],0xff 6777; MIPS32: andi [[T4]],[[T4]],0x1 6778; MIPS32: sll [[T10]],[[T10]],0x1f 6779; MIPS32: sll [[T4]],[[T4]],0x1f 6780; MIPS32: sltu [[T4]],[[T4]],[[T10]] 6781; MIPS32: xori [[T4]],[[T4]],0x1 6782; MIPS32: andi [[T4]],[[T4]],0xff 6783; MIPS32: sll [[T4]],[[T4]],0x8 6784; MIPS32: lui [[T10]],0xffff 6785; MIPS32: ori [[T10]],[[T10]],0xff 6786; MIPS32: and [[T11]],[[T11]],[[T10]] 6787; MIPS32: or [[T4]],[[T4]],[[T11]] 6788; MIPS32: move [[T10]],a2 6789; MIPS32: srl [[T10]],[[T10]],0x10 6790; MIPS32: andi [[T10]],[[T10]],0xff 6791; MIPS32: andi [[T10]],[[T10]],0x1 6792; MIPS32: move [[T11]],[[T2]] 6793; MIPS32: srl [[T11]],[[T11]],0x10 6794; MIPS32: andi [[T11]],[[T11]],0xff 6795; MIPS32: andi [[T11]],[[T11]],0x1 6796; MIPS32: sll [[T10]],[[T10]],0x1f 6797; MIPS32: sll [[T11]],[[T11]],0x1f 6798; MIPS32: sltu [[T11]],[[T11]],[[T10]] 6799; MIPS32: xori [[T11]],[[T11]],0x1 6800; MIPS32: andi [[T11]],[[T11]],0xff 6801; MIPS32: sll [[T11]],[[T11]],0x10 6802; MIPS32: lui [[T10]],0xff00 6803; MIPS32: ori [[T10]],[[T10]],0xffff 6804; MIPS32: and [[T4]],[[T4]],[[T10]] 6805; MIPS32: or [[T11]],[[T11]],[[T4]] 6806; MIPS32: srl [[T12:.*]],a2,0x18 6807; MIPS32: andi [[T12]],[[T12]],0x1 6808; MIPS32: srl [[T2]],[[T2]],0x18 6809; MIPS32: andi [[T2]],[[T2]],0x1 6810; MIPS32: sll [[T12]],[[T12]],0x1f 6811; MIPS32: sll [[T2]],[[T2]],0x1f 6812; MIPS32: sltu [[T2]],[[T2]],[[T12]] 6813; MIPS32: xori [[T2]],[[T2]],0x1 6814; MIPS32: sll [[T2]],[[T2]],0x18 6815; MIPS32: sll [[T11]],[[T11]],0x8 6816; MIPS32: srl [[T11]],[[T11]],0x8 6817; MIPS32: or [[T2]],[[T2]],[[T11]] 6818; MIPS32: move [[T10]],a3 6819; MIPS32: andi [[T10]],[[T10]],0xff 6820; MIPS32: andi [[T10]],[[T10]],0x1 6821; MIPS32: move [[T11]],[[T3]] 6822; MIPS32: andi [[T11]],[[T11]],0xff 6823; MIPS32: andi [[T11]],[[T11]],0x1 6824; MIPS32: sll [[T10]],[[T10]],0x1f 6825; MIPS32: sll [[T11]],[[T11]],0x1f 6826; MIPS32: sltu [[T11]],[[T11]],[[T10]] 6827; MIPS32: xori [[T11]],[[T11]],0x1 6828; MIPS32: andi [[T11]],[[T11]],0xff 6829; MIPS32: srl [[T7]],[[T7]],0x8 6830; MIPS32: sll [[T7]],[[T7]],0x8 6831; MIPS32: or [[T11]],[[T11]],[[T7]] 6832; MIPS32: move [[T10]],a3 6833; MIPS32: srl [[T10]],[[T10]],0x8 6834; MIPS32: andi [[T10]],[[T10]],0xff 6835; MIPS32: andi [[T10]],[[T10]],0x1 6836; MIPS32: move [[T12]],[[T3]] 6837; MIPS32: srl [[T12]],[[T12]],0x8 6838; MIPS32: andi [[T12]],[[T12]],0xff 6839; MIPS32: andi [[T12]],[[T12]],0x1 6840; MIPS32: sll [[T10]],[[T10]],0x1f 6841; MIPS32: sll [[T12]],[[T12]],0x1f 6842; MIPS32: sltu [[T12]],[[T12]],[[T10]] 6843; MIPS32: xori [[T12]],[[T12]],0x1 6844; MIPS32: andi [[T12]],[[T12]],0xff 6845; MIPS32: sll [[T12]],[[T12]],0x8 6846; MIPS32: lui [[T10]],0xffff 6847; MIPS32: ori [[T10]],[[T10]],0xff 6848; MIPS32: and [[T11]],[[T11]],[[T10]] 6849; MIPS32: or [[T12]],[[T12]],[[T11]] 6850; MIPS32: move [[T10]],a3 6851; MIPS32: srl [[T10]],[[T10]],0x10 6852; MIPS32: andi [[T10]],[[T10]],0xff 6853; MIPS32: andi [[T10]],[[T10]],0x1 6854; MIPS32: move [[T11]],[[T3]] 6855; MIPS32: srl [[T11]],[[T11]],0x10 6856; MIPS32: andi [[T11]],[[T11]],0xff 6857; MIPS32: andi [[T11]],[[T11]],0x1 6858; MIPS32: sll [[T10]],[[T10]],0x1f 6859; MIPS32: sll [[T11]],[[T11]],0x1f 6860; MIPS32: sltu [[T11]],[[T11]],[[T10]] 6861; MIPS32: xori [[T11]],[[T11]],0x1 6862; MIPS32: andi [[T11]],[[T11]],0xff 6863; MIPS32: sll [[T11]],[[T11]],0x10 6864; MIPS32: lui [[T10]],0xff00 6865; MIPS32: ori [[T10]],[[T10]],0xffff 6866; MIPS32: and [[T12]],[[T12]],[[T10]] 6867; MIPS32: or [[T11]],[[T11]],[[T12]] 6868; MIPS32: srl [[T13:.*]],a3,0x18 6869; MIPS32: andi [[T13]],[[T13]],0x1 6870; MIPS32: srl [[T3]],[[T3]],0x18 6871; MIPS32: andi [[T3]],[[T3]],0x1 6872; MIPS32: sll [[T13]],[[T13]],0x1f 6873; MIPS32: sll [[T3]],[[T3]],0x1f 6874; MIPS32: sltu [[T3]],[[T3]],[[T13]] 6875; MIPS32: xori [[T3]],[[T3]],0x1 6876; MIPS32: sll [[T3]],[[T3]],0x18 6877; MIPS32: sll [[T11]],[[T11]],0x8 6878; MIPS32: srl [[T11]],[[T11]],0x8 6879; MIPS32: or [[T3]],[[T3]],[[T11]] 6880; MIPS32: move a0,[[T2]] 6881; MIPS32: move a1,[[T3]] 6882} 6883 6884define internal <16 x i1> @test_icmp_v16i1_ult(<16 x i1> %a, <16 x i1> %b) { 6885entry: 6886 %res = icmp ult <16 x i1> %a, %b 6887 ret <16 x i1> %res 6888; CHECK-LABEL: test_icmp_v16i1_ult 6889; CHECK: pxor 6890; CHECK: pcmpgtb 6891 6892; MIPS32-LABEL: test_icmp_v16i1_ult 6893; MIPS32: lw [[T0:.*]], 6894; MIPS32: lw [[T1:.*]], 6895; MIPS32: lw [[T2:.*]], 6896; MIPS32: lw [[T3:.*]], 6897; MIPS32: move [[T4:.*]],zero 6898; MIPS32: move [[T5:.*]],zero 6899; MIPS32: move [[T6:.*]],zero 6900; MIPS32: move [[T7:.*]],zero 6901; MIPS32: move [[T8:.*]],a0 6902; MIPS32: andi [[T8]],[[T8]],0xff 6903; MIPS32: andi [[T8]],[[T8]],0x1 6904; MIPS32: move [[T9:.*]],[[T0]] 6905; MIPS32: andi [[T9]],[[T9]],0xff 6906; MIPS32: andi [[T9]],[[T9]],0x1 6907; MIPS32: sll [[T8]],[[T8]],0x1f 6908; MIPS32: sll [[T9]],[[T9]],0x1f 6909; MIPS32: sltu [[T8]],[[T8]],[[T9]] 6910; MIPS32: andi [[T8]],[[T8]],0xff 6911; MIPS32: srl [[T4]],[[T4]],0x8 6912; MIPS32: sll [[T4]],[[T4]],0x8 6913; MIPS32: or [[T8]],[[T8]],[[T4]] 6914; MIPS32: move [[T4]],a0 6915; MIPS32: srl [[T4]],[[T4]],0x8 6916; MIPS32: andi [[T4]],[[T4]],0xff 6917; MIPS32: andi [[T4]],[[T4]],0x1 6918; MIPS32: move [[T9]],[[T0]] 6919; MIPS32: srl [[T9]],[[T9]],0x8 6920; MIPS32: andi [[T9]],[[T9]],0xff 6921; MIPS32: andi [[T9]],[[T9]],0x1 6922; MIPS32: sll [[T4]],[[T4]],0x1f 6923; MIPS32: sll [[T9]],[[T9]],0x1f 6924; MIPS32: sltu [[T4]],[[T4]],[[T9]] 6925; MIPS32: andi [[T4]],[[T4]],0xff 6926; MIPS32: sll [[T4]],[[T4]],0x8 6927; MIPS32: lui [[T9]],0xffff 6928; MIPS32: ori [[T9]],[[T9]],0xff 6929; MIPS32: and [[T8]],[[T8]],[[T9]] 6930; MIPS32: or [[T4]],[[T4]],[[T8]] 6931; MIPS32: move [[T8]],a0 6932; MIPS32: srl [[T8]],[[T8]],0x10 6933; MIPS32: andi [[T8]],[[T8]],0xff 6934; MIPS32: andi [[T8]],[[T8]],0x1 6935; MIPS32: move [[T9]],[[T0]] 6936; MIPS32: srl [[T9]],[[T9]],0x10 6937; MIPS32: andi [[T9]],[[T9]],0xff 6938; MIPS32: andi [[T9]],[[T9]],0x1 6939; MIPS32: sll [[T8]],[[T8]],0x1f 6940; MIPS32: sll [[T9]],[[T9]],0x1f 6941; MIPS32: sltu [[T8]],[[T8]],[[T9]] 6942; MIPS32: andi [[T8]],[[T8]],0xff 6943; MIPS32: sll [[T8]],[[T8]],0x10 6944; MIPS32: lui [[T9]],0xff00 6945; MIPS32: ori [[T9]],[[T9]],0xffff 6946; MIPS32: and [[T4]],[[T4]],[[T9]] 6947; MIPS32: or [[T8]],[[T8]],[[T4]] 6948; MIPS32: srl [[T10:.*]],a0,0x18 6949; MIPS32: andi [[T10]],[[T10]],0x1 6950; MIPS32: srl [[T0]],[[T0]],0x18 6951; MIPS32: andi [[T0]],[[T0]],0x1 6952; MIPS32: sll [[T10]],[[T10]],0x1f 6953; MIPS32: sll [[T0]],[[T0]],0x1f 6954; MIPS32: sltu [[T10]],[[T10]],[[T0]] 6955; MIPS32: sll [[T10]],[[T10]],0x18 6956; MIPS32: sll [[T8]],[[T8]],0x8 6957; MIPS32: srl [[T8]],[[T8]],0x8 6958; MIPS32: or [[T10]],[[T10]],[[T8]] 6959; MIPS32: move [[T0]],a1 6960; MIPS32: andi [[T0]],[[T0]],0xff 6961; MIPS32: andi [[T0]],[[T0]],0x1 6962; MIPS32: move [[T4]],[[T1]] 6963; MIPS32: andi [[T4]],[[T4]],0xff 6964; MIPS32: andi [[T4]],[[T4]],0x1 6965; MIPS32: sll [[T0]],[[T0]],0x1f 6966; MIPS32: sll [[T4]],[[T4]],0x1f 6967; MIPS32: sltu [[T0]],[[T0]],[[T4]] 6968; MIPS32: andi [[T0]],[[T0]],0xff 6969; MIPS32: srl [[T5]],[[T5]],0x8 6970; MIPS32: sll [[T5]],[[T5]],0x8 6971; MIPS32: or [[T0]],[[T0]],[[T5]] 6972; MIPS32: move [[T4]],a1 6973; MIPS32: srl [[T4]],[[T4]],0x8 6974; MIPS32: andi [[T4]],[[T4]],0xff 6975; MIPS32: andi [[T4]],[[T4]],0x1 6976; MIPS32: move [[T5]],[[T1]] 6977; MIPS32: srl [[T5]],[[T5]],0x8 6978; MIPS32: andi [[T5]],[[T5]],0xff 6979; MIPS32: andi [[T5]],[[T5]],0x1 6980; MIPS32: sll [[T4]],[[T4]],0x1f 6981; MIPS32: sll [[T5]],[[T5]],0x1f 6982; MIPS32: sltu [[T4]],[[T4]],[[T5]] 6983; MIPS32: andi [[T4]],[[T4]],0xff 6984; MIPS32: sll [[T4]],[[T4]],0x8 6985; MIPS32: lui [[T5]],0xffff 6986; MIPS32: ori [[T5]],[[T5]],0xff 6987; MIPS32: and [[T0]],[[T0]],[[T5]] 6988; MIPS32: or [[T4]],[[T4]],[[T0]] 6989; MIPS32: move [[T0]],a1 6990; MIPS32: srl [[T0]],[[T0]],0x10 6991; MIPS32: andi [[T0]],[[T0]],0xff 6992; MIPS32: andi [[T0]],[[T0]],0x1 6993; MIPS32: move [[T5]],[[T1]] 6994; MIPS32: srl [[T5]],[[T5]],0x10 6995; MIPS32: andi [[T5]],[[T5]],0xff 6996; MIPS32: andi [[T5]],[[T5]],0x1 6997; MIPS32: sll [[T0]],[[T0]],0x1f 6998; MIPS32: sll [[T5]],[[T5]],0x1f 6999; MIPS32: sltu [[T0]],[[T0]],[[T5]] 7000; MIPS32: andi [[T0]],[[T0]],0xff 7001; MIPS32: sll [[T0]],[[T0]],0x10 7002; MIPS32: lui [[T5]],0xff00 7003; MIPS32: ori [[T5]],[[T5]],0xffff 7004; MIPS32: and [[T4]],[[T4]],[[T5]] 7005; MIPS32: or [[T0]],[[T0]],[[T4]] 7006; MIPS32: srl [[T11:.*]],a1,0x18 7007; MIPS32: andi [[T11]],[[T11]],0x1 7008; MIPS32: srl [[T1]],[[T1]],0x18 7009; MIPS32: andi [[T1]],[[T1]],0x1 7010; MIPS32: sll [[T11]],[[T11]],0x1f 7011; MIPS32: sll [[T1]],[[T1]],0x1f 7012; MIPS32: sltu [[T11]],[[T11]],[[T1]] 7013; MIPS32: sll [[T11]],[[T11]],0x18 7014; MIPS32: sll [[T0]],[[T0]],0x8 7015; MIPS32: srl [[T0]],[[T0]],0x8 7016; MIPS32: or [[T11]],[[T11]],[[T0]] 7017; MIPS32: move [[T0]],a2 7018; MIPS32: andi [[T0]],[[T0]],0xff 7019; MIPS32: andi [[T0]],[[T0]],0x1 7020; MIPS32: move [[T1]],[[T2]] 7021; MIPS32: andi [[T1]],[[T1]],0xff 7022; MIPS32: andi [[T1]],[[T1]],0x1 7023; MIPS32: sll [[T0]],[[T0]],0x1f 7024; MIPS32: sll [[T1]],[[T1]],0x1f 7025; MIPS32: sltu [[T0]],[[T0]],[[T1]] 7026; MIPS32: andi [[T0]],[[T0]],0xff 7027; MIPS32: srl [[T6]],[[T6]],0x8 7028; MIPS32: sll [[T6]],[[T6]],0x8 7029; MIPS32: or [[T0]],[[T0]],[[T6]] 7030; MIPS32: move [[T1]],a2 7031; MIPS32: srl [[T1]],[[T1]],0x8 7032; MIPS32: andi [[T1]],[[T1]],0xff 7033; MIPS32: andi [[T1]],[[T1]],0x1 7034; MIPS32: move [[T4]],[[T2]] 7035; MIPS32: srl [[T4]],[[T4]],0x8 7036; MIPS32: andi [[T4]],[[T4]],0xff 7037; MIPS32: andi [[T4]],[[T4]],0x1 7038; MIPS32: sll [[T1]],[[T1]],0x1f 7039; MIPS32: sll [[T4]],[[T4]],0x1f 7040; MIPS32: sltu [[T1]],[[T1]],[[T4]] 7041; MIPS32: andi [[T1]],[[T1]],0xff 7042; MIPS32: sll [[T1]],[[T1]],0x8 7043; MIPS32: lui [[T4]],0xffff 7044; MIPS32: ori [[T4]],[[T4]],0xff 7045; MIPS32: and [[T0]],[[T0]],[[T4]] 7046; MIPS32: or [[T1]],[[T1]],[[T0]] 7047; MIPS32: move [[T0]],a2 7048; MIPS32: srl [[T0]],[[T0]],0x10 7049; MIPS32: andi [[T0]],[[T0]],0xff 7050; MIPS32: andi [[T0]],[[T0]],0x1 7051; MIPS32: move [[T4]],[[T2]] 7052; MIPS32: srl [[T4]],[[T4]],0x10 7053; MIPS32: andi [[T4]],[[T4]],0xff 7054; MIPS32: andi [[T4]],[[T4]],0x1 7055; MIPS32: sll [[T0]],[[T0]],0x1f 7056; MIPS32: sll [[T4]],[[T4]],0x1f 7057; MIPS32: sltu [[T0]],[[T0]],[[T4]] 7058; MIPS32: andi [[T0]],[[T0]],0xff 7059; MIPS32: sll [[T0]],[[T0]],0x10 7060; MIPS32: lui [[T4]],0xff00 7061; MIPS32: ori [[T4]],[[T4]],0xffff 7062; MIPS32: and [[T1]],[[T1]],[[T4]] 7063; MIPS32: or [[T0]],[[T0]],[[T1]] 7064; MIPS32: srl [[T12:.*]],a2,0x18 7065; MIPS32: andi [[T12]],[[T12]],0x1 7066; MIPS32: srl [[T2]],[[T2]],0x18 7067; MIPS32: andi [[T2]],[[T2]],0x1 7068; MIPS32: sll [[T12]],[[T12]],0x1f 7069; MIPS32: sll [[T2]],[[T2]],0x1f 7070; MIPS32: sltu [[T12]],[[T12]],[[T2]] 7071; MIPS32: sll [[T12]],[[T12]],0x18 7072; MIPS32: sll [[T0]],[[T0]],0x8 7073; MIPS32: srl [[T0]],[[T0]],0x8 7074; MIPS32: or [[T12]],[[T12]],[[T0]] 7075; MIPS32: move [[T0]],a3 7076; MIPS32: andi [[T0]],[[T0]],0xff 7077; MIPS32: andi [[T0]],[[T0]],0x1 7078; MIPS32: move [[T1]],[[T3]] 7079; MIPS32: andi [[T1]],[[T1]],0xff 7080; MIPS32: andi [[T1]],[[T1]],0x1 7081; MIPS32: sll [[T0]],[[T0]],0x1f 7082; MIPS32: sll [[T1]],[[T1]],0x1f 7083; MIPS32: sltu [[T0]],[[T0]],[[T1]] 7084; MIPS32: andi [[T0]],[[T0]],0xff 7085; MIPS32: srl [[T7]],[[T7]],0x8 7086; MIPS32: sll [[T7]],[[T7]],0x8 7087; MIPS32: or [[T0]],[[T0]],[[T7]] 7088; MIPS32: move [[T1]],a3 7089; MIPS32: srl [[T1]],[[T1]],0x8 7090; MIPS32: andi [[T1]],[[T1]],0xff 7091; MIPS32: andi [[T1]],[[T1]],0x1 7092; MIPS32: move [[T2]],[[T3]] 7093; MIPS32: srl [[T2]],[[T2]],0x8 7094; MIPS32: andi [[T2]],[[T2]],0xff 7095; MIPS32: andi [[T2]],[[T2]],0x1 7096; MIPS32: sll [[T1]],[[T1]],0x1f 7097; MIPS32: sll [[T2]],[[T2]],0x1f 7098; MIPS32: sltu [[T1]],[[T1]],[[T2]] 7099; MIPS32: andi [[T1]],[[T1]],0xff 7100; MIPS32: sll [[T1]],[[T1]],0x8 7101; MIPS32: lui [[T2]],0xffff 7102; MIPS32: ori [[T2]],[[T2]],0xff 7103; MIPS32: and [[T0]],[[T0]],[[T2]] 7104; MIPS32: or [[T1]],[[T1]],[[T0]] 7105; MIPS32: move [[T0]],a3 7106; MIPS32: srl [[T0]],[[T0]],0x10 7107; MIPS32: andi [[T0]],[[T0]],0xff 7108; MIPS32: andi [[T0]],[[T0]],0x1 7109; MIPS32: move [[T2]],[[T3]] 7110; MIPS32: srl [[T2]],[[T2]],0x10 7111; MIPS32: andi [[T2]],[[T2]],0xff 7112; MIPS32: andi [[T2]],[[T2]],0x1 7113; MIPS32: sll [[T0]],[[T0]],0x1f 7114; MIPS32: sll [[T2]],[[T2]],0x1f 7115; MIPS32: sltu [[T0]],[[T0]],[[T2]] 7116; MIPS32: andi [[T0]],[[T0]],0xff 7117; MIPS32: sll [[T0]],[[T0]],0x10 7118; MIPS32: lui [[T2]],0xff00 7119; MIPS32: ori [[T2]],[[T2]],0xffff 7120; MIPS32: and [[T1]],[[T1]],[[T2]] 7121; MIPS32: or [[T0]],[[T0]],[[T1]] 7122; MIPS32: srl [[T13:.*]],a3,0x18 7123; MIPS32: andi [[T13]],[[T13]],0x1 7124; MIPS32: srl [[T3]],[[T3]],0x18 7125; MIPS32: andi [[T3]],[[T3]],0x1 7126; MIPS32: sll [[T13]],[[T13]],0x1f 7127; MIPS32: sll [[T3]],[[T3]],0x1f 7128; MIPS32: sltu [[T13]],[[T13]],[[T3]] 7129; MIPS32: sll [[T13]],[[T13]],0x18 7130; MIPS32: sll [[T0]],[[T0]],0x8 7131; MIPS32: srl [[T0]],[[T0]],0x8 7132; MIPS32: or [[T13]],[[T13]],[[T0]] 7133; MIPS32: move v0,[[T10]] 7134; MIPS32: move v1,[[T11]] 7135; MIPS32: move a0,[[T12]] 7136; MIPS32: move a1,[[T13]] 7137} 7138