1; This file tests support for the select instruction with vector valued inputs. 2 3; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ 4; RUN: | FileCheck %s 5; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ 6; RUN: | FileCheck %s 7; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \ 8; RUN: | FileCheck --check-prefix=SSE41 %s 9; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \ 10; RUN: | FileCheck --check-prefix=SSE41 %s 11 12; RUN: %if --need=target_MIPS32 --need=allow_dump \ 13; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\ 14; RUN: -i %s --args -O2 \ 15; RUN: | %if --need=target_MIPS32 --need=allow_dump \ 16; RUN: --command FileCheck --check-prefix MIPS32 %s 17 18define internal <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1, 19 <16 x i8> %arg2) { 20entry: 21 %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2 22 ret <16 x i8> %res 23; CHECK-LABEL: test_select_v16i8 24; CHECK: pand 25; CHECK: pandn 26; CHECK: por 27 28; SSE41-LABEL: test_select_v16i8 29; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 30 31; MIPS32-LABEL: test_select_v16i8 32; MIPS32: addiu [[T0:.*]],sp,-32 33; MIPS32: sw [[T1:.*]], 34; MIPS32: sw [[T2:.*]], 35; MIPS32: sw [[T3:.*]], 36; MIPS32: sw [[T4:.*]], 37; MIPS32: sw [[T5:.*]], 38; MIPS32: lw [[T6:.*]], 39; MIPS32: lw [[T7:.*]], 40; MIPS32: lw [[T8:.*]], 41; MIPS32: lw [[T9:.*]], 42; MIPS32: lw [[T10:.*]], 43; MIPS32: lw [[T11:.*]], 44; MIPS32: lw [[T12:.*]], 45; MIPS32: lw [[T13:.*]], 46; MIPS32: move [[T14:.*]],zero 47; MIPS32: move [[T15:.*]],zero 48; MIPS32: move [[T5]],zero 49; MIPS32: move [[T4]],zero 50; MIPS32: move [[T3]],a0 51; MIPS32: andi [[T3]],[[T3]],0xff 52; MIPS32: andi [[T3]],[[T3]],0x1 53; MIPS32: move [[T2]],[[T6]] 54; MIPS32: andi [[T2]],[[T2]],0xff 55; MIPS32: move [[T1]],[[T10]] 56; MIPS32: andi [[T1]],[[T1]],0xff 57; MIPS32: movn [[T1]],[[T2]],[[T3]] 58; MIPS32: andi [[T1]],[[T1]],0xff 59; MIPS32: srl [[T14]],[[T14]],0x8 60; MIPS32: sll [[T14]],[[T14]],0x8 61; MIPS32: or [[T1]],[[T1]],[[T14]] 62; MIPS32: move [[T14]],a0 63; MIPS32: srl [[T14]],[[T14]],0x8 64; MIPS32: andi [[T14]],[[T14]],0xff 65; MIPS32: andi [[T14]],[[T14]],0x1 66; MIPS32: move [[T3]],[[T6]] 67; MIPS32: srl [[T3]],[[T3]],0x8 68; MIPS32: andi [[T3]],[[T3]],0xff 69; MIPS32: move [[T2]],[[T10]] 70; MIPS32: srl [[T2]],[[T2]],0x8 71; MIPS32: andi [[T2]],[[T2]],0xff 72; MIPS32: movn [[T2]],[[T3]],[[T14]] 73; MIPS32: andi [[T2]],[[T2]],0xff 74; MIPS32: sll [[T2]],[[T2]],0x8 75; MIPS32: lui [[T14]],0xffff 76; MIPS32: ori [[T14]],[[T14]],0xff 77; MIPS32: and [[T1]],[[T1]],[[T14]] 78; MIPS32: or [[T2]],[[T2]],[[T1]] 79; MIPS32: move [[T14]],a0 80; MIPS32: srl [[T14]],[[T14]],0x10 81; MIPS32: andi [[T14]],[[T14]],0xff 82; MIPS32: andi [[T14]],[[T14]],0x1 83; MIPS32: move [[T3]],[[T6]] 84; MIPS32: srl [[T3]],[[T3]],0x10 85; MIPS32: andi [[T3]],[[T3]],0xff 86; MIPS32: move [[T1]],[[T10]] 87; MIPS32: srl [[T1]],[[T1]],0x10 88; MIPS32: andi [[T1]],[[T1]],0xff 89; MIPS32: movn [[T1]],[[T3]],[[T14]] 90; MIPS32: andi [[T1]],[[T1]],0xff 91; MIPS32: sll [[T1]],[[T1]],0x10 92; MIPS32: lui [[T14]],0xff00 93; MIPS32: ori [[T14]],[[T14]],0xffff 94; MIPS32: and [[T2]],[[T2]],[[T14]] 95; MIPS32: or [[T1]],[[T1]],[[T2]] 96; MIPS32: srl [[T16:.*]],a0,0x18 97; MIPS32: andi [[T16]],[[T16]],0x1 98; MIPS32: srl [[T6]],[[T6]],0x18 99; MIPS32: srl [[T10]],[[T10]],0x18 100; MIPS32: movn [[T10]],[[T6]],[[T16]] 101; MIPS32: sll [[T10]],[[T10]],0x18 102; MIPS32: sll [[T1]],[[T1]],0x8 103; MIPS32: srl [[T1]],[[T1]],0x8 104; MIPS32: or [[T10]],[[T10]],[[T1]] 105; MIPS32: move [[T6]],a1 106; MIPS32: andi [[T6]],[[T6]],0xff 107; MIPS32: andi [[T6]],[[T6]],0x1 108; MIPS32: move [[T16]],[[T7]] 109; MIPS32: andi [[T16]],[[T16]],0xff 110; MIPS32: move [[T14]],[[T11]] 111; MIPS32: andi [[T14]],[[T14]],0xff 112; MIPS32: movn [[T14]],[[T16]],[[T6]] 113; MIPS32: andi [[T14]],[[T14]],0xff 114; MIPS32: srl [[T15]],[[T15]],0x8 115; MIPS32: sll [[T15]],[[T15]],0x8 116; MIPS32: or [[T14]],[[T14]],[[T15]] 117; MIPS32: move [[T6]],a1 118; MIPS32: srl [[T6]],[[T6]],0x8 119; MIPS32: andi [[T6]],[[T6]],0xff 120; MIPS32: andi [[T6]],[[T6]],0x1 121; MIPS32: move [[T16]],[[T7]] 122; MIPS32: srl [[T16]],[[T16]],0x8 123; MIPS32: andi [[T16]],[[T16]],0xff 124; MIPS32: move [[T15]],[[T11]] 125; MIPS32: srl [[T15]],[[T15]],0x8 126; MIPS32: andi [[T15]],[[T15]],0xff 127; MIPS32: movn [[T15]],[[T16]],[[T6]] 128; MIPS32: andi [[T15]],[[T15]],0xff 129; MIPS32: sll [[T15]],[[T15]],0x8 130; MIPS32: lui [[T6]],0xffff 131; MIPS32: ori [[T6]],[[T6]],0xff 132; MIPS32: and [[T14]],[[T14]],[[T6]] 133; MIPS32: or [[T15]],[[T15]],[[T14]] 134; MIPS32: move [[T6]],a1 135; MIPS32: srl [[T6]],[[T6]],0x10 136; MIPS32: andi [[T6]],[[T6]],0xff 137; MIPS32: andi [[T6]],[[T6]],0x1 138; MIPS32: move [[T16]],[[T7]] 139; MIPS32: srl [[T16]],[[T16]],0x10 140; MIPS32: andi [[T16]],[[T16]],0xff 141; MIPS32: move [[T14]],[[T11]] 142; MIPS32: srl [[T14]],[[T14]],0x10 143; MIPS32: andi [[T14]],[[T14]],0xff 144; MIPS32: movn [[T14]],[[T16]],[[T6]] 145; MIPS32: andi [[T14]],[[T14]],0xff 146; MIPS32: sll [[T14]],[[T14]],0x10 147; MIPS32: lui [[T6]],0xff00 148; MIPS32: ori [[T6]],[[T6]],0xffff 149; MIPS32: and [[T15]],[[T15]],[[T6]] 150; MIPS32: or [[T14]],[[T14]],[[T15]] 151; MIPS32: srl [[T17:.*]],a1,0x18 152; MIPS32: andi [[T17]],[[T17]],0x1 153; MIPS32: srl [[T7]],[[T7]],0x18 154; MIPS32: srl [[T11]],[[T11]],0x18 155; MIPS32: movn [[T11]],[[T7]],[[T17]] 156; MIPS32: sll [[T11]],[[T11]],0x18 157; MIPS32: sll [[T14]],[[T14]],0x8 158; MIPS32: srl [[T14]],[[T14]],0x8 159; MIPS32: or [[T11]],[[T11]],[[T14]] 160; MIPS32: move [[T6]],a2 161; MIPS32: andi [[T6]],[[T6]],0xff 162; MIPS32: andi [[T6]],[[T6]],0x1 163; MIPS32: move [[T7]],[[T8]] 164; MIPS32: andi [[T7]],[[T7]],0xff 165; MIPS32: move [[T16]],[[T12]] 166; MIPS32: andi [[T16]],[[T16]],0xff 167; MIPS32: movn [[T16]],[[T7]],[[T6]] 168; MIPS32: andi [[T16]],[[T16]],0xff 169; MIPS32: srl [[T5]],[[T5]],0x8 170; MIPS32: sll [[T5]],[[T5]],0x8 171; MIPS32: or [[T16]],[[T16]],[[T5]] 172; MIPS32: move [[T6]],a2 173; MIPS32: srl [[T6]],[[T6]],0x8 174; MIPS32: andi [[T6]],[[T6]],0xff 175; MIPS32: andi [[T6]],[[T6]],0x1 176; MIPS32: move [[T7]],[[T8]] 177; MIPS32: srl [[T7]],[[T7]],0x8 178; MIPS32: andi [[T7]],[[T7]],0xff 179; MIPS32: move [[T17]],[[T12]] 180; MIPS32: srl [[T17]],[[T17]],0x8 181; MIPS32: andi [[T17]],[[T17]],0xff 182; MIPS32: movn [[T17]],[[T7]],[[T6]] 183; MIPS32: andi [[T17]],[[T17]],0xff 184; MIPS32: sll [[T17]],[[T17]],0x8 185; MIPS32: lui [[T6]],0xffff 186; MIPS32: ori [[T6]],[[T6]],0xff 187; MIPS32: and [[T16]],[[T16]],[[T6]] 188; MIPS32: or [[T17]],[[T17]],[[T16]] 189; MIPS32: move [[T6]],a2 190; MIPS32: srl [[T6]],[[T6]],0x10 191; MIPS32: andi [[T6]],[[T6]],0xff 192; MIPS32: andi [[T6]],[[T6]],0x1 193; MIPS32: move [[T7]],[[T8]] 194; MIPS32: srl [[T7]],[[T7]],0x10 195; MIPS32: andi [[T7]],[[T7]],0xff 196; MIPS32: move [[T16]],[[T12]] 197; MIPS32: srl [[T16]],[[T16]],0x10 198; MIPS32: andi [[T16]],[[T16]],0xff 199; MIPS32: movn [[T16]],[[T7]],[[T6]] 200; MIPS32: andi [[T16]],[[T16]],0xff 201; MIPS32: sll [[T16]],[[T16]],0x10 202; MIPS32: lui [[T6]],0xff00 203; MIPS32: ori [[T6]],[[T6]],0xffff 204; MIPS32: and [[T17]],[[T17]],[[T6]] 205; MIPS32: or [[T16]],[[T16]],[[T17]] 206; MIPS32: srl [[T18:.*]],a2,0x18 207; MIPS32: andi [[T18]],[[T18]],0x1 208; MIPS32: srl [[T8]],[[T8]],0x18 209; MIPS32: srl [[T12]],[[T12]],0x18 210; MIPS32: movn [[T12]],[[T8]],[[T18]] 211; MIPS32: sll [[T12]],[[T12]],0x18 212; MIPS32: sll [[T16]],[[T16]],0x8 213; MIPS32: srl [[T16]],[[T16]],0x8 214; MIPS32: or [[T12]],[[T12]],[[T16]] 215; MIPS32: move [[T6]],a3 216; MIPS32: andi [[T6]],[[T6]],0xff 217; MIPS32: andi [[T6]],[[T6]],0x1 218; MIPS32: move [[T7]],[[T9]] 219; MIPS32: andi [[T7]],[[T7]],0xff 220; MIPS32: move [[T16]],[[T13]] 221; MIPS32: andi [[T16]],[[T16]],0xff 222; MIPS32: movn [[T16]],[[T7]],[[T6]] 223; MIPS32: andi [[T16]],[[T16]],0xff 224; MIPS32: srl [[T4]],[[T4]],0x8 225; MIPS32: sll [[T4]],[[T4]],0x8 226; MIPS32: or [[T16]],[[T16]],[[T4]] 227; MIPS32: move [[T6]],a3 228; MIPS32: srl [[T6]],[[T6]],0x8 229; MIPS32: andi [[T6]],[[T6]],0xff 230; MIPS32: andi [[T6]],[[T6]],0x1 231; MIPS32: move [[T7]],[[T9]] 232; MIPS32: srl [[T7]],[[T7]],0x8 233; MIPS32: andi [[T7]],[[T7]],0xff 234; MIPS32: move [[T17]],[[T13]] 235; MIPS32: srl [[T17]],[[T17]],0x8 236; MIPS32: andi [[T17]],[[T17]],0xff 237; MIPS32: movn [[T17]],[[T7]],[[T6]] 238; MIPS32: andi [[T17]],[[T17]],0xff 239; MIPS32: sll [[T17]],[[T17]],0x8 240; MIPS32: lui [[T6]],0xffff 241; MIPS32: ori [[T6]],[[T6]],0xff 242; MIPS32: and [[T16]],[[T16]],[[T6]] 243; MIPS32: or [[T17]],[[T17]],[[T16]] 244; MIPS32: move [[T6]],a3 245; MIPS32: srl [[T6]],[[T6]],0x10 246; MIPS32: andi [[T6]],[[T6]],0xff 247; MIPS32: andi [[T6]],[[T6]],0x1 248; MIPS32: move [[T7]],[[T9]] 249; MIPS32: srl [[T7]],[[T7]],0x10 250; MIPS32: andi [[T7]],[[T7]],0xff 251; MIPS32: move [[T16]],[[T13]] 252; MIPS32: srl [[T16]],[[T16]],0x10 253; MIPS32: andi [[T16]],[[T16]],0xff 254; MIPS32: movn [[T16]],[[T7]],[[T6]] 255; MIPS32: andi [[T16]],[[T16]],0xff 256; MIPS32: sll [[T16]],[[T16]],0x10 257; MIPS32: lui [[T6]],0xff00 258; MIPS32: ori [[T6]],[[T6]],0xffff 259; MIPS32: and [[T17]],[[T17]],[[T6]] 260; MIPS32: or [[T16]],[[T16]],[[T17]] 261; MIPS32: srl [[T19:.*]],a3,0x18 262; MIPS32: andi [[T19]],[[T19]],0x1 263; MIPS32: srl [[T9]],[[T9]],0x18 264; MIPS32: srl [[T13]],[[T13]],0x18 265; MIPS32: movn [[T13]],[[T9]],[[T19]] 266; MIPS32: sll [[T13]],[[T13]],0x18 267; MIPS32: sll [[T16]],[[T16]],0x8 268; MIPS32: srl [[T16]],[[T16]],0x8 269; MIPS32: or [[T13]],[[T13]],[[T16]] 270; MIPS32: move v0,[[T10]] 271; MIPS32: move v1,[[T11]] 272; MIPS32: move a0,[[T12]] 273; MIPS32: move a1,[[T13]] 274; MIPS32: lw [[T5]], 275; MIPS32: lw [[T4]], 276; MIPS32: lw [[T3]], 277; MIPS32: lw [[T2]], 278; MIPS32: lw [[T1]], 279; MIPS32: addiu [[T0]],sp,32 280} 281 282define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, 283 <16 x i1> %arg2) { 284entry: 285 %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2 286 ret <16 x i1> %res 287; CHECK-LABEL: test_select_v16i1 288; CHECK: pand 289; CHECK: pandn 290; CHECK: por 291 292; SSE41-LABEL: test_select_v16i1 293; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 294 295; MIPS32-LABEL: test_select_v16i1 296; MIPS32: addiu [[T0:.*]],sp,-32 297; MIPS32: sw [[T1:.*]], 298; MIPS32: sw [[T2:.*]], 299; MIPS32: sw [[T3:.*]], 300; MIPS32: sw [[T4:.*]], 301; MIPS32: sw [[T5:.*]], 302; MIPS32: lw [[T6:.*]], 303; MIPS32: lw [[T7:.*]], 304; MIPS32: lw [[T8:.*]], 305; MIPS32: lw [[T9:.*]], 306; MIPS32: lw [[T10:.*]], 307; MIPS32: lw [[T11:.*]], 308; MIPS32: lw [[T12:.*]], 309; MIPS32: lw [[T13:.*]], 310; MIPS32: move [[T14:.*]],zero 311; MIPS32: move [[T15:.*]],zero 312; MIPS32: move [[T5]],zero 313; MIPS32: move [[T4]],zero 314; MIPS32: move [[T3]],a0 315; MIPS32: andi [[T3]],[[T3]],0xff 316; MIPS32: andi [[T3]],[[T3]],0x1 317; MIPS32: move [[T2]],[[T6]] 318; MIPS32: andi [[T2]],[[T2]],0xff 319; MIPS32: andi [[T2]],[[T2]],0x1 320; MIPS32: move [[T1]],[[T10]] 321; MIPS32: andi [[T1]],[[T1]],0xff 322; MIPS32: andi [[T1]],[[T1]],0x1 323; MIPS32: movn [[T1]],[[T2]],[[T3]] 324; MIPS32: andi [[T1]],[[T1]],0xff 325; MIPS32: srl [[T14]],[[T14]],0x8 326; MIPS32: sll [[T14]],[[T14]],0x8 327; MIPS32: or [[T1]],[[T1]],[[T14]] 328; MIPS32: move [[T14]],a0 329; MIPS32: srl [[T14]],[[T14]],0x8 330; MIPS32: andi [[T14]],[[T14]],0xff 331; MIPS32: andi [[T14]],[[T14]],0x1 332; MIPS32: move [[T3]],[[T6]] 333; MIPS32: srl [[T3]],[[T3]],0x8 334; MIPS32: andi [[T3]],[[T3]],0xff 335; MIPS32: andi [[T3]],[[T3]],0x1 336; MIPS32: move [[T2]],[[T10]] 337; MIPS32: srl [[T2]],[[T2]],0x8 338; MIPS32: andi [[T2]],[[T2]],0xff 339; MIPS32: andi [[T2]],[[T2]],0x1 340; MIPS32: movn [[T2]],[[T3]],[[T14]] 341; MIPS32: andi [[T2]],[[T2]],0xff 342; MIPS32: sll [[T2]],[[T2]],0x8 343; MIPS32: lui [[T14]],0xffff 344; MIPS32: ori [[T14]],[[T14]],0xff 345; MIPS32: and [[T1]],[[T1]],[[T14]] 346; MIPS32: or [[T2]],[[T2]],[[T1]] 347; MIPS32: move [[T14]],a0 348; MIPS32: srl [[T14]],[[T14]],0x10 349; MIPS32: andi [[T14]],[[T14]],0xff 350; MIPS32: andi [[T14]],[[T14]],0x1 351; MIPS32: move [[T3]],[[T6]] 352; MIPS32: srl [[T3]],[[T3]],0x10 353; MIPS32: andi [[T3]],[[T3]],0xff 354; MIPS32: andi [[T3]],[[T3]],0x1 355; MIPS32: move [[T1]],[[T10]] 356; MIPS32: srl [[T1]],[[T1]],0x10 357; MIPS32: andi [[T1]],[[T1]],0xff 358; MIPS32: andi [[T1]],[[T1]],0x1 359; MIPS32: movn [[T1]],[[T3]],[[T14]] 360; MIPS32: andi [[T1]],[[T1]],0xff 361; MIPS32: sll [[T1]],[[T1]],0x10 362; MIPS32: lui [[T14]],0xff00 363; MIPS32: ori [[T14]],[[T14]],0xffff 364; MIPS32: and [[T2]],[[T2]],[[T14]] 365; MIPS32: or [[T1]],[[T1]],[[T2]] 366; MIPS32: srl [[T16:.*]],a0,0x18 367; MIPS32: andi [[T16]],[[T16]],0x1 368; MIPS32: srl [[T6]],[[T6]],0x18 369; MIPS32: andi [[T6]],[[T6]],0x1 370; MIPS32: srl [[T10]],[[T10]],0x18 371; MIPS32: andi [[T10]],[[T10]],0x1 372; MIPS32: movn [[T10]],[[T6]],[[T16]] 373; MIPS32: sll [[T10]],[[T10]],0x18 374; MIPS32: sll [[T1]],[[T1]],0x8 375; MIPS32: srl [[T1]],[[T1]],0x8 376; MIPS32: or [[T10]],[[T10]],[[T1]] 377; MIPS32: move [[T6]],a1 378; MIPS32: andi [[T6]],[[T6]],0xff 379; MIPS32: andi [[T6]],[[T6]],0x1 380; MIPS32: move [[T16]],[[T7]] 381; MIPS32: andi [[T16]],[[T16]],0xff 382; MIPS32: andi [[T16]],[[T16]],0x1 383; MIPS32: move [[T14]],[[T11]] 384; MIPS32: andi [[T14]],[[T14]],0xff 385; MIPS32: andi [[T14]],[[T14]],0x1 386; MIPS32: movn [[T14]],[[T16]],[[T6]] 387; MIPS32: andi [[T14]],[[T14]],0xff 388; MIPS32: srl [[T15]],[[T15]],0x8 389; MIPS32: sll [[T15]],[[T15]],0x8 390; MIPS32: or [[T14]],[[T14]],[[T15]] 391; MIPS32: move [[T6]],a1 392; MIPS32: srl [[T6]],[[T6]],0x8 393; MIPS32: andi [[T6]],[[T6]],0xff 394; MIPS32: andi [[T6]],[[T6]],0x1 395; MIPS32: move [[T16]],[[T7]] 396; MIPS32: srl [[T16]],[[T16]],0x8 397; MIPS32: andi [[T16]],[[T16]],0xff 398; MIPS32: andi [[T16]],[[T16]],0x1 399; MIPS32: move [[T15]],[[T11]] 400; MIPS32: srl [[T15]],[[T15]],0x8 401; MIPS32: andi [[T15]],[[T15]],0xff 402; MIPS32: andi [[T15]],[[T15]],0x1 403; MIPS32: movn [[T15]],[[T16]],[[T6]] 404; MIPS32: andi [[T15]],[[T15]],0xff 405; MIPS32: sll [[T15]],[[T15]],0x8 406; MIPS32: lui [[T6]],0xffff 407; MIPS32: ori [[T6]],[[T6]],0xff 408; MIPS32: and [[T14]],[[T14]],[[T6]] 409; MIPS32: or [[T15]],[[T15]],[[T14]] 410; MIPS32: move [[T6]],a1 411; MIPS32: srl [[T6]],[[T6]],0x10 412; MIPS32: andi [[T6]],[[T6]],0xff 413; MIPS32: andi [[T6]],[[T6]],0x1 414; MIPS32: move [[T16]],[[T7]] 415; MIPS32: srl [[T16]],[[T16]],0x10 416; MIPS32: andi [[T16]],[[T16]],0xff 417; MIPS32: andi [[T16]],[[T16]],0x1 418; MIPS32: move [[T14]],[[T11]] 419; MIPS32: srl [[T14]],[[T14]],0x10 420; MIPS32: andi [[T14]],[[T14]],0xff 421; MIPS32: andi [[T14]],[[T14]],0x1 422; MIPS32: movn [[T14]],[[T16]],[[T6]] 423; MIPS32: andi [[T14]],[[T14]],0xff 424; MIPS32: sll [[T14]],[[T14]],0x10 425; MIPS32: lui [[T6]],0xff00 426; MIPS32: ori [[T6]],[[T6]],0xffff 427; MIPS32: and [[T15]],[[T15]],[[T6]] 428; MIPS32: or [[T14]],[[T14]],[[T15]] 429; MIPS32: srl [[T17:.*]],a1,0x18 430; MIPS32: andi [[T17]],[[T17]],0x1 431; MIPS32: srl [[T7]],[[T7]],0x18 432; MIPS32: andi [[T7]],[[T7]],0x1 433; MIPS32: srl [[T11]],[[T11]],0x18 434; MIPS32: andi [[T11]],[[T11]],0x1 435; MIPS32: movn [[T11]],[[T7]],[[T17]] 436; MIPS32: sll [[T11]],[[T11]],0x18 437; MIPS32: sll [[T14]],[[T14]],0x8 438; MIPS32: srl [[T14]],[[T14]],0x8 439; MIPS32: or [[T11]],[[T11]],[[T14]] 440; MIPS32: move [[T6]],a2 441; MIPS32: andi [[T6]],[[T6]],0xff 442; MIPS32: andi [[T6]],[[T6]],0x1 443; MIPS32: move [[T7]],[[T8]] 444; MIPS32: andi [[T7]],[[T7]],0xff 445; MIPS32: andi [[T7]],[[T7]],0x1 446; MIPS32: move [[T16]],[[T12]] 447; MIPS32: andi [[T16]],[[T16]],0xff 448; MIPS32: andi [[T16]],[[T16]],0x1 449; MIPS32: movn [[T16]],[[T7]],[[T6]] 450; MIPS32: andi [[T16]],[[T16]],0xff 451; MIPS32: srl [[T5]],[[T5]],0x8 452; MIPS32: sll [[T5]],[[T5]],0x8 453; MIPS32: or [[T16]],[[T16]],[[T5]] 454; MIPS32: move [[T6]],a2 455; MIPS32: srl [[T6]],[[T6]],0x8 456; MIPS32: andi [[T6]],[[T6]],0xff 457; MIPS32: andi [[T6]],[[T6]],0x1 458; MIPS32: move [[T7]],[[T8]] 459; MIPS32: srl [[T7]],[[T7]],0x8 460; MIPS32: andi [[T7]],[[T7]],0xff 461; MIPS32: andi [[T7]],[[T7]],0x1 462; MIPS32: move [[T17]],[[T12]] 463; MIPS32: srl [[T17]],[[T17]],0x8 464; MIPS32: andi [[T17]],[[T17]],0xff 465; MIPS32: andi [[T17]],[[T17]],0x1 466; MIPS32: movn [[T17]],[[T7]],[[T6]] 467; MIPS32: andi [[T17]],[[T17]],0xff 468; MIPS32: sll [[T17]],[[T17]],0x8 469; MIPS32: lui [[T6]],0xffff 470; MIPS32: ori [[T6]],[[T6]],0xff 471; MIPS32: and [[T16]],[[T16]],[[T6]] 472; MIPS32: or [[T17]],[[T17]],[[T16]] 473; MIPS32: move [[T6]],a2 474; MIPS32: srl [[T6]],[[T6]],0x10 475; MIPS32: andi [[T6]],[[T6]],0xff 476; MIPS32: andi [[T6]],[[T6]],0x1 477; MIPS32: move [[T7]],[[T8]] 478; MIPS32: srl [[T7]],[[T7]],0x10 479; MIPS32: andi [[T7]],[[T7]],0xff 480; MIPS32: andi [[T7]],[[T7]],0x1 481; MIPS32: move [[T16]],[[T12]] 482; MIPS32: srl [[T16]],[[T16]],0x10 483; MIPS32: andi [[T16]],[[T16]],0xff 484; MIPS32: andi [[T16]],[[T16]],0x1 485; MIPS32: movn [[T16]],[[T7]],[[T6]] 486; MIPS32: andi [[T16]],[[T16]],0xff 487; MIPS32: sll [[T16]],[[T16]],0x10 488; MIPS32: lui [[T6]],0xff00 489; MIPS32: ori [[T6]],[[T6]],0xffff 490; MIPS32: and [[T17]],[[T17]],[[T6]] 491; MIPS32: or [[T16]],[[T16]],[[T17]] 492; MIPS32: srl [[T18:.*]],a2,0x18 493; MIPS32: andi [[T18]],[[T18]],0x1 494; MIPS32: srl [[T8]],[[T8]],0x18 495; MIPS32: andi [[T8]],[[T8]],0x1 496; MIPS32: srl [[T12]],[[T12]],0x18 497; MIPS32: andi [[T12]],[[T12]],0x1 498; MIPS32: movn [[T12]],[[T8]],[[T18]] 499; MIPS32: sll [[T12]],[[T12]],0x18 500; MIPS32: sll [[T16]],[[T16]],0x8 501; MIPS32: srl [[T16]],[[T16]],0x8 502; MIPS32: or [[T12]],[[T12]],[[T16]] 503; MIPS32: move [[T6]],a3 504; MIPS32: andi [[T6]],[[T6]],0xff 505; MIPS32: andi [[T6]],[[T6]],0x1 506; MIPS32: move [[T7]],[[T9]] 507; MIPS32: andi [[T7]],[[T7]],0xff 508; MIPS32: andi [[T7]],[[T7]],0x1 509; MIPS32: move [[T16]],[[T13]] 510; MIPS32: andi [[T16]],[[T16]],0xff 511; MIPS32: andi [[T16]],[[T16]],0x1 512; MIPS32: movn [[T16]],[[T7]],[[T6]] 513; MIPS32: andi [[T16]],[[T16]],0xff 514; MIPS32: srl [[T4]],[[T4]],0x8 515; MIPS32: sll [[T4]],[[T4]],0x8 516; MIPS32: or [[T16]],[[T16]],[[T4]] 517; MIPS32: move [[T6]],a3 518; MIPS32: srl [[T6]],[[T6]],0x8 519; MIPS32: andi [[T6]],[[T6]],0xff 520; MIPS32: andi [[T6]],[[T6]],0x1 521; MIPS32: move [[T7]],[[T9]] 522; MIPS32: srl [[T7]],[[T7]],0x8 523; MIPS32: andi [[T7]],[[T7]],0xff 524; MIPS32: andi [[T7]],[[T7]],0x1 525; MIPS32: move [[T17]],[[T13]] 526; MIPS32: srl [[T17]],[[T17]],0x8 527; MIPS32: andi [[T17]],[[T17]],0xff 528; MIPS32: andi [[T17]],[[T17]],0x1 529; MIPS32: movn [[T17]],[[T7]],[[T6]] 530; MIPS32: andi [[T17]],[[T17]],0xff 531; MIPS32: sll [[T17]],[[T17]],0x8 532; MIPS32: lui [[T6]],0xffff 533; MIPS32: ori [[T6]],[[T6]],0xff 534; MIPS32: and [[T16]],[[T16]],[[T6]] 535; MIPS32: or [[T17]],[[T17]],[[T16]] 536; MIPS32: move [[T6]],a3 537; MIPS32: srl [[T6]],[[T6]],0x10 538; MIPS32: andi [[T6]],[[T6]],0xff 539; MIPS32: andi [[T6]],[[T6]],0x1 540; MIPS32: move [[T7]],[[T9]] 541; MIPS32: srl [[T7]],[[T7]],0x10 542; MIPS32: andi [[T7]],[[T7]],0xff 543; MIPS32: andi [[T7]],[[T7]],0x1 544; MIPS32: move [[T16]],[[T13]] 545; MIPS32: srl [[T16]],[[T16]],0x10 546; MIPS32: andi [[T16]],[[T16]],0xff 547; MIPS32: andi [[T16]],[[T16]],0x1 548; MIPS32: movn [[T16]],[[T7]],[[T6]] 549; MIPS32: andi [[T16]],[[T16]],0xff 550; MIPS32: sll [[T16]],[[T16]],0x10 551; MIPS32: lui [[T6]],0xff00 552; MIPS32: ori [[T6]],[[T6]],0xffff 553; MIPS32: and [[T17]],[[T17]],[[T6]] 554; MIPS32: or [[T16]],[[T16]],[[T17]] 555; MIPS32: srl [[T19:.*]],a3,0x18 556; MIPS32: andi [[T19]],[[T19]],0x1 557; MIPS32: srl [[T9]],[[T9]],0x18 558; MIPS32: andi [[T9]],[[T9]],0x1 559; MIPS32: srl [[T13]],[[T13]],0x18 560; MIPS32: andi [[T13]],[[T13]],0x1 561; MIPS32: movn [[T13]],[[T9]],[[T19]] 562; MIPS32: sll [[T13]],[[T13]],0x18 563; MIPS32: sll [[T16]],[[T16]],0x8 564; MIPS32: srl [[T16]],[[T16]],0x8 565; MIPS32: or [[T13]],[[T13]],[[T16]] 566; MIPS32: move v0,[[T10]] 567; MIPS32: move v1,[[T11]] 568; MIPS32: move a0,[[T12]] 569; MIPS32: move a1,[[T13]] 570; MIPS32: lw [[T5]], 571; MIPS32: lw [[T4]], 572; MIPS32: lw [[T3]], 573; MIPS32: lw [[T2]], 574; MIPS32: lw [[T1]], 575; MIPS32: addiu [[T0]],sp,32 576} 577 578define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, 579 <8 x i16> %arg2) { 580entry: 581 %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 582 ret <8 x i16> %res 583; CHECK-LABEL: test_select_v8i16 584; CHECK: pand 585; CHECK: pandn 586; CHECK: por 587 588; SSE41-LABEL: test_select_v8i16 589; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 590 591; MIPS32-LABEL: test_select_v8i16 592; MIPS32: addiu [[T0:.*]],sp,-32 593; MIPS32: sw [[T1:.*]], 594; MIPS32: sw [[T2:.*]], 595; MIPS32: sw [[T3:.*]], 596; MIPS32: sw [[T4:.*]], 597; MIPS32: sw [[T5:.*]], 598; MIPS32: lw [[T6:.*]], 599; MIPS32: lw [[T7:.*]], 600; MIPS32: lw [[T8:.*]], 601; MIPS32: lw [[T9:.*]], 602; MIPS32: lw [[T10:.*]], 603; MIPS32: lw [[T11:.*]], 604; MIPS32: lw [[T12:.*]], 605; MIPS32: lw [[T13:.*]], 606; MIPS32: move [[T14:.*]],zero 607; MIPS32: move [[T15:.*]],zero 608; MIPS32: move [[T5]],zero 609; MIPS32: move [[T4]],zero 610; MIPS32: move [[T3]],a0 611; MIPS32: andi [[T3]],[[T3]],0xffff 612; MIPS32: andi [[T3]],[[T3]],0x1 613; MIPS32: move [[T2]],[[T6]] 614; MIPS32: andi [[T2]],[[T2]],0xffff 615; MIPS32: move [[T1]],[[T10]] 616; MIPS32: andi [[T1]],[[T1]],0xffff 617; MIPS32: movn [[T1]],[[T2]],[[T3]] 618; MIPS32: andi [[T1]],[[T1]],0xffff 619; MIPS32: srl [[T14]],[[T14]],0x10 620; MIPS32: sll [[T14]],[[T14]],0x10 621; MIPS32: or [[T1]],[[T1]],[[T14]] 622; MIPS32: srl [[T16:.*]],a0,0x10 623; MIPS32: andi [[T16]],[[T16]],0x1 624; MIPS32: srl [[T6]],[[T6]],0x10 625; MIPS32: srl [[T10]],[[T10]],0x10 626; MIPS32: movn [[T10]],[[T6]],[[T16]] 627; MIPS32: sll [[T10]],[[T10]],0x10 628; MIPS32: sll [[T1]],[[T1]],0x10 629; MIPS32: srl [[T1]],[[T1]],0x10 630; MIPS32: or [[T10]],[[T10]],[[T1]] 631; MIPS32: move [[T6]],a1 632; MIPS32: andi [[T6]],[[T6]],0xffff 633; MIPS32: andi [[T6]],[[T6]],0x1 634; MIPS32: move [[T16]],[[T7]] 635; MIPS32: andi [[T16]],[[T16]],0xffff 636; MIPS32: move [[T14]],[[T11]] 637; MIPS32: andi [[T14]],[[T14]],0xffff 638; MIPS32: movn [[T14]],[[T16]],[[T6]] 639; MIPS32: andi [[T14]],[[T14]],0xffff 640; MIPS32: srl [[T15]],[[T15]],0x10 641; MIPS32: sll [[T15]],[[T15]],0x10 642; MIPS32: or [[T14]],[[T14]],[[T15]] 643; MIPS32: srl [[T17:.*]],a1,0x10 644; MIPS32: andi [[T17]],[[T17]],0x1 645; MIPS32: srl [[T7]],[[T7]],0x10 646; MIPS32: srl [[T11]],[[T11]],0x10 647; MIPS32: movn [[T11]],[[T7]],[[T17]] 648; MIPS32: sll [[T11]],[[T11]],0x10 649; MIPS32: sll [[T14]],[[T14]],0x10 650; MIPS32: srl [[T14]],[[T14]],0x10 651; MIPS32: or [[T11]],[[T11]],[[T14]] 652; MIPS32: move [[T6]],a2 653; MIPS32: andi [[T6]],[[T6]],0xffff 654; MIPS32: andi [[T6]],[[T6]],0x1 655; MIPS32: move [[T7]],[[T8]] 656; MIPS32: andi [[T7]],[[T7]],0xffff 657; MIPS32: move [[T16]],[[T12]] 658; MIPS32: andi [[T16]],[[T16]],0xffff 659; MIPS32: movn [[T16]],[[T7]],[[T6]] 660; MIPS32: andi [[T16]],[[T16]],0xffff 661; MIPS32: srl [[T5]],[[T5]],0x10 662; MIPS32: sll [[T5]],[[T5]],0x10 663; MIPS32: or [[T16]],[[T16]],[[T5]] 664; MIPS32: srl [[T18:.*]],a2,0x10 665; MIPS32: andi [[T18]],[[T18]],0x1 666; MIPS32: srl [[T8]],[[T8]],0x10 667; MIPS32: srl [[T12]],[[T12]],0x10 668; MIPS32: movn [[T12]],[[T8]],[[T18]] 669; MIPS32: sll [[T12]],[[T12]],0x10 670; MIPS32: sll [[T16]],[[T16]],0x10 671; MIPS32: srl [[T16]],[[T16]],0x10 672; MIPS32: or [[T12]],[[T12]],[[T16]] 673; MIPS32: move [[T6]],a3 674; MIPS32: andi [[T6]],[[T6]],0xffff 675; MIPS32: andi [[T6]],[[T6]],0x1 676; MIPS32: move [[T7]],[[T9]] 677; MIPS32: andi [[T7]],[[T7]],0xffff 678; MIPS32: move [[T16]],[[T13]] 679; MIPS32: andi [[T16]],[[T16]],0xffff 680; MIPS32: movn [[T16]],[[T7]],[[T6]] 681; MIPS32: andi [[T16]],[[T16]],0xffff 682; MIPS32: srl [[T4]],[[T4]],0x10 683; MIPS32: sll [[T4]],[[T4]],0x10 684; MIPS32: or [[T16]],[[T16]],[[T4]] 685; MIPS32: srl [[T19:.*]],a3,0x10 686; MIPS32: andi [[T19]],[[T19]],0x1 687; MIPS32: srl [[T9]],[[T9]],0x10 688; MIPS32: srl [[T13]],[[T13]],0x10 689; MIPS32: movn [[T13]],[[T9]],[[T19]] 690; MIPS32: sll [[T13]],[[T13]],0x10 691; MIPS32: sll [[T16]],[[T16]],0x10 692; MIPS32: srl [[T16]],[[T16]],0x10 693; MIPS32: or [[T13]],[[T13]],[[T16]] 694; MIPS32: move v0,[[T10]] 695; MIPS32: move v1,[[T11]] 696; MIPS32: move a0,[[T12]] 697; MIPS32: move a1,[[T13]] 698; MIPS32: lw [[T5]], 699; MIPS32: lw [[T4]], 700; MIPS32: lw [[T3]], 701; MIPS32: lw [[T2]], 702; MIPS32: lw [[T1]], 703; MIPS32: addiu [[T0]],sp,32 704} 705 706define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, 707 <8 x i1> %arg2) { 708entry: 709 %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 710 ret <8 x i1> %res 711; CHECK-LABEL: test_select_v8i1 712; CHECK: pand 713; CHECK: pandn 714; CHECK: por 715 716; SSE41-LABEL: test_select_v8i1 717; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 718 719; MIPS32-LABEL: test_select_v8i1 720; MIPS32: addiu [[T0:.*]],sp,-32 721; MIPS32: sw [[T1:.*]], 722; MIPS32: sw [[T2:.*]], 723; MIPS32: sw [[T3:.*]], 724; MIPS32: sw [[T4:.*]], 725; MIPS32: sw [[T5:.*]], 726; MIPS32: lw [[T6:.*]], 727; MIPS32: lw [[T7:.*]], 728; MIPS32: lw [[T8:.*]], 729; MIPS32: lw [[T9:.*]], 730; MIPS32: lw [[T10:.*]], 731; MIPS32: lw [[T11:.*]], 732; MIPS32: lw [[T12:.*]], 733; MIPS32: lw [[T13:.*]], 734; MIPS32: move [[T14:.*]],zero 735; MIPS32: move [[T15:.*]],zero 736; MIPS32: move [[T5]],zero 737; MIPS32: move [[T4]],zero 738; MIPS32: move [[T3]],a0 739; MIPS32: andi [[T3]],[[T3]],0xffff 740; MIPS32: andi [[T3]],[[T3]],0x1 741; MIPS32: move [[T2]],[[T6]] 742; MIPS32: andi [[T2]],[[T2]],0xffff 743; MIPS32: andi [[T2]],[[T2]],0x1 744; MIPS32: move [[T1]],[[T10]] 745; MIPS32: andi [[T1]],[[T1]],0xffff 746; MIPS32: andi [[T1]],[[T1]],0x1 747; MIPS32: movn [[T1]],[[T2]],[[T3]] 748; MIPS32: andi [[T1]],[[T1]],0xffff 749; MIPS32: srl [[T14]],[[T14]],0x10 750; MIPS32: sll [[T14]],[[T14]],0x10 751; MIPS32: or [[T1]],[[T1]],[[T14]] 752; MIPS32: srl [[T16:.*]],a0,0x10 753; MIPS32: andi [[T16]],[[T16]],0x1 754; MIPS32: srl [[T6]],[[T6]],0x10 755; MIPS32: andi [[T6]],[[T6]],0x1 756; MIPS32: srl [[T10]],[[T10]],0x10 757; MIPS32: andi [[T10]],[[T10]],0x1 758; MIPS32: movn [[T10]],[[T6]],[[T16]] 759; MIPS32: sll [[T10]],[[T10]],0x10 760; MIPS32: sll [[T1]],[[T1]],0x10 761; MIPS32: srl [[T1]],[[T1]],0x10 762; MIPS32: or [[T10]],[[T10]],[[T1]] 763; MIPS32: move [[T6]],a1 764; MIPS32: andi [[T6]],[[T6]],0xffff 765; MIPS32: andi [[T6]],[[T6]],0x1 766; MIPS32: move [[T16]],[[T7]] 767; MIPS32: andi [[T16]],[[T16]],0xffff 768; MIPS32: andi [[T16]],[[T16]],0x1 769; MIPS32: move [[T14]],[[T11]] 770; MIPS32: andi [[T14]],[[T14]],0xffff 771; MIPS32: andi [[T14]],[[T14]],0x1 772; MIPS32: movn [[T14]],[[T16]],[[T6]] 773; MIPS32: andi [[T14]],[[T14]],0xffff 774; MIPS32: srl [[T15]],[[T15]],0x10 775; MIPS32: sll [[T15]],[[T15]],0x10 776; MIPS32: or [[T14]],[[T14]],[[T15]] 777; MIPS32: srl [[T17:.*]],a1,0x10 778; MIPS32: andi [[T17]],[[T17]],0x1 779; MIPS32: srl [[T7]],[[T7]],0x10 780; MIPS32: andi [[T7]],[[T7]],0x1 781; MIPS32: srl [[T11]],[[T11]],0x10 782; MIPS32: andi [[T11]],[[T11]],0x1 783; MIPS32: movn [[T11]],[[T7]],[[T17]] 784; MIPS32: sll [[T11]],[[T11]],0x10 785; MIPS32: sll [[T14]],[[T14]],0x10 786; MIPS32: srl [[T14]],[[T14]],0x10 787; MIPS32: or [[T11]],[[T11]],[[T14]] 788; MIPS32: move [[T6]],a2 789; MIPS32: andi [[T6]],[[T6]],0xffff 790; MIPS32: andi [[T6]],[[T6]],0x1 791; MIPS32: move [[T7]],[[T8]] 792; MIPS32: andi [[T7]],[[T7]],0xffff 793; MIPS32: andi [[T7]],[[T7]],0x1 794; MIPS32: move [[T16]],[[T12]] 795; MIPS32: andi [[T16]],[[T16]],0xffff 796; MIPS32: andi [[T16]],[[T16]],0x1 797; MIPS32: movn [[T16]],[[T7]],[[T6]] 798; MIPS32: andi [[T16]],[[T16]],0xffff 799; MIPS32: srl [[T5]],[[T5]],0x10 800; MIPS32: sll [[T5]],[[T5]],0x10 801; MIPS32: or [[T16]],[[T16]],[[T5]] 802; MIPS32: srl [[T18:.*]],a2,0x10 803; MIPS32: andi [[T18]],[[T18]],0x1 804; MIPS32: srl [[T8]],[[T8]],0x10 805; MIPS32: andi [[T8]],[[T8]],0x1 806; MIPS32: srl [[T12]],[[T12]],0x10 807; MIPS32: andi [[T12]],[[T12]],0x1 808; MIPS32: movn [[T12]],[[T8]],[[T18]] 809; MIPS32: sll [[T12]],[[T12]],0x10 810; MIPS32: sll [[T16]],[[T16]],0x10 811; MIPS32: srl [[T16]],[[T16]],0x10 812; MIPS32: or [[T12]],[[T12]],[[T16]] 813; MIPS32: move [[T6]],a3 814; MIPS32: andi [[T6]],[[T6]],0xffff 815; MIPS32: andi [[T6]],[[T6]],0x1 816; MIPS32: move [[T7]],[[T9]] 817; MIPS32: andi [[T7]],[[T7]],0xffff 818; MIPS32: andi [[T7]],[[T7]],0x1 819; MIPS32: move [[T16]],[[T13]] 820; MIPS32: andi [[T16]],[[T16]],0xffff 821; MIPS32: andi [[T16]],[[T16]],0x1 822; MIPS32: movn [[T16]],[[T7]],[[T6]] 823; MIPS32: andi [[T16]],[[T16]],0xffff 824; MIPS32: srl [[T4]],[[T4]],0x10 825; MIPS32: sll [[T4]],[[T4]],0x10 826; MIPS32: or [[T16]],[[T16]],[[T4]] 827; MIPS32: srl [[T19:.*]],a3,0x10 828; MIPS32: andi [[T19]],[[T19]],0x1 829; MIPS32: srl [[T9]],[[T9]],0x10 830; MIPS32: andi [[T9]],[[T9]],0x1 831; MIPS32: srl [[T13]],[[T13]],0x10 832; MIPS32: andi [[T13]],[[T13]],0x1 833; MIPS32: movn [[T13]],[[T9]],[[T19]] 834; MIPS32: sll [[T13]],[[T13]],0x10 835; MIPS32: sll [[T16]],[[T16]],0x10 836; MIPS32: srl [[T16]],[[T16]],0x10 837; MIPS32: or [[T13]],[[T13]],[[T16]] 838; MIPS32: move v0,[[T10]] 839; MIPS32: move v1,[[T11]] 840; MIPS32: move a0,[[T12]] 841; MIPS32: move a1,[[T13]] 842; MIPS32: lw [[T5]], 843; MIPS32: lw [[T4]], 844; MIPS32: lw [[T3]], 845; MIPS32: lw [[T2]], 846; MIPS32: lw [[T1]], 847; MIPS32: addiu [[T0]],sp,32 848} 849 850define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, 851 <4 x i32> %arg2) { 852entry: 853 %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 854 ret <4 x i32> %res 855; CHECK-LABEL: test_select_v4i32 856; CHECK: pand 857; CHECK: pandn 858; CHECK: por 859 860; SSE41-LABEL: test_select_v4i32 861; SSE41: pslld xmm0,0x1f 862; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 863 864; MIPS32-LABEL: test_select_v4i32 865; MIPS32: lw [[T0:.*]], 866; MIPS32: lw [[T1:.*]], 867; MIPS32: lw [[T2:.*]], 868; MIPS32: lw [[T3:.*]], 869; MIPS32: lw [[T4:.*]], 870; MIPS32: lw [[T5:.*]], 871; MIPS32: lw [[T6:.*]], 872; MIPS32: lw [[T7:.*]], 873; MIPS32: andi [[T8:.*]],a0,0x1 874; MIPS32: movn [[T4]],[[T0]],[[T8]] 875; MIPS32: andi [[T9:.*]],a1,0x1 876; MIPS32: movn [[T5]],[[T1]],[[T9]] 877; MIPS32: andi [[T10:.*]],a2,0x1 878; MIPS32: movn [[T6]],[[T2]],[[T10]] 879; MIPS32: andi [[T11:.*]],a3,0x1 880; MIPS32: movn [[T7]],[[T3]],[[T11]] 881; MIPS32: move v0,[[T4]] 882; MIPS32: move v1,[[T5]] 883; MIPS32: move a0,[[T6]] 884; MIPS32: move a1,[[T7]] 885} 886 887define internal <4 x float> @test_select_v4f32( 888 <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) { 889entry: 890 %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2 891 ret <4 x float> %res 892; CHECK-LABEL: test_select_v4f32 893; CHECK: pand 894; CHECK: pandn 895; CHECK: por 896 897; SSE41-LABEL: test_select_v4f32 898; SSE41: pslld xmm0,0x1f 899; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 900 901; MIPS32-LABEL: test_select_v4f32 902; MIPS32: lw [[T0:.*]], 903; MIPS32: lw [[T1:.*]], 904; MIPS32: lw [[T2:.*]], 905; MIPS32: lw [[T3:.*]], 906; MIPS32: lw [[T4:.*]], 907; MIPS32: lw [[T5:.*]], 908; MIPS32: lw [[T6:.*]], 909; MIPS32: lw [[T7:.*]], 910; MIPS32: lw [[T8:.*]], 911; MIPS32: lw [[T9:.*]], 912; MIPS32: andi [[T10:.*]],a2,0x1 913; MIPS32: mtc1 [[T2]],$f0 914; MIPS32: mtc1 [[T6]],$f1 915; MIPS32: movn.s [[T11:.*]],$f0,[[T10]] 916; MIPS32: mfc1 [[T2]],[[T11]] 917; MIPS32: andi [[T12:.*]],a3,0x1 918; MIPS32: mtc1 [[T3]],$f0 919; MIPS32: mtc1 [[T7]],[[T11]] 920; MIPS32: movn.s [[T11]],$f0,[[T12]] 921; MIPS32: mfc1 [[T3]],[[T11]] 922; MIPS32: andi [[T0]],[[T0]],0x1 923; MIPS32: mtc1 [[T4]],$f0 924; MIPS32: mtc1 [[T8]],[[T11]] 925; MIPS32: movn.s [[T11]],$f0,[[T0]] 926; MIPS32: mfc1 [[T4]],[[T11]] 927; MIPS32: andi [[T1]],[[T1]],0x1 928; MIPS32: mtc1 [[T5]],$f0 929; MIPS32: mtc1 [[T9]],[[T11]] 930; MIPS32: movn.s [[T11]],$f0,[[T1]] 931; MIPS32: mfc1 [[T10]],[[T11]] 932; MIPS32: move [[T12]],a0 933; MIPS32: sw [[T2]],0(a3) 934; MIPS32: sw v1,4(a3) 935; MIPS32: sw a1,8(a3) 936; MIPS32: sw [[T10]],12(a3) 937; MIPS32: move v0,a0 938} 939 940define internal <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, 941 <4 x i1> %arg2) { 942entry: 943 %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 944 ret <4 x i1> %res 945; CHECK-LABEL: test_select_v4i1 946; CHECK: pand 947; CHECK: pandn 948; CHECK: por 949 950; SSE41-LABEL: test_select_v4i1 951; SSE41: pslld xmm0,0x1f 952; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} 953 954; MIPS32-LABEL: test_select_v4i1 955; MIPS32: lw [[T0:.*]], 956; MIPS32: lw [[T1:.*]], 957; MIPS32: lw [[T2:.*]], 958; MIPS32: lw [[T3:.*]], 959; MIPS32: lw [[T4:.*]], 960; MIPS32: lw [[T5:.*]], 961; MIPS32: lw [[T6:.*]], 962; MIPS32: lw [[T7:.*]], 963; MIPS32: andi [[T8:.*]],a0,0x1 964; MIPS32: andi [[T0]],[[T0]],0x1 965; MIPS32: andi [[T4]],[[T4]],0x1 966; MIPS32: movn [[T4]],[[T0]],[[T8]] 967; MIPS32: andi [[T9:.*]],a1,0x1 968; MIPS32: andi [[T1]],[[T1]],0x1 969; MIPS32: andi [[T5]],[[T5]],0x1 970; MIPS32: movn [[T5]],[[T1]],[[T9]] 971; MIPS32: andi [[T10:.*]],a2,0x1 972; MIPS32: andi [[T2]],[[T2]],0x1 973; MIPS32: andi [[T6]],[[T6]],0x1 974; MIPS32: movn [[T6]],[[T2]],[[T10]] 975; MIPS32: andi [[T11:.*]],a3,0x1 976; MIPS32: andi [[T3]],[[T3]],0x1 977; MIPS32: andi [[T7]],[[T7]],0x1 978; MIPS32: movn [[T7]],[[T3]],[[T11]] 979; MIPS32: move v0,[[T4]] 980; MIPS32: move v1,[[T5]] 981; MIPS32: move a0,[[T6]] 982; MIPS32: move a1,[[T7]] 983} 984