Lines Matching refs:ldr
23 ldr r0, =PSSR
27 ldr ip, [r3]
63 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
70 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
73 1: ldr r0, [r1, #PXA3_DDR_HCAL]
77 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
84 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
88 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
93 1: ldr r0, [r1, #PXA3_DMCISR]
97 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
100 1: ldr r0, [r1, #PXA3_MDCNFG]
104 ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
108 ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt