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1/*
2 * PXA27x standby mode
3 *
4 * Author: David Burrage
5 *
6 * 2005 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12#include <linux/linkage.h>
13#include <asm/assembler.h>
14#include <mach/hardware.h>
15
16#include <mach/pxa-regs.h>
17#include <mach/pxa2xx-regs.h>
18
19		.text
20
21#ifdef CONFIG_PXA27x
22ENTRY(pxa_cpu_standby)
23	ldr	r0, =PSSR
24	mov	r1, #(PSSR_PH | PSSR_STS)
25	mov	r2, #PWRMODE_STANDBY
26	mov	r3, #UNCACHED_PHYS_0	@ Read mem context in.
27	ldr	ip, [r3]
28	b	1f
29
30	.align	5
311:	mcr	p14, 0, r2, c7, c0, 0	@ put the system into Standby
32	str	r1, [r0]		@ make sure PSSR_PH/STS are clear
33	mov	pc, lr
34
35#endif
36
37#ifdef CONFIG_PXA3xx
38
39#define PXA3_MDCNFG		0x0000
40#define PXA3_MDCNFG_DMCEN	(1 << 30)
41#define PXA3_DDR_HCAL		0x0060
42#define PXA3_DDR_HCAL_HCRNG	0x1f
43#define PXA3_DDR_HCAL_HCPROG	(1 << 28)
44#define PXA3_DDR_HCAL_HCEN	(1 << 31)
45#define PXA3_DMCIER		0x0070
46#define PXA3_DMCIER_EDLP	(1 << 29)
47#define PXA3_DMCISR		0x0078
48#define PXA3_RCOMP		0x0100
49#define PXA3_RCOMP_SWEVAL	(1 << 31)
50
51ENTRY(pm_enter_standby_start)
52	mov	r1, #0xf6000000			@ DMEMC_REG_BASE (PXA3_MDCNFG)
53	add	r1, r1, #0x00100000
54
55	/*
56	 * Preload the TLB entry for accessing the dynamic memory
57	 * controller registers.  Note that page table lookups will
58	 * fail until the dynamic memory controller has been
59	 * reinitialised - and that includes MMU page table walks.
60	 * This also means that only the dynamic memory controller
61	 * can be reliably accessed in the code following standby.
62	 */
63	ldr	r2, [r1]			@ Dummy read PXA3_MDCNFG
64
65	mcr	p14, 0, r0, c7, c0, 0
66	.rept	8
67	nop
68	.endr
69
70	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ Clear (and wait for) HCEN
71	bic	r0, r0, #PXA3_DDR_HCAL_HCEN
72	str	r0, [r1, #PXA3_DDR_HCAL]
731:	ldr	r0, [r1, #PXA3_DDR_HCAL]
74	tst	r0, #PXA3_DDR_HCAL_HCEN
75	bne	1b
76
77	ldr	r0, [r1, #PXA3_RCOMP]		@ Initiate RCOMP
78	orr	r0, r0, #PXA3_RCOMP_SWEVAL
79	str	r0, [r1, #PXA3_RCOMP]
80
81	mov	r0, #~0				@ Clear interrupts
82	str	r0, [r1, #PXA3_DMCISR]
83
84	ldr	r0, [r1, #PXA3_DMCIER]		@ set DMIER[EDLP]
85	orr	r0, r0, #PXA3_DMCIER_EDLP
86	str	r0, [r1, #PXA3_DMCIER]
87
88	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ clear HCRNG, set HCPROG, HCEN
89	bic	r0, r0, #PXA3_DDR_HCAL_HCRNG
90	orr	r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
91	str	r0, [r1, #PXA3_DDR_HCAL]
92
931:	ldr	r0, [r1, #PXA3_DMCISR]
94	tst	r0, #PXA3_DMCIER_EDLP
95	beq	1b
96
97	ldr	r0, [r1, #PXA3_MDCNFG]		@ set PXA3_MDCNFG[DMCEN]
98	orr	r0, r0, #PXA3_MDCNFG_DMCEN
99	str	r0, [r1, #PXA3_MDCNFG]
1001:	ldr	r0, [r1, #PXA3_MDCNFG]
101	tst	r0, #PXA3_MDCNFG_DMCEN
102	beq	1b
103
104	ldr	r0, [r1, #PXA3_DDR_HCAL]	@ set PXA3_DDR_HCAL[HCRNG]
105	orr	r0, r0, #2 @ HCRNG
106	str	r0, [r1, #PXA3_DDR_HCAL]
107
108	ldr	r0, [r1, #PXA3_DMCIER]		@ Clear the interrupt
109	bic	r0, r0, #0x20000000
110	str	r0, [r1, #PXA3_DMCIER]
111
112	mov	pc, lr
113ENTRY(pm_enter_standby_end)
114
115#endif
116