Searched refs:DMA_CCR (Results 1 – 2 of 2) sorted by relevance
56 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ macro223 DMA_BASE + DMA_CCR(channel)); in imx_dma_setup_single()233 DMA_BASE + DMA_CCR(channel)); in imx_dma_setup_single()320 DMA_BASE + DMA_CCR(channel)); in imx_dma_setup_sg()328 DMA_BASE + DMA_CCR(channel)); in imx_dma_setup_sg()467 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN | in imx_dma_enable()469 DMA_BASE + DMA_CCR(channel)); in imx_dma_enable()477 tmp = __raw_readl(DMA_BASE + DMA_CCR(channel)); in imx_dma_enable()479 DMA_BASE + DMA_CCR(channel)); in imx_dma_enable()506 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN, in imx_dma_disable()[all …]
26 #define DMA_CCR(chan) (chan->mmr_base + 0x0) macro772 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); in iop_chan_append()774 __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); in iop_chan_append()784 u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); in iop_chan_disable()786 __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); in iop_chan_disable()791 u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); in iop_chan_enable()794 __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); in iop_chan_enable()