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Searched refs:DR (Results 1 – 16 of 16) sorted by relevance

/arch/arm/mach-imx/
Dleds-mx1ads.c37 DR(0) &= ~(1<<2); in mx1ads_leds_event()
41 DR(0) |= 1<<2; in mx1ads_leds_event()
47 DR(0) ^= 1<<2; in mx1ads_leds_event()
/arch/s390/math-emu/
Dmath.c169 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR); in emu_adbr()
176 FP_ADD_D(DR, DA, DB); in emu_adbr()
177 FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR); in emu_adbr()
184 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR); in emu_adb()
191 FP_ADD_D(DR, DA, DB); in emu_adb()
192 FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR); in emu_adb()
431 FP_DECL_D(DR); in emu_cdfbr()
438 FP_FROM_INT_D(DR, si, 32, int); in emu_cdfbr()
439 FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR); in emu_cdfbr()
543 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR); in emu_ddbr()
[all …]
/arch/alpha/math-emu/
Dmath.c102 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR); in alpha_fp_emul()
197 FP_SUB_D(DR, DA, DB); in alpha_fp_emul()
201 FP_ADD_D(DR, DA, DB); in alpha_fp_emul()
205 FP_MUL_D(DR, DA, DB); in alpha_fp_emul()
209 FP_DIV_D(DR, DA, DB); in alpha_fp_emul()
213 FP_SQRT_D(DR, DB); in alpha_fp_emul()
263 FP_FROM_INT_D(DR, ((long)vb), 64, long); in alpha_fp_emul()
278 FP_PACK_DP(&vc, DR); in alpha_fp_emul()
/arch/sparc/math-emu/
Dmath_32.c283 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR); in do_one_mathemu()
425 case FADDD: FP_ADD_D (DR, DA, DB); break; in do_one_mathemu()
429 case FSUBD: FP_SUB_D (DR, DA, DB); break; in do_one_mathemu()
435 case FMULD: FP_MUL_D (DR, DA, DB); break; in do_one_mathemu()
441 case FDIVD: FP_DIV_D (DR, DA, DB); break; in do_one_mathemu()
445 case FSQRTD: FP_SQRT_D (DR, DB); break; in do_one_mathemu()
457 case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break; in do_one_mathemu()
460 case FSTOD: FP_CONV (D, S, 2, 1, DR, SB); break; in do_one_mathemu()
465 case FQTOD: FP_CONV (D, Q, 2, 4, DR, QB); break; in do_one_mathemu()
504 case 6: FP_PACK_DP (rd, DR); break; in do_one_mathemu()
Dmath_64.c179 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR); in do_mathemu()
422 case FADDD: FP_ADD_D (DR, DA, DB); break; in do_mathemu()
426 case FSUBD: FP_SUB_D (DR, DA, DB); break; in do_mathemu()
432 case FMULD: FP_MUL_D (DR, DA, DB); break; in do_mathemu()
438 case FDIVD: FP_DIV_D (DR, DA, DB); break; in do_mathemu()
442 case FSQRTD: FP_SQRT_D (DR, DB); break; in do_mathemu()
460 case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break; in do_mathemu()
464 case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break; in do_mathemu()
466 case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break; in do_mathemu()
471 case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break; in do_mathemu()
[all …]
/arch/arm/mach-imx/include/mach/
Dgpio.h36 DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK)); in imx_gpio_set_value_inline()
38 DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK)); in imx_gpio_set_value_inline()
Dimx-regs.h69 #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) macro
/arch/powerpc/math-emu/
Dmath_efp.c351 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR); in do_spe_mathemu()
386 FP_ADD_D(DR, DA, DB); in do_spe_mathemu()
390 FP_SUB_D(DR, DA, DB); in do_spe_mathemu()
394 FP_MUL_D(DR, DA, DB); in do_spe_mathemu()
398 FP_DIV_D(DR, DA, DB); in do_spe_mathemu()
442 FP_CONV(D, S, 2, 1, DR, SB); in do_spe_mathemu()
474 FP_PACK_DP(vc.dp, DR); in do_spe_mathemu()
/arch/sh/math-emu/
Dmath.c40 #define DR ((unsigned long long*)(fregs->fp_regs)) macro
41 #define DRn (DR[BANK(n)/2])
42 #define DRm (DR[BANK(m)/2])
47 #define XDn (DR[BANK(XREG(n))/2])
48 #define XDm (DR[BANK(XREG(m))/2])
/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h571 #define DR 0x01 macro
/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h988 #define DR 0x01 macro
/arch/blackfin/mach-bf518/include/mach/
DdefBF51x_base.h858 #define DR 0x01 /* Data Ready */ macro
/arch/blackfin/mach-bf527/include/mach/
DdefBF52x_base.h859 #define DR 0x01 /* Data Ready */ macro
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h1131 #define DR 0x01 /* Data Ready */ macro
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h3411 #define DR 0x1 /* Data Ready */ macro
/arch/blackfin/mach-bf538/include/mach/
DdefBF539.h1708 #define DR 0x01 /* Data Ready */ macro