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1 /*
2  * arch/sparc/math-emu/math.c
3  *
4  * Copyright (C) 1998 Peter Maydell (pmaydell@chiark.greenend.org.uk)
5  * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
6  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
7  *
8  * This is a good place to start if you're trying to understand the
9  * emulation code, because it's pretty simple. What we do is
10  * essentially analyse the instruction to work out what the operation
11  * is and which registers are involved. We then execute the appropriate
12  * FXXXX function. [The floating point queue introduces a minor wrinkle;
13  * see below...]
14  * The fxxxxx.c files each emulate a single insn. They look relatively
15  * simple because the complexity is hidden away in an unholy tangle
16  * of preprocessor macros.
17  *
18  * The first layer of macros is single.h, double.h, quad.h. Generally
19  * these files define macros for working with floating point numbers
20  * of the three IEEE formats. FP_ADD_D(R,A,B) is for adding doubles,
21  * for instance. These macros are usually defined as calls to more
22  * generic macros (in this case _FP_ADD(D,2,R,X,Y) where the number
23  * of machine words required to store the given IEEE format is passed
24  * as a parameter. [double.h and co check the number of bits in a word
25  * and define FP_ADD_D & co appropriately].
26  * The generic macros are defined in op-common.h. This is where all
27  * the grotty stuff like handling NaNs is coded. To handle the possible
28  * word sizes macros in op-common.h use macros like _FP_FRAC_SLL_##wc()
29  * where wc is the 'number of machine words' parameter (here 2).
30  * These are defined in the third layer of macros: op-1.h, op-2.h
31  * and op-4.h. These handle operations on floating point numbers composed
32  * of 1,2 and 4 machine words respectively. [For example, on sparc64
33  * doubles are one machine word so macros in double.h eventually use
34  * constructs in op-1.h, but on sparc32 they use op-2.h definitions.]
35  * soft-fp.h is on the same level as op-common.h, and defines some
36  * macros which are independent of both word size and FP format.
37  * Finally, sfp-machine.h is the machine dependent part of the
38  * code: it defines the word size and what type a word is. It also
39  * defines how _FP_MUL_MEAT_t() maps to _FP_MUL_MEAT_n_* : op-n.h
40  * provide several possible flavours of multiply algorithm, most
41  * of which require that you supply some form of asm or C primitive to
42  * do the actual multiply. (such asm primitives should be defined
43  * in sfp-machine.h too). udivmodti4.c is the same sort of thing.
44  *
45  * There may be some errors here because I'm working from a
46  * SPARC architecture manual V9, and what I really want is V8...
47  * Also, the insns which can generate exceptions seem to be a
48  * greater subset of the FPops than for V9 (for example, FCMPED
49  * has to be emulated on V8). So I think I'm going to have
50  * to emulate them all just to be on the safe side...
51  *
52  * Emulation routines originate from soft-fp package, which is
53  * part of glibc and has appropriate copyrights in it (allegedly).
54  *
55  * NB: on sparc int == long == 4 bytes, long long == 8 bytes.
56  * Most bits of the kernel seem to go for long rather than int,
57  * so we follow that practice...
58  */
59 
60 /* TODO:
61  * fpsave() saves the FP queue but fpload() doesn't reload it.
62  * Therefore when we context switch or change FPU ownership
63  * we have to check to see if the queue had anything in it and
64  * emulate it if it did. This is going to be a pain.
65  */
66 
67 #include <linux/types.h>
68 #include <linux/sched.h>
69 #include <linux/mm.h>
70 #include <asm/uaccess.h>
71 
72 #include "sfp-util_32.h"
73 #include <math-emu/soft-fp.h>
74 #include <math-emu/single.h>
75 #include <math-emu/double.h>
76 #include <math-emu/quad.h>
77 
78 #define FLOATFUNC(x) extern int x(void *,void *,void *)
79 
80 /* The Vn labels indicate what version of the SPARC architecture gas thinks
81  * each insn is. This is from the binutils source :->
82  */
83 /* quadword instructions */
84 #define FSQRTQ	0x02b		/* v8 */
85 #define FADDQ	0x043		/* v8 */
86 #define FSUBQ	0x047		/* v8 */
87 #define FMULQ	0x04b		/* v8 */
88 #define FDIVQ	0x04f		/* v8 */
89 #define FDMULQ	0x06e		/* v8 */
90 #define FQTOS	0x0c7		/* v8 */
91 #define FQTOD	0x0cb		/* v8 */
92 #define FITOQ	0x0cc		/* v8 */
93 #define FSTOQ	0x0cd		/* v8 */
94 #define FDTOQ	0x0ce		/* v8 */
95 #define FQTOI	0x0d3		/* v8 */
96 #define FCMPQ	0x053		/* v8 */
97 #define FCMPEQ	0x057		/* v8 */
98 /* single/double instructions (subnormal): should all work */
99 #define FSQRTS	0x029		/* v7 */
100 #define FSQRTD	0x02a		/* v7 */
101 #define FADDS	0x041		/* v6 */
102 #define FADDD	0x042		/* v6 */
103 #define FSUBS	0x045		/* v6 */
104 #define FSUBD	0x046		/* v6 */
105 #define FMULS	0x049		/* v6 */
106 #define FMULD	0x04a		/* v6 */
107 #define FDIVS	0x04d		/* v6 */
108 #define FDIVD	0x04e		/* v6 */
109 #define FSMULD	0x069		/* v6 */
110 #define FDTOS	0x0c6		/* v6 */
111 #define FSTOD	0x0c9		/* v6 */
112 #define FSTOI	0x0d1		/* v6 */
113 #define FDTOI	0x0d2		/* v6 */
114 #define FABSS	0x009		/* v6 */
115 #define FCMPS	0x051		/* v6 */
116 #define FCMPES	0x055		/* v6 */
117 #define FCMPD	0x052		/* v6 */
118 #define FCMPED	0x056		/* v6 */
119 #define FMOVS	0x001		/* v6 */
120 #define FNEGS	0x005		/* v6 */
121 #define FITOS	0x0c4		/* v6 */
122 #define FITOD	0x0c8		/* v6 */
123 
124 #define FSR_TEM_SHIFT	23UL
125 #define FSR_TEM_MASK	(0x1fUL << FSR_TEM_SHIFT)
126 #define FSR_AEXC_SHIFT	5UL
127 #define FSR_AEXC_MASK	(0x1fUL << FSR_AEXC_SHIFT)
128 #define FSR_CEXC_SHIFT	0UL
129 #define FSR_CEXC_MASK	(0x1fUL << FSR_CEXC_SHIFT)
130 
131 static int do_one_mathemu(u32 insn, unsigned long *fsr, unsigned long *fregs);
132 
133 /* Unlike the Sparc64 version (which has a struct fpustate), we
134  * pass the taskstruct corresponding to the task which currently owns the
135  * FPU. This is partly because we don't have the fpustate struct and
136  * partly because the task owning the FPU isn't always current (as is
137  * the case for the Sparc64 port). This is probably SMP-related...
138  * This function returns 1 if all queued insns were emulated successfully.
139  * The test for unimplemented FPop in kernel mode has been moved into
140  * kernel/traps.c for simplicity.
141  */
do_mathemu(struct pt_regs * regs,struct task_struct * fpt)142 int do_mathemu(struct pt_regs *regs, struct task_struct *fpt)
143 {
144 	/* regs->pc isn't necessarily the PC at which the offending insn is sitting.
145 	 * The FPU maintains a queue of FPops which cause traps.
146 	 * When it hits an instruction that requires that the trapped op succeeded
147 	 * (usually because it reads a reg. that the trapped op wrote) then it
148 	 * causes this exception. We need to emulate all the insns on the queue
149 	 * and then allow the op to proceed.
150 	 * This code should also handle the case where the trap was precise,
151 	 * in which case the queue length is zero and regs->pc points at the
152 	 * single FPop to be emulated. (this case is untested, though :->)
153 	 * You'll need this case if you want to be able to emulate all FPops
154 	 * because the FPU either doesn't exist or has been software-disabled.
155 	 * [The UltraSPARC makes FP a precise trap; this isn't as stupid as it
156 	 * might sound because the Ultra does funky things with a superscalar
157 	 * architecture.]
158 	 */
159 
160 	/* You wouldn't believe how often I typed 'ftp' when I meant 'fpt' :-> */
161 
162 	int i;
163 	int retcode = 0;                               /* assume all succeed */
164 	unsigned long insn;
165 
166 #ifdef DEBUG_MATHEMU
167 	printk("In do_mathemu()... pc is %08lx\n", regs->pc);
168 	printk("fpqdepth is %ld\n", fpt->thread.fpqdepth);
169 	for (i = 0; i < fpt->thread.fpqdepth; i++)
170 		printk("%d: %08lx at %08lx\n", i, fpt->thread.fpqueue[i].insn,
171 		       (unsigned long)fpt->thread.fpqueue[i].insn_addr);
172 #endif
173 
174 	if (fpt->thread.fpqdepth == 0) {                   /* no queue, guilty insn is at regs->pc */
175 #ifdef DEBUG_MATHEMU
176 		printk("precise trap at %08lx\n", regs->pc);
177 #endif
178 		if (!get_user(insn, (u32 __user *) regs->pc)) {
179 			retcode = do_one_mathemu(insn, &fpt->thread.fsr, fpt->thread.float_regs);
180 			if (retcode) {
181 				/* in this case we need to fix up PC & nPC */
182 				regs->pc = regs->npc;
183 				regs->npc += 4;
184 			}
185 		}
186 		return retcode;
187 	}
188 
189 	/* Normal case: need to empty the queue... */
190 	for (i = 0; i < fpt->thread.fpqdepth; i++) {
191 		retcode = do_one_mathemu(fpt->thread.fpqueue[i].insn, &(fpt->thread.fsr), fpt->thread.float_regs);
192 		if (!retcode)                               /* insn failed, no point doing any more */
193 			break;
194 	}
195 	/* Now empty the queue and clear the queue_not_empty flag */
196 	if (retcode)
197 		fpt->thread.fsr &= ~(0x3000 | FSR_CEXC_MASK);
198 	else
199 		fpt->thread.fsr &= ~0x3000;
200 	fpt->thread.fpqdepth = 0;
201 
202 	return retcode;
203 }
204 
205 /* All routines returning an exception to raise should detect
206  * such exceptions _before_ rounding to be consistent with
207  * the behavior of the hardware in the implemented cases
208  * (and thus with the recommendations in the V9 architecture
209  * manual).
210  *
211  * We return 0 if a SIGFPE should be sent, 1 otherwise.
212  */
record_exception(unsigned long * pfsr,int eflag)213 static inline int record_exception(unsigned long *pfsr, int eflag)
214 {
215 	unsigned long fsr = *pfsr;
216 	int would_trap;
217 
218 	/* Determine if this exception would have generated a trap. */
219 	would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
220 
221 	/* If trapping, we only want to signal one bit. */
222 	if (would_trap != 0) {
223 		eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
224 		if ((eflag & (eflag - 1)) != 0) {
225 			if (eflag & FP_EX_INVALID)
226 				eflag = FP_EX_INVALID;
227 			else if (eflag & FP_EX_OVERFLOW)
228 				eflag = FP_EX_OVERFLOW;
229 			else if (eflag & FP_EX_UNDERFLOW)
230 				eflag = FP_EX_UNDERFLOW;
231 			else if (eflag & FP_EX_DIVZERO)
232 				eflag = FP_EX_DIVZERO;
233 			else if (eflag & FP_EX_INEXACT)
234 				eflag = FP_EX_INEXACT;
235 		}
236 	}
237 
238 	/* Set CEXC, here is the rule:
239 	 *
240 	 *    In general all FPU ops will set one and only one
241 	 *    bit in the CEXC field, this is always the case
242 	 *    when the IEEE exception trap is enabled in TEM.
243 	 */
244 	fsr &= ~(FSR_CEXC_MASK);
245 	fsr |= ((long)eflag << FSR_CEXC_SHIFT);
246 
247 	/* Set the AEXC field, rule is:
248 	 *
249 	 *    If a trap would not be generated, the
250 	 *    CEXC just generated is OR'd into the
251 	 *    existing value of AEXC.
252 	 */
253 	if (would_trap == 0)
254 		fsr |= ((long)eflag << FSR_AEXC_SHIFT);
255 
256 	/* If trapping, indicate fault trap type IEEE. */
257 	if (would_trap != 0)
258 		fsr |= (1UL << 14);
259 
260 	*pfsr = fsr;
261 
262 	return (would_trap ? 0 : 1);
263 }
264 
265 typedef union {
266 	u32 s;
267 	u64 d;
268 	u64 q[2];
269 } *argp;
270 
do_one_mathemu(u32 insn,unsigned long * pfsr,unsigned long * fregs)271 static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs)
272 {
273 	/* Emulate the given insn, updating fsr and fregs appropriately. */
274 	int type = 0;
275 	/* r is rd, b is rs2 and a is rs1. The *u arg tells
276 	   whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
277 	   non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
278 #define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6)
279 	int freg;
280 	argp rs1 = NULL, rs2 = NULL, rd = NULL;
281 	FP_DECL_EX;
282 	FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
283 	FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
284 	FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
285 	int IR;
286 	long fsr;
287 
288 #ifdef DEBUG_MATHEMU
289 	printk("In do_mathemu(), emulating %08lx\n", insn);
290 #endif
291 
292 	if ((insn & 0xc1f80000) == 0x81a00000)	/* FPOP1 */ {
293 		switch ((insn >> 5) & 0x1ff) {
294 		case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
295 		case FADDQ:
296 		case FSUBQ:
297 		case FMULQ:
298 		case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
299 		case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
300 		case FQTOS: TYPE(3,1,1,3,1,0,0); break;
301 		case FQTOD: TYPE(3,2,1,3,1,0,0); break;
302 		case FITOQ: TYPE(3,3,1,1,0,0,0); break;
303 		case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
304 		case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
305 		case FQTOI: TYPE(3,1,0,3,1,0,0); break;
306 		case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
307 		case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
308 		case FADDD:
309 		case FSUBD:
310 		case FMULD:
311 		case FDIVD: TYPE(2,2,1,2,1,2,1); break;
312 		case FADDS:
313 		case FSUBS:
314 		case FMULS:
315 		case FDIVS: TYPE(2,1,1,1,1,1,1); break;
316 		case FSMULD: TYPE(2,2,1,1,1,1,1); break;
317 		case FDTOS: TYPE(2,1,1,2,1,0,0); break;
318 		case FSTOD: TYPE(2,2,1,1,1,0,0); break;
319 		case FSTOI: TYPE(2,1,0,1,1,0,0); break;
320 		case FDTOI: TYPE(2,1,0,2,1,0,0); break;
321 		case FITOS: TYPE(2,1,1,1,0,0,0); break;
322 		case FITOD: TYPE(2,2,1,1,0,0,0); break;
323 		case FMOVS:
324 		case FABSS:
325 		case FNEGS: TYPE(2,1,0,1,0,0,0); break;
326 		}
327 	} else if ((insn & 0xc1f80000) == 0x81a80000)	/* FPOP2 */ {
328 		switch ((insn >> 5) & 0x1ff) {
329 		case FCMPS: TYPE(3,0,0,1,1,1,1); break;
330 		case FCMPES: TYPE(3,0,0,1,1,1,1); break;
331 		case FCMPD: TYPE(3,0,0,2,1,2,1); break;
332 		case FCMPED: TYPE(3,0,0,2,1,2,1); break;
333 		case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
334 		case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
335 		}
336 	}
337 
338 	if (!type) {	/* oops, didn't recognise that FPop */
339 #ifdef DEBUG_MATHEMU
340 		printk("attempt to emulate unrecognised FPop!\n");
341 #endif
342 		return 0;
343 	}
344 
345 	/* Decode the registers to be used */
346 	freg = (*pfsr >> 14) & 0xf;
347 
348 	*pfsr &= ~0x1c000;				/* clear the traptype bits */
349 
350 	freg = ((insn >> 14) & 0x1f);
351 	switch (type & 0x3) {				/* is rs1 single, double or quad? */
352 	case 3:
353 		if (freg & 3) {				/* quadwords must have bits 4&5 of the */
354 							/* encoded reg. number set to zero. */
355 			*pfsr |= (6 << 14);
356 			return 0;			/* simulate invalid_fp_register exception */
357 		}
358 	/* fall through */
359 	case 2:
360 		if (freg & 1) {				/* doublewords must have bit 5 zeroed */
361 			*pfsr |= (6 << 14);
362 			return 0;
363 		}
364 	}
365 	rs1 = (argp)&fregs[freg];
366 	switch (type & 0x7) {
367 	case 7: FP_UNPACK_QP (QA, rs1); break;
368 	case 6: FP_UNPACK_DP (DA, rs1); break;
369 	case 5: FP_UNPACK_SP (SA, rs1); break;
370 	}
371 	freg = (insn & 0x1f);
372 	switch ((type >> 3) & 0x3) {			/* same again for rs2 */
373 	case 3:
374 		if (freg & 3) {				/* quadwords must have bits 4&5 of the */
375 							/* encoded reg. number set to zero. */
376 			*pfsr |= (6 << 14);
377 			return 0;			/* simulate invalid_fp_register exception */
378 		}
379 	/* fall through */
380 	case 2:
381 		if (freg & 1) {				/* doublewords must have bit 5 zeroed */
382 			*pfsr |= (6 << 14);
383 			return 0;
384 		}
385 	}
386 	rs2 = (argp)&fregs[freg];
387 	switch ((type >> 3) & 0x7) {
388 	case 7: FP_UNPACK_QP (QB, rs2); break;
389 	case 6: FP_UNPACK_DP (DB, rs2); break;
390 	case 5: FP_UNPACK_SP (SB, rs2); break;
391 	}
392 	freg = ((insn >> 25) & 0x1f);
393 	switch ((type >> 6) & 0x3) {			/* and finally rd. This one's a bit different */
394 	case 0:						/* dest is fcc. (this must be FCMPQ or FCMPEQ) */
395 		if (freg) {				/* V8 has only one set of condition codes, so */
396 							/* anything but 0 in the rd field is an error */
397 			*pfsr |= (6 << 14);		/* (should probably flag as invalid opcode */
398 			return 0;			/* but SIGFPE will do :-> ) */
399 		}
400 		break;
401 	case 3:
402 		if (freg & 3) {				/* quadwords must have bits 4&5 of the */
403 							/* encoded reg. number set to zero. */
404 			*pfsr |= (6 << 14);
405 			return 0;			/* simulate invalid_fp_register exception */
406 		}
407 	/* fall through */
408 	case 2:
409 		if (freg & 1) {				/* doublewords must have bit 5 zeroed */
410 			*pfsr |= (6 << 14);
411 			return 0;
412 		}
413 	/* fall through */
414 	case 1:
415 		rd = (void *)&fregs[freg];
416 		break;
417 	}
418 #ifdef DEBUG_MATHEMU
419 	printk("executing insn...\n");
420 #endif
421 	/* do the Right Thing */
422 	switch ((insn >> 5) & 0x1ff) {
423 	/* + */
424 	case FADDS: FP_ADD_S (SR, SA, SB); break;
425 	case FADDD: FP_ADD_D (DR, DA, DB); break;
426 	case FADDQ: FP_ADD_Q (QR, QA, QB); break;
427 	/* - */
428 	case FSUBS: FP_SUB_S (SR, SA, SB); break;
429 	case FSUBD: FP_SUB_D (DR, DA, DB); break;
430 	case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
431 	/* * */
432 	case FMULS: FP_MUL_S (SR, SA, SB); break;
433 	case FSMULD: FP_CONV (D, S, 2, 1, DA, SA);
434 		     FP_CONV (D, S, 2, 1, DB, SB);
435 	case FMULD: FP_MUL_D (DR, DA, DB); break;
436 	case FDMULQ: FP_CONV (Q, D, 4, 2, QA, DA);
437 		     FP_CONV (Q, D, 4, 2, QB, DB);
438 	case FMULQ: FP_MUL_Q (QR, QA, QB); break;
439 	/* / */
440 	case FDIVS: FP_DIV_S (SR, SA, SB); break;
441 	case FDIVD: FP_DIV_D (DR, DA, DB); break;
442 	case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
443 	/* sqrt */
444 	case FSQRTS: FP_SQRT_S (SR, SB); break;
445 	case FSQRTD: FP_SQRT_D (DR, DB); break;
446 	case FSQRTQ: FP_SQRT_Q (QR, QB); break;
447 	/* mov */
448 	case FMOVS: rd->s = rs2->s; break;
449 	case FABSS: rd->s = rs2->s & 0x7fffffff; break;
450 	case FNEGS: rd->s = rs2->s ^ 0x80000000; break;
451 	/* float to int */
452 	case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
453 	case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
454 	case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
455 	/* int to float */
456 	case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
457 	case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
458 	case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
459 	/* float to float */
460 	case FSTOD: FP_CONV (D, S, 2, 1, DR, SB); break;
461 	case FSTOQ: FP_CONV (Q, S, 4, 1, QR, SB); break;
462 	case FDTOQ: FP_CONV (Q, D, 4, 2, QR, DB); break;
463 	case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break;
464 	case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break;
465 	case FQTOD: FP_CONV (D, Q, 2, 4, DR, QB); break;
466 	/* comparison */
467 	case FCMPS:
468 	case FCMPES:
469 		FP_CMP_S(IR, SB, SA, 3);
470 		if (IR == 3 &&
471 		    (((insn >> 5) & 0x1ff) == FCMPES ||
472 		     FP_ISSIGNAN_S(SA) ||
473 		     FP_ISSIGNAN_S(SB)))
474 			FP_SET_EXCEPTION (FP_EX_INVALID);
475 		break;
476 	case FCMPD:
477 	case FCMPED:
478 		FP_CMP_D(IR, DB, DA, 3);
479 		if (IR == 3 &&
480 		    (((insn >> 5) & 0x1ff) == FCMPED ||
481 		     FP_ISSIGNAN_D(DA) ||
482 		     FP_ISSIGNAN_D(DB)))
483 			FP_SET_EXCEPTION (FP_EX_INVALID);
484 		break;
485 	case FCMPQ:
486 	case FCMPEQ:
487 		FP_CMP_Q(IR, QB, QA, 3);
488 		if (IR == 3 &&
489 		    (((insn >> 5) & 0x1ff) == FCMPEQ ||
490 		     FP_ISSIGNAN_Q(QA) ||
491 		     FP_ISSIGNAN_Q(QB)))
492 			FP_SET_EXCEPTION (FP_EX_INVALID);
493 	}
494 	if (!FP_INHIBIT_RESULTS) {
495 		switch ((type >> 6) & 0x7) {
496 		case 0: fsr = *pfsr;
497 			if (IR == -1) IR = 2;
498 			/* fcc is always fcc0 */
499 			fsr &= ~0xc00; fsr |= (IR << 10); break;
500 			*pfsr = fsr;
501 			break;
502 		case 1: rd->s = IR; break;
503 		case 5: FP_PACK_SP (rd, SR); break;
504 		case 6: FP_PACK_DP (rd, DR); break;
505 		case 7: FP_PACK_QP (rd, QR); break;
506 		}
507 	}
508 	if (_fex == 0)
509 		return 1;				/* success! */
510 	return record_exception(pfsr, _fex);
511 }
512