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Searched refs:ENDCPLB (Results 1 – 15 of 15) sorted by relevance

/arch/blackfin/mach-bf537/include/mach/
Dmem_map.h73 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
79 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
87 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
109 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
116 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
124 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
145 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
152 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
160 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf533/include/mach/
Dmem_map.h76 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
82 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
90 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
114 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
121 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
129 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
148 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
153 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf518/include/mach/
Dmem_map.h71 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
77 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
85 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf538/include/mach/
Dmem_map.h75 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
81 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
89 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf527/include/mach/
Dmem_map.h71 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
77 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
85 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf548/include/mach/
Dmem_map.h75 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
81 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
89 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-bf561/include/mach/
Dmem_map.h54 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
60 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
68 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
/arch/blackfin/mach-common/
Dpm.c183 ctrl &= ~ENDCPLB; in dcache_disable()
195 ctrl |= ENDCPLB; in dcache_enable()
Dhead.S112 R0 = ~ENDCPLB;
/arch/blackfin/kernel/cplb-mpu/
Dcplbmgr.c49 ctrl &= ~ENDCPLB; in disable_dcplb()
59 ctrl |= ENDCPLB; in enable_dcplb()
/arch/blackfin/kernel/
Dcplbinfo.c82 (cdata->mem_control & ENDCPLB ? "en" : "dis"), in cplbinfo_start()
Dsetup.c1141 if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
/arch/blackfin/mach-bf561/
Dsecondary.S103 R0 = ~ENDCPLB;
/arch/blackfin/kernel/cplb-nompu/
Dcplbmgr.c76 bfin_write_DMEM_CONTROL_SSYNC(ctrl & ~ENDCPLB); in write_dcplb_data()
/arch/blackfin/include/asm/
Ddef_LPBlackfin.h574 #define ENDCPLB 0x00000002 /* Enable DCPLB */ macro