1 /* 2 * file: include/asm-blackfin/mach-bf548/mem_map.h 3 * based on: 4 * author: 5 * 6 * created: 7 * description: 8 * Memory MAP Common header file for blackfin BF537/6/4 of processors. 9 * rev: 10 * 11 * modified: 12 * 13 * bugs: enter bugs at http://blackfin.uclinux.org/ 14 * 15 * this program is free software; you can redistribute it and/or modify 16 * it under the terms of the gnu general public license as published by 17 * the free software foundation; either version 2, or (at your option) 18 * any later version. 19 * 20 * this program is distributed in the hope that it will be useful, 21 * but without any warranty; without even the implied warranty of 22 * merchantability or fitness for a particular purpose. see the 23 * gnu general public license for more details. 24 * 25 * you should have received a copy of the gnu general public license 26 * along with this program; see the file copying. 27 * if not, write to the free software foundation, 28 * 59 temple place - suite 330, boston, ma 02111-1307, usa. 29 */ 30 31 #ifndef _MEM_MAP_548_H_ 32 #define _MEM_MAP_548_H_ 33 34 #define COREMMR_BASE 0xFFE00000 /* Core MMRs */ 35 #define SYSMMR_BASE 0xFFC00000 /* System MMRs */ 36 37 /* Async Memory Banks */ 38 #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ 39 #define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ 40 #define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ 41 #define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ 42 #define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ 43 #define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ 44 #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ 45 #define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ 46 47 /* Boot ROM Memory */ 48 49 #define BOOT_ROM_START 0xEF000000 50 #define BOOT_ROM_LENGTH 0x1000 51 52 /* L1 Instruction ROM */ 53 54 #define L1_ROM_START 0xFFA14000 55 #define L1_ROM_LENGTH 0x10000 56 57 /* Level 1 Memory */ 58 59 /* Memory Map for ADSP-BF548 processors */ 60 #ifdef CONFIG_BFIN_ICACHE 61 #define BFIN_ICACHESIZE (16*1024) 62 #else 63 #define BFIN_ICACHESIZE (0*1024) 64 #endif 65 66 #define L1_CODE_START 0xFFA00000 67 #define L1_DATA_A_START 0xFF800000 68 #define L1_DATA_B_START 0xFF900000 69 70 #define L1_CODE_LENGTH 0xC000 71 72 #ifdef CONFIG_BFIN_DCACHE 73 74 #ifdef CONFIG_BFIN_DCACHE_BANKA 75 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 76 #define L1_DATA_A_LENGTH (0x8000 - 0x4000) 77 #define L1_DATA_B_LENGTH 0x8000 78 #define BFIN_DCACHESIZE (16*1024) 79 #define BFIN_DSUPBANKS 1 80 #else 81 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 82 #define L1_DATA_A_LENGTH (0x8000 - 0x4000) 83 #define L1_DATA_B_LENGTH (0x8000 - 0x4000) 84 #define BFIN_DCACHESIZE (32*1024) 85 #define BFIN_DSUPBANKS 2 86 #endif 87 88 #else 89 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 90 #define L1_DATA_A_LENGTH 0x8000 91 #define L1_DATA_B_LENGTH 0x8000 92 #define BFIN_DCACHESIZE (0*1024) 93 #define BFIN_DSUPBANKS 0 94 #endif /*CONFIG_BFIN_DCACHE*/ 95 96 /* Level 2 Memory */ 97 #define L2_START 0xFEB00000 98 #if defined(CONFIG_BF542) 99 # define L2_LENGTH 0 100 #elif defined(CONFIG_BF544) 101 # define L2_LENGTH 0x10000 102 #else 103 # define L2_LENGTH 0x20000 104 #endif 105 106 /* Scratch Pad Memory */ 107 108 #define L1_SCRATCH_START 0xFFB00000 109 #define L1_SCRATCH_LENGTH 0x1000 110 111 #define GET_PDA_SAFE(preg) \ 112 preg.l = _cpu_pda; \ 113 preg.h = _cpu_pda; 114 115 #define GET_PDA(preg, dreg) GET_PDA_SAFE(preg) 116 117 #endif/* _MEM_MAP_548_H_ */ 118