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/arch/alpha/lib/
Dev67-strncat.S57 bsr $23, __stxncpy # L0 :/* Now do the append. */
64 ret # L0 :
80 ret # L0 :
86 ret # L0 :
92 ret # L0 :
Dev6-copy_user.S130 br $31, $dirtyentry # L0 .. .. .. : L U U L
234 ret $31,($28),1 # L0 .. .. .. : L U L U
256 ret $31,($28),1 # L0
Dev67-strcat.S52 br __stxcpy # L0 :
Dev67-strlen.S47 ret $31, ($26) # L0 :
Dev6-divide.S206 ret $31,($23),1 # L0 : L U U L
243 bsr $23,ufunction # L0: L U L U
258 ret $31,($23),1 # L0 : L U U L
Dev6-memset.S212 ret $31,($26),1 # L0 :
229 ret $31,($26),1 # L0 :
389 ret $31,($26),1 # L0 :
406 ret $31,($26),1 # L0 :
576 ret $31,($26),1 # L0 :
593 ret $31,($26),1 # L0 :
Dev6-memchr.S95 ret # L0 : L U L U
119 ret # L0 : L U L U
189 ret # L0 :
Dev6-memcpy.S86 ldq $6, 0($17) # L0 : bytes 0..7
175 ret $31, ($26), 1 # L0 :
239 ret $31, ($26), 1 # L0 :
Dev6-stxncpy.S132 ret (t9) # L0 : Latency=3
139 br $a_eos # L0 : Latency=3
311 ret (t9) # L0 : Latency=3
332 br $u_final # L0 : Latency=3
392 ret (t9) # L0 : Latency=3
Dev6-stxcpy.S108 ret (t9) # L0 : Latency=3
134 br stxcpy_aligned # L0 : Latency=3
258 ret (t9) # L0 : Latency=3
Dev67-strlen_user.S92 ret # L0 :
Dev67-strchr.S86 ret # L0 :
Dev6-csum_ipv6_magic.S148 ret # L0 : L U L U
/arch/m68knommu/platform/68328/
Dhead-ram.S58 L0: label
60 bne L0
Dhead-pilot.S115 L0: label
117 bne L0
/arch/xtensa/lib/
Dmemset.S55 .L0: # return here from .Ldstunaligned when dst is aligned label
121 bbci.l a5, 1, .L0 # if now aligned, return to main algorithm
128 j .L0 # dst is now aligned, return to main algorithm
/arch/blackfin/kernel/cplb-nompu/
DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/arch/blackfin/kernel/cplb-mpu/
DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/arch/sh/lib/
Dclear_page.S81 .L0: dt r3 define
83 bf/s .L0
/arch/arm/mach-omap2/
Dsram243x.S68 mov r9, #0x0 @ shift back to L0-voltage
73 str r3, [r2] @ go to L0-freq operation
107 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
201 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
Dsram242x.S68 mov r9, #0x0 @ shift back to L0-voltage
73 str r3, [r2] @ go to L0-freq operation
107 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
201 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
/arch/blackfin/mach-bf561/
Dsecondary.S60 L0 = r0; define
/arch/sh/lib64/
Dmemcpy.S57 movi (L1-L0+63*32 + 1) & 0xffff,r1
59 L0: ptrel r0,tr0 label
Dcopy_user_memcpy.S72 movi (L1-L0+63*32 + 1) & 0xffff,r1
74 L0: ptrel r0,tr0 label
/arch/blackfin/mach-common/
Dhead.S64 L0 = r0; define

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