| /arch/arm/mm/ |
| D | proc-xsc3.S | 72 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
120 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
167 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
190 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
191 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
218 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
223 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
238 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
243 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
262 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
[all …]
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| /arch/blackfin/ |
| D | Kconfig | 690 bool "Locate interrupt entry code in L1 Memory"
694 into L1 instruction memory. (less latency)
697 …bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memor…
701 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
705 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
709 into L1 instruction memory. (less latency)
712 bool "Locate frequently called timer_interrupt() function in L1 Memory"
716 into L1 instruction memory. (less latency)
719 bool "Locate frequently idle function in L1 Memory"
723 into L1 instruction memory. (less latency)
[all …]
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| /arch/m68knommu/lib/ |
| D | divsi3.S | 98 jpl L1
105 L1: movel sp@(8), d0 /* d0 = dividend */ label
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| D | udivsi3.S | 149 L1: addl d0,d0 | shift reg pair (p,a) one bit left label
157 jcc L1
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| /arch/alpha/boot/ |
| D | bootp.c | 65 #define L1 ((unsigned long *) 0x200802000) macro
77 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| D | main.c | 60 #define L1 ((unsigned long *) 0x200802000) macro
72 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| D | bootpz.c | 113 #define L1 ((unsigned long *) 0x200802000) macro
125 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| /arch/m68knommu/platform/68328/ |
| D | head-ram.S | 110 L1: label
113 bhi L1
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| D | head-pilot.S | 157 L1: label
160 bhi L1
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| /arch/m68k/fpsp040/ |
| D | setox.S | 104 | 3.1 R := X + N*L1, where L1 := single-precision(-log2/64).
105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
108 | b) N*L1 is exact because N is no longer than 22 bits and
109 | L1 is no longer than 24 bits.
110 | c) The calculation X+N*L1 is also exact due to cancellation.
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
505 fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
507 faddx %fp1,%fp0 | ...X + N*L1
[all …]
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| /arch/blackfin/kernel/cplb-nompu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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| /arch/blackfin/kernel/cplb-mpu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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| /arch/arm/mach-omap2/ |
| D | sram243x.S | 45 str r3, [r2] @ go to L1-freq operation
48 mov r9, #0x1 @ set up for L1 voltage call
107 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
111 str r5, [r4] @ Force transition to L1
201 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
205 str r8, [r10] @ Force transition to L1
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| D | sram242x.S | 45 str r3, [r2] @ go to L1-freq operation
48 mov r9, #0x1 @ set up for L1 voltage call
107 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
111 str r5, [r4] @ Force transition to L1
201 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
205 str r8, [r10] @ Force transition to L1
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| /arch/powerpc/boot/dts/ |
| D | gef_sbc610.dts | 46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
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| D | mpc866ads.dts | 30 d-cache-size = <0x2000>; // L1, 8K
31 i-cache-size = <0x4000>; // L1, 16K
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| D | mpc7448hpc2.dts | 40 d-cache-size = <0x8000>; // L1, 32K bytes
41 i-cache-size = <0x8000>; // L1, 32K bytes
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| D | tqm5200.dts | 30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
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| D | cm5200.dts | 30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
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| D | mpc8572ds_camp_core1.dts | 41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
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| D | ksi8560.dts | 38 d-cache-size = <0x8000>; /* L1, 32K */
39 i-cache-size = <0x8000>; /* L1, 32K */
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| /arch/m68knommu/platform/68360/ |
| D | head-ram.S | 226 L1: label
229 bhi L1
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| D | head-rom.S | 236 L1: label
239 bhi L1
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| /arch/alpha/lib/ |
| D | ev6-memset.S | 159 wh64 ($4) # L1 : memory subsystem write hint
336 wh64 ($4) # L1 : memory subsystem write hint
523 wh64 ($4) # L1 : memory subsystem write hint
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| /arch/blackfin/mach-bf561/ |
| D | secondary.S | 61 L1 = r0; define
|