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Searched refs:MDCNFG (Results 1 – 7 of 7) sorted by relevance

/arch/arm/mach-sa1100/
Dcpu-sa1100.c154 MDCNFG |= MDCNFG_CDB2; in sa1100_update_dram_timings()
162 MDCNFG = settings->mdcnfg; in sa1100_update_dram_timings()
169 MDCNFG |= MDCNFG_CDB2; in sa1100_update_dram_timings()
177 MDCNFG = settings->mdcnfg; in sa1100_update_dram_timings()
Dcpu-sa1110.c160 sd->mdcnfg = MDCNFG & 0x007f007f; in sdram_calculate_timing()
313 : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg), in sa1110_target()
Dsleep.S122 ldr r9, =MDCNFG
150 @ Step 4 clear DE bis in MDCNFG
/arch/arm/mach-pxa/include/mach/
Dpxa2xx-regs.h21 #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ macro
/arch/arm/mach-pxa/
Dcpufreq-pxa2xx.c200 uint32_t mdcnfg = MDCNFG; in init_sdram_rows()
/arch/arm/common/
Dsa1111.c687 FExtr(MDCNFG, MDCNFG_SA1110_DRAC0), in __sa1111_probe()
688 FExtr(MDCNFG, MDCNFG_SA1110_TDL0)); in __sa1111_probe()
/arch/arm/mach-sa1100/include/mach/
DSA-1100.h1401 #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */ macro