| /arch/blackfin/lib/ |
| D | udivsi3.S | 43 CC = R0 < R1 (IU); /* If X < Y, always return 0 */
46 R2 = R1 << 16;
51 R3 = R1 >> 15; /* and Y is a 15-bit number */
70 DIVQ(R0, R1); // 1
71 DIVQ(R0, R1); // 2
72 DIVQ(R0, R1); // 3
73 DIVQ(R0, R1); // 4
74 DIVQ(R0, R1); // 5
75 DIVQ(R0, R1); // 6
76 DIVQ(R0, R1); // 7
[all …]
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| D | smulsi3_highpart.S | 12 R2 = R1.L * R0.L (FU);
13 R3 = R1.H * R0.L (IS,M);
14 R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);
16 R1.L = R2.H + R1.L;
20 R1.L = R1.L + R3.L;
22 R1 >>>= 16;
24 R1 = R1 + R3; define
25 R1 = R1 + R2; define
27 R1 = R1 + R2; define
29 R0 = R0 + R1;
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| D | divsi3.S | 59 R3 = R0 ^ R1;
77 DIVS(R0, R1);
78 DIVQ(R0, R1);
79 DIVQ(R0, R1);
80 DIVQ(R0, R1);
81 DIVQ(R0, R1);
82 DIVQ(R0, R1);
83 DIVQ(R0, R1);
84 DIVQ(R0, R1);
85 DIVQ(R0, R1);
[all …]
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| D | memmove.S | 45 P3 = R1; /* P3 = From Address */
50 CC = R1 < R0 (IU); /* From < To */
52 R3 = R1 + R2;
59 R3 = R1 | R0; /* OR addresses together */
70 R1 = [I0++]; define
75 [P0++] = R1;
77 R1 = [I0++]; define
81 MNOP || [P0++] = R1 || R1 = [I0++];
83 [P0++] = R1;
92 .Lbyte2_s: R1 = B[P3++](Z);
[all …]
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| D | umulsi3_highpart.S | 12 R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
13 R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU);
18 R0 = R0 + R1;
20 R1 = cc; define
21 R1 = PACK(R1.l,R0.h); define
22 R0 = R1 + R2;
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| D | memcmp.S | 47 P3 = R1; /* P3 = s2 Address */
51 I0 = R1; /* s2 */
52 R1 = R1 | R0; /* OR addresses together */ define
53 R1 <<= 30; /* check bottom two bits */
66 R1 = [I0++]; define
68 MNOP || R0 = [P0++] || R1 = [I0++];
70 CC = R0 == R1;
83 R1 = B[P3++](Z); /* *s2 */ define
85 CC = R0 == R1;
91 R0 = R0 - R1;
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| D | memcpy.S | 59 P1 = R1 ; /* src*/
63 CC = R1 < R0; /* src < dst */
65 R3 = R1 + R2;
72 R3 = R1 | R0;
73 R1 = 0x3; define
74 R3 = R3 & R1;
122 R1 = B[P1++] (X); define
124 B[P0++] = R1;
141 R1 = B[P1--] (X); define
143 B[P0--] = R1;
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| D | memset.S | 54 R1 = R1.B (Z); /* R1 = fill char */ define
62 R2 = R1 << 8; /* create quad filler */
63 R2.L = R2.L + R1.L(NS);
64 R2.H = R2.L + R1.H(NS);
88 B[P0++] = R1;
100 B[P0++] = R1;
105 B[P0++] = R1;
106 B[P0++] = R1;
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| D | outs.S | 36 P1 = R1; /* P1 = address */
47 P1 = R1; /* P1 = address */
58 P1 = R1; /* P1 = address */
69 P1 = R1; /* P1 = address */
73 .Lword8_loop_s: R1 = B[P1++];
76 R0 = R0 + R1;
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| D | modsi3.S | 51 CC=R1==0;
53 CC=R0==R1;
55 CC = R1 == 1;
57 CC = R1 == -1;
66 R6 = R1; /* Save for later */
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| D | muldi3.S | 45 A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
50 A0 += R2.l * R1.l (FU); /* E2 */
60 R1 = A0.w; define
65 R1.h = R1.h + R4.l (NS) || R4 = [SP];
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| D | umodsi3.S | 44 CC= R1==0;
46 CC=R0==R1;
48 CC = R1 == 1;
50 CC = R0<R1 (IU);
56 R6 = R1;
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| D | memchr.S | 47 R1 = R1.B(Z); define
56 CC = R3 == R1;
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| D | ins.S | 78 P1 = R1; /* P1 = address */ \
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| /arch/x86/crypto/ |
| D | twofish-x86_64-asm_64.S | 46 #define R1 %rbx macro
222 pushq R1
232 movq (R3), R1
234 input_whitening(R1,%r11,a_offset)
238 shr $32, R1
243 encrypt_round(R0,R1,R2,R3,0);
244 encrypt_round(R2,R3,R0,R1,8);
245 encrypt_round(R0,R1,R2,R3,2*8);
246 encrypt_round(R2,R3,R0,R1,3*8);
247 encrypt_round(R0,R1,R2,R3,4*8);
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| D | twofish-i586-asm_32.S | 247 encrypt_round(R0,R1,R2,R3,0);
248 encrypt_round(R2,R3,R0,R1,8);
249 encrypt_round(R0,R1,R2,R3,2*8);
250 encrypt_round(R2,R3,R0,R1,3*8);
251 encrypt_round(R0,R1,R2,R3,4*8);
252 encrypt_round(R2,R3,R0,R1,5*8);
253 encrypt_round(R0,R1,R2,R3,6*8);
254 encrypt_round(R2,R3,R0,R1,7*8);
255 encrypt_round(R0,R1,R2,R3,8*8);
256 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
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| D | aes-x86_64-asm_64.S | 22 #define R1 %rax macro
136 prologue(FUNC,KEY,B128,B192,R2,R8,R7,R9,R1,R3,R4,R6,R10,R5,R11)
141 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4) \
142 move_regs(R1,R2,R5,R6)
145 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4)
148 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R3,R4) \
149 move_regs(R1,R2,R5,R6)
152 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R3,R4)
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| /arch/blackfin/kernel/ |
| D | fixed_code.S | 36 [P0] = R1;
52 CC = R0 == R1;
68 R1 = [P0]; define
69 R0 = R1 + R0;
83 R1 = [P0]; define
84 R0 = R1 - R0;
98 R1 = [P0]; define
99 R0 = R1 | R0;
113 R1 = [P0]; define
114 R0 = R1 & R0;
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| /arch/blackfin/mach-common/ |
| D | cache.S | 34 R1 += -1;
35 R1 = R1 & R2; define
36 R1 += L1_CACHE_BYTES;
39 R2 = R1 - R0;
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| D | head.S | 48 R1 = R0; define
96 P0 = R1;
97 R0 = R1;
102 R1 = [p0]; define
104 R0 = R0 & R1;
111 R1 = [p0]; define
113 R0 = R0 & R1;
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| D | dpmc_modes.S | 25 R1 = W[P0](z); define
26 BITSET (R1, 3);
27 W[P0] = R1.L;
37 R1 = IWR_DISABLE_ALL; define
62 R1 = IWR_DISABLE_ALL; define
88 P4 = R1;
92 R1 = IWR_DISABLE_ALL; define
121 R1 = 0x6; define
122 R1 <<= 16;
124 R1 = R1|R2; define
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| D | interrupt.S | 170 R1.L = LO(VEC_HWERR);
171 R1.H = HI(VEC_HWERR);
172 R0 = R0 | R1;
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| /arch/blackfin/mach-bf561/ |
| D | secondary.S | 43 R1 = R0; define
84 R1 = [p0]; define
86 R0 = R0 & R1;
102 R1 = [p0]; define
104 R0 = R0 & R1;
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| /arch/blackfin/include/asm/ |
| D | entry.h | 34 R1 = [P0];
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| /arch/parisc/kernel/ |
| D | unaligned.c | 117 #define R1(i) (((i)>>21)&0x1f) macro
451 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; in handle_unaligned()
675 if (modify && R1(regs->iir)) in handle_unaligned()
676 regs->gr[R1(regs->iir)] = newbase; in handle_unaligned()
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