Searched refs:SAR (Results 1 – 10 of 10) sorted by relevance
| /arch/sh/include/cpu-sh2/cpu/ |
| D | dma.h | 15 #define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 }) macro
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| /arch/arm/mach-imx/ |
| D | dma.c | 92 SAR(dma_ch) = nextaddr; in imx_dma_sg_next()
96 dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch)); in imx_dma_sg_next()
167 SAR(dma_ch) = dev_addr; in imx_dma_setup_single()
173 SAR(dma_ch) = (unsigned int)dma_address; in imx_dma_setup_single()
252 SAR(dma_ch) = dev_addr; in imx_dma_setup_sg()
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| /arch/xtensa/include/asm/ |
| D | system.h | 201 "rsr a13," __stringify(SAR) "\n\t" in spill_registers()
207 "wsr a13," __stringify(SAR) "\n\t" in spill_registers()
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| D | regs.h | 33 #define SAR 3 macro
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| /arch/sh/drivers/dma/ |
| D | dma-sh.h | 59 #define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \ macro
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| D | dma-sh.c | 186 ctrl_outl(chan->sar, SAR[chan->chan]); in sh_dmac_xfer_dma()
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| /arch/xtensa/kernel/ |
| D | coprocessor.S | 234 rsr a3, SAR
256 ssl a3 # SAR: 32 - coprocessor_number
324 wsr a0, SAR
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| D | entry.S | 127 rsr a3, SAR
207 rsr a2, SAR # original WINDOWBASE
267 rsr a3, SAR
478 rsr a3, SAR
607 wsr a3, SAR
1131 rsr a0, SAR
1135 s32i a0, a2, PT_AREG5 # store SAR to PT_AREG5
1143 call0 _spill_registers # destroys a3, a4, and SAR
1150 wsr a3, SAR
1251 rsr a3, SAR # WB is still in SAR
[all …]
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| D | align.S | 180 rsr a0, SAR
423 wsr a0, SAR
441 wsr a0, SAR
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| /arch/arm/mach-imx/include/mach/ |
| D | imx-regs.h | 299 #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ macro
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