1 /* 2 * arch/sh/drivers/dma/dma-sh.h 3 * 4 * Copyright (C) 2000 Takashi YOSHII 5 * Copyright (C) 2003 Paul Mundt 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #ifndef __DMA_SH_H 12 #define __DMA_SH_H 13 14 #include <cpu/dma.h> 15 16 /* Definitions for the SuperH DMAC */ 17 #define REQ_L 0x00000000 18 #define REQ_E 0x00080000 19 #define RACK_H 0x00000000 20 #define RACK_L 0x00040000 21 #define ACK_R 0x00000000 22 #define ACK_W 0x00020000 23 #define ACK_H 0x00000000 24 #define ACK_L 0x00010000 25 #define DM_INC 0x00004000 26 #define DM_DEC 0x00008000 27 #define SM_INC 0x00001000 28 #define SM_DEC 0x00002000 29 #define RS_IN 0x00000200 30 #define RS_OUT 0x00000300 31 #define TS_BLK 0x00000040 32 #define TM_BUR 0x00000020 33 #define CHCR_DE 0x00000001 34 #define CHCR_TE 0x00000002 35 #define CHCR_IE 0x00000004 36 37 /* DMAOR definitions */ 38 #define DMAOR_AE 0x00000004 39 #define DMAOR_NMIF 0x00000002 40 #define DMAOR_DME 0x00000001 41 42 /* 43 * Define the default configuration for dual address memory-memory transfer. 44 * The 0x400 value represents auto-request, external->external. 45 */ 46 #define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32) 47 48 #define MAX_DMAC_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) 49 50 /* 51 * Subtypes that have fewer channels than this simply need to change 52 * CONFIG_NR_ONCHIP_DMA_CHANNELS. Likewise, subtypes with a larger number 53 * of channels should expand on this. 54 * 55 * For most subtypes we can easily figure these values out with some 56 * basic calculation, unfortunately on other subtypes these are more 57 * scattered, so we just leave it unrolled for simplicity. 58 */ 59 #define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \ 60 SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30, \ 61 SH_DMAC_BASE + 0x50, SH_DMAC_BASE + 0x60}) 62 #define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \ 63 SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34, \ 64 SH_DMAC_BASE + 0x54, SH_DMAC_BASE + 0x64}) 65 #define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \ 66 SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38, \ 67 SH_DMAC_BASE + 0x58, SH_DMAC_BASE + 0x68}) 68 #define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \ 69 SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c, \ 70 SH_DMAC_BASE + 0x5c, SH_DMAC_BASE + 0x6c}) 71 72 #define DMAOR (SH_DMAC_BASE + 0x40) 73 74 #endif /* __DMA_SH_H */ 75 76