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Searched refs:SDRAM (Results 1 – 25 of 44) sorted by relevance

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/arch/arm/mach-pnx4008/
Dsleep.S48 @ clear SDRAM self-refresh bit latch
50 @ clear SDRAM self-refresh bit
57 @ set SDRAM self-refresh bit
61 @ set SDRAM self-refresh bit latch
65 @ clear SDRAM self-refresh bit latch
69 @ clear SDRAM self-refresh bit
73 @ wait for SDRAM to get into self-refresh mode
78 @ to prepare SDRAM to get out of self-refresh mode after wakeup
98 @ clear STOP mode and SDRAM self-refresh bits
101 @ wait for SDRAM to get out self-refresh mode
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/arch/arm/mach-l7200/include/mach/
Dpmu.h33 unsigned int SDRAM; /* SDRAM configuration bypass register */ member
120 #define GET_SDRREFFQ ((PMU->SDRAM >> 0) & 0x01)
121 #define GET_SDRREFACK ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
122 #define GET_SDRSTOPRQ ((PMU->SDRAM >> 2) & 0x01)
123 #define GET_SDRSTOPACK ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
124 #define GET_PICEN ((PMU->SDRAM >> 4) & 0x01)
125 #define GET_PICTEST ((PMU->SDRAM >> 5) & 0x01)
/arch/arm/mach-s3c2410/
Dsleep.S52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
64 streq r7, [ r4 ] @ SDRAM sleep command
65 streq r8, [ r5 ] @ SDRAM power-down config
/arch/frv/kernel/
Dhead-mmu-fr451.S39 # describe the position and layout of the SDRAM controller registers
43 # GR11 - displacement of 2nd SDRAM addr reg from GR14
44 # GR12 - displacement of 3rd SDRAM addr reg from GR14
45 # GR13 - displacement of 4th SDRAM addr reg from GR14
46 # GR14 - address of 1st SDRAM addr reg
47 # GR15 - amount to shift address by to match SDRAM addr reg
167 # determine the total SDRAM size
170 # GR25 - SDRAM size
182 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
224 # GR25 SDRAM size [saved]
Dhead-uc-fr401.S38 # describe the position and layout of the SDRAM controller registers
42 # GR11 - displacement of 2nd SDRAM addr reg from GR14
43 # GR12 - displacement of 3rd SDRAM addr reg from GR14
44 # GR13 - displacement of 4th SDRAM addr reg from GR14
45 # GR14 - address of 1st SDRAM addr reg
46 # GR15 - amount to shift address by to match SDRAM addr reg
172 # determine the total SDRAM size
175 # GR25 - SDRAM size
187 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
235 # GR25 SDRAM size [saved]
Dhead-uc-fr555.S37 # describe the position and layout of the SDRAM controller registers
41 # GR11 - displacement of 2nd SDRAM addr reg from GR14
42 # GR12 - displacement of 3rd SDRAM addr reg from GR14
43 # GR13 - displacement of 4th SDRAM addr reg from GR14
44 # GR14 - address of 1st SDRAM addr reg
45 # GR15 - amount to shift address by to match SDRAM addr reg
160 # determine the total SDRAM size
163 # GR25 - SDRAM size
175 sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value
219 # GR25 SDRAM size saved
Dcmode.S84 # to access SDRAM and the internal resources.
114 # (6) Execute loading the dummy for SDRAM.
117 # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
154 # (14) Release the self-refresh of SDRAM.
Dhead.inc47 __sdram_base = 0x00000000 /* base address to which SDRAM relocated */
49 __sdram_base = __page_offset /* base address to which SDRAM relocated */
Dsleep.S135 # put SDRAM in self-refresh mode
143 # Execute dummy load from SDRAM
146 # put the SDRAM into self-refresh mode
152 # wait for SDRAM to reach self-refresh mode
189 # wake SDRAM from self-refresh mode
200 # wait for the SDRAM to stabilise
Dhead.S105 # we need to relocate the SDRAM to 0x00000000 (linux) or 0xC0000000 (uClinux)
422 # save the SDRAM details
563 # GR25 SDRAM size [saved]
/arch/arm/mach-lh7a40x/
DKconfig46 the SDRAM controller, organizing memory as a contiguous
54 <file:Documentation/arm/Sharp-LH/SDRAM>.
70 <file:Documentation/arm/Sharp-LH/SDRAM>.
/arch/arm/mach-pxa/
Dsleep.S188 @ prepare SDRAM refresh settings
192 @ enable SDRAM self-refresh mode
239 @ prepare SDRAM refresh settings
243 @ enable SDRAM self-refresh mode
250 @ We keep the change-down close to the actual suspend on SDRAM
303 @ external accesses after SDRAM is put in self-refresh mode
309 @ put SDRAM into self-refresh
/arch/m32r/platforms/mappi2/
Ddot.gdbinit.vdec29 # Initialize SDRAM controller for Mappi
29 Mappi SDRAM controller initialization
33 # Initialize SDRAM controller for Mappi
54 Mappi SDRAM controller initialization
/arch/cris/arch-v10/lib/
Dhw_settings.S35 ; SDRAM or EDO DRAM?
/arch/arm/mach-omap1/
Dsleep.S76 @ prepare to put SDRAM into self-refresh manually
160 @ prepare to put SDRAM into self-refresh manually
229 @ Prepare to put SDRAM into self-refresh manually
/arch/cris/arch-v32/mach-fs/
DKconfig51 SDRAM configuration for group 0. The value depends on the
62 SDRAM configuration for group 1. The defult value is 0
71 SDRAM timing parameters. The default value is ok for
81 SDRAM command. Should be 0 unless you really know what
/arch/cris/arch-v32/mach-a3/
DKconfig27 hex "DDR2 SDRAM timing"
30 SDRAM timing parameters.
/arch/m32r/platforms/m32700ut/
Ddot.gdbinit_400MHz_32MB33 # Initialize SDRAM controller
53 SDRAM controller initialization
164 # SDRAM: 32MB
Ddot.gdbinit_200MHz_16MB33 # Initialize SDRAM controller
53 SDRAM controller initialization
164 # SDRAM: 16MB
Ddot.gdbinit_300MHz_32MB33 # Initialize SDRAM controller
53 SDRAM controller initialization
164 # SDRAM: 32MB
/arch/frv/
DKconfig101 The arch is, however, capable of supporting up to 3GB of SDRAM.
120 will rearrange the SDRAM layout to start at this address, and move
122 sufficiently less than 0xE0000000 that the SDRAM does not intersect
125 The base address must also be aligned such that the SDRAM controller
126 can decode it. For instance, a 512MB SDRAM bank must be 512MB aligned.
/arch/m32r/platforms/oaks32r/
Ddot.gdbinit.nommu30 # Initialize SDRAM controller
44 SDRAM controller initialization
/arch/blackfin/
DKconfig432 bootloader settings. If the clocks are not set, the SDRAM settings
490 This sets the frequency of the system clock (including SDRAM or DDR).
495 prompt "DDR SDRAM Chip Type"
508 prompt "DDR/SDRAM Timing"
512 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
513 The calculated SDRAM timing parameters may not be 100%
913 Cached data will be written back to SDRAM only when needed.
919 Cached data will always be written back to SDRAM when the
930 Cached data will be written back to SDRAM only when needed.
936 Cached data will always be written back to SDRAM when the
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/arch/cris/arch-v32/
DKconfig155 SDRAM configuration for group 0. The value depends on the
166 SDRAM configuration for group 1. The default value is 0
175 SDRAM timing parameters. The default value is ok for
185 SDRAM command. Should be 0 unless you really know what
/arch/arm/mach-at91/
Dpm.c69 #warning Assuming EB1 SDRAM controller is *NOT* used

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