1/* head-uc-fr555.S: FR555 uc-linux specific bits of initialisation 2 * 3 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#include <linux/threads.h> 13#include <linux/linkage.h> 14#include <asm/ptrace.h> 15#include <asm/page.h> 16#include <asm/spr-regs.h> 17#include <asm/mb86943a.h> 18#include "head.inc" 19 20 21#define __551_DARS0 0xfeff0100 22#define __551_DARS1 0xfeff0104 23#define __551_DARS2 0xfeff0108 24#define __551_DARS3 0xfeff010c 25#define __551_DAMK0 0xfeff0110 26#define __551_DAMK1 0xfeff0114 27#define __551_DAMK2 0xfeff0118 28#define __551_DAMK3 0xfeff011c 29#define __551_LCR 0xfeff1100 30#define __551_LSBR 0xfeff1c00 31 32 .section .text.init,"ax" 33 .balign 4 34 35############################################################################### 36# 37# describe the position and layout of the SDRAM controller registers 38# 39# ENTRY: EXIT: 40# GR5 - cacheline size 41# GR11 - displacement of 2nd SDRAM addr reg from GR14 42# GR12 - displacement of 3rd SDRAM addr reg from GR14 43# GR13 - displacement of 4th SDRAM addr reg from GR14 44# GR14 - address of 1st SDRAM addr reg 45# GR15 - amount to shift address by to match SDRAM addr reg 46# GR26 &__head_reference [saved] 47# GR30 LED address [saved] 48# CC0 - T if DARS0 is present 49# CC1 - T if DARS1 is present 50# CC2 - T if DARS2 is present 51# CC3 - T if DARS3 is present 52# 53############################################################################### 54 .globl __head_fr555_describe_sdram 55__head_fr555_describe_sdram: 56 sethi.p %hi(__551_DARS0),gr14 57 setlo %lo(__551_DARS0),gr14 58 setlos.p #__551_DARS1-__551_DARS0,gr11 59 setlos #__551_DARS2-__551_DARS0,gr12 60 setlos.p #__551_DARS3-__551_DARS0,gr13 61 setlos #64,gr5 ; cacheline size 62 setlos #20,gr15 ; amount to shift addr by 63 setlos #0x00ff,gr4 64 movgs gr4,cccr ; extant DARS/DAMK regs 65 bralr 66 67############################################################################### 68# 69# rearrange the bus controller registers 70# 71# ENTRY: EXIT: 72# GR26 &__head_reference [saved] 73# GR30 LED address revised LED address 74# 75############################################################################### 76 .globl __head_fr555_set_busctl 77__head_fr555_set_busctl: 78 LEDS 0x100f 79 sethi.p %hi(__551_LSBR),gr10 80 setlo %lo(__551_LSBR),gr10 81 sethi.p %hi(__551_LCR),gr11 82 setlo %lo(__551_LCR),gr11 83 84 # set the bus controller 85 sethi.p %hi(__region_CS1),gr4 86 setlo %lo(__region_CS1),gr4 87 sethi.p %hi(__region_CS1_M),gr5 88 setlo %lo(__region_CS1_M),gr5 89 sethi.p %hi(__region_CS1_C),gr6 90 setlo %lo(__region_CS1_C),gr6 91 sti gr4,@(gr10,#1*0x08) 92 sti gr5,@(gr10,#1*0x08+0x100) 93 sti gr6,@(gr11,#1*0x08) 94 sethi.p %hi(__region_CS2),gr4 95 setlo %lo(__region_CS2),gr4 96 sethi.p %hi(__region_CS2_M),gr5 97 setlo %lo(__region_CS2_M),gr5 98 sethi.p %hi(__region_CS2_C),gr6 99 setlo %lo(__region_CS2_C),gr6 100 sti gr4,@(gr10,#2*0x08) 101 sti gr5,@(gr10,#2*0x08+0x100) 102 sti gr6,@(gr11,#2*0x08) 103 sethi.p %hi(__region_CS3),gr4 104 setlo %lo(__region_CS3),gr4 105 sethi.p %hi(__region_CS3_M),gr5 106 setlo %lo(__region_CS3_M),gr5 107 sethi.p %hi(__region_CS3_C),gr6 108 setlo %lo(__region_CS3_C),gr6 109 sti gr4,@(gr10,#3*0x08) 110 sti gr5,@(gr10,#3*0x08+0x100) 111 sti gr6,@(gr11,#3*0x08) 112 sethi.p %hi(__region_CS4),gr4 113 setlo %lo(__region_CS4),gr4 114 sethi.p %hi(__region_CS4_M),gr5 115 setlo %lo(__region_CS4_M),gr5 116 sethi.p %hi(__region_CS4_C),gr6 117 setlo %lo(__region_CS4_C),gr6 118 sti gr4,@(gr10,#4*0x08) 119 sti gr5,@(gr10,#4*0x08+0x100) 120 sti gr6,@(gr11,#4*0x08) 121 sethi.p %hi(__region_CS5),gr4 122 setlo %lo(__region_CS5),gr4 123 sethi.p %hi(__region_CS5_M),gr5 124 setlo %lo(__region_CS5_M),gr5 125 sethi.p %hi(__region_CS5_C),gr6 126 setlo %lo(__region_CS5_C),gr6 127 sti gr4,@(gr10,#5*0x08) 128 sti gr5,@(gr10,#5*0x08+0x100) 129 sti gr6,@(gr11,#5*0x08) 130 sethi.p %hi(__region_CS6),gr4 131 setlo %lo(__region_CS6),gr4 132 sethi.p %hi(__region_CS6_M),gr5 133 setlo %lo(__region_CS6_M),gr5 134 sethi.p %hi(__region_CS6_C),gr6 135 setlo %lo(__region_CS6_C),gr6 136 sti gr4,@(gr10,#6*0x08) 137 sti gr5,@(gr10,#6*0x08+0x100) 138 sti gr6,@(gr11,#6*0x08) 139 sethi.p %hi(__region_CS7),gr4 140 setlo %lo(__region_CS7),gr4 141 sethi.p %hi(__region_CS7_M),gr5 142 setlo %lo(__region_CS7_M),gr5 143 sethi.p %hi(__region_CS7_C),gr6 144 setlo %lo(__region_CS7_C),gr6 145 sti gr4,@(gr10,#7*0x08) 146 sti gr5,@(gr10,#7*0x08+0x100) 147 sti gr6,@(gr11,#7*0x08) 148 membar 149 bar 150 151 # adjust LED bank address 152#ifdef CONFIG_MB93091_VDK 153 sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30 154 setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30 155#endif 156 bralr 157 158############################################################################### 159# 160# determine the total SDRAM size 161# 162# ENTRY: EXIT: 163# GR25 - SDRAM size 164# GR26 &__head_reference [saved] 165# GR30 LED address [saved] 166# 167############################################################################### 168 .globl __head_fr555_survey_sdram 169__head_fr555_survey_sdram: 170 sethi.p %hi(__551_DAMK0),gr11 171 setlo %lo(__551_DAMK0),gr11 172 sethi.p %hi(__551_DARS0),gr12 173 setlo %lo(__551_DARS0),gr12 174 175 sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value 176 setlo %lo(0xfff),gr17 177 setlos #0,gr25 178 179 ldi @(gr11,#0x00),gr6 ; DAMK0: bits 11:0 match addr 11:0 180 subcc gr6,gr17,gr0,icc0 181 beq icc0,#0,__head_no_DCS0 182 ldi @(gr12,#0x00),gr4 ; DARS0 183 add gr25,gr6,gr25 184 addi gr25,#1,gr25 185__head_no_DCS0: 186 187 ldi @(gr11,#0x04),gr6 ; DAMK1: bits 11:0 match addr 11:0 188 subcc gr6,gr17,gr0,icc0 189 beq icc0,#0,__head_no_DCS1 190 ldi @(gr12,#0x04),gr4 ; DARS1 191 add gr25,gr6,gr25 192 addi gr25,#1,gr25 193__head_no_DCS1: 194 195 ldi @(gr11,#0x8),gr6 ; DAMK2: bits 11:0 match addr 11:0 196 subcc gr6,gr17,gr0,icc0 197 beq icc0,#0,__head_no_DCS2 198 ldi @(gr12,#0x8),gr4 ; DARS2 199 add gr25,gr6,gr25 200 addi gr25,#1,gr25 201__head_no_DCS2: 202 203 ldi @(gr11,#0xc),gr6 ; DAMK3: bits 11:0 match addr 11:0 204 subcc gr6,gr17,gr0,icc0 205 beq icc0,#0,__head_no_DCS3 206 ldi @(gr12,#0xc),gr4 ; DARS3 207 add gr25,gr6,gr25 208 addi gr25,#1,gr25 209__head_no_DCS3: 210 211 slli gr25,#20,gr25 ; shift [11:0] -> [31:20] 212 bralr 213 214############################################################################### 215# 216# set the protection map with the I/DAMPR registers 217# 218# ENTRY: EXIT: 219# GR25 SDRAM size saved 220# GR30 LED address saved 221# 222############################################################################### 223 .globl __head_fr555_set_protection 224__head_fr555_set_protection: 225 movsg lr,gr27 226 227 sethi.p %hi(0xfff00000),gr11 228 setlo %lo(0xfff00000),gr11 229 230 # set the I/O region protection registers for FR555 231 sethi.p %hi(__region_IO),gr7 232 setlo %lo(__region_IO),gr7 233 ori gr7,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5 234 movgs gr0,iampr15 235 movgs gr0,iamlr15 236 movgs gr5,dampr15 237 movgs gr7,damlr15 238 239 # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible 240 # - start with the highest numbered registers 241 sethi.p %hi(__kernel_image_end),gr8 242 setlo %lo(__kernel_image_end),gr8 243 sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap 244 setlo %lo(32768),gr4 245 add gr8,gr4,gr8 246 sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB 247 setlo %lo(1024*2048-1),gr4 248 add.p gr8,gr4,gr8 249 not gr4,gr4 250 and gr8,gr4,gr8 251 252 sethi.p %hi(__page_offset),gr9 253 setlo %lo(__page_offset),gr9 254 add gr9,gr25,gr9 255 256 # GR8 = base of uncovered RAM 257 # GR9 = top of uncovered RAM 258 # GR11 - mask for DAMLR/IAMLR regs 259 # 260 call __head_split_region 261 movgs gr4,iampr14 262 movgs gr6,iamlr14 263 movgs gr5,dampr14 264 movgs gr7,damlr14 265 call __head_split_region 266 movgs gr4,iampr13 267 movgs gr6,iamlr13 268 movgs gr5,dampr13 269 movgs gr7,damlr13 270 call __head_split_region 271 movgs gr4,iampr12 272 movgs gr6,iamlr12 273 movgs gr5,dampr12 274 movgs gr7,damlr12 275 call __head_split_region 276 movgs gr4,iampr11 277 movgs gr6,iamlr11 278 movgs gr5,dampr11 279 movgs gr7,damlr11 280 call __head_split_region 281 movgs gr4,iampr10 282 movgs gr6,iamlr10 283 movgs gr5,dampr10 284 movgs gr7,damlr10 285 call __head_split_region 286 movgs gr4,iampr9 287 movgs gr6,iamlr9 288 movgs gr5,dampr9 289 movgs gr7,damlr9 290 call __head_split_region 291 movgs gr4,iampr8 292 movgs gr6,iamlr8 293 movgs gr5,dampr8 294 movgs gr7,damlr8 295 296 call __head_split_region 297 movgs gr4,iampr7 298 movgs gr6,iamlr7 299 movgs gr5,dampr7 300 movgs gr7,damlr7 301 call __head_split_region 302 movgs gr4,iampr6 303 movgs gr6,iamlr6 304 movgs gr5,dampr6 305 movgs gr7,damlr6 306 call __head_split_region 307 movgs gr4,iampr5 308 movgs gr6,iamlr5 309 movgs gr5,dampr5 310 movgs gr7,damlr5 311 call __head_split_region 312 movgs gr4,iampr4 313 movgs gr6,iamlr4 314 movgs gr5,dampr4 315 movgs gr7,damlr4 316 call __head_split_region 317 movgs gr4,iampr3 318 movgs gr6,iamlr3 319 movgs gr5,dampr3 320 movgs gr7,damlr3 321 call __head_split_region 322 movgs gr4,iampr2 323 movgs gr6,iamlr2 324 movgs gr5,dampr2 325 movgs gr7,damlr2 326 call __head_split_region 327 movgs gr4,iampr1 328 movgs gr6,iamlr1 329 movgs gr5,dampr1 330 movgs gr7,damlr1 331 332 # cover kernel core image with kernel-only segment 333 sethi.p %hi(__page_offset),gr8 334 setlo %lo(__page_offset),gr8 335 call __head_split_region 336 337#ifdef CONFIG_PROTECT_KERNEL 338 ori.p gr4,#xAMPRx_S_KERNEL,gr4 339 ori gr5,#xAMPRx_S_KERNEL,gr5 340#endif 341 342 movgs gr4,iampr0 343 movgs gr6,iamlr0 344 movgs gr5,dampr0 345 movgs gr7,damlr0 346 jmpl @(gr27,gr0) 347