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Searched refs:SIC_IWR0 (Results 1 – 13 of 13) sorted by relevance

/arch/blackfin/mach-common/
Dclocks-init.c43 #ifdef SIC_IWR0 in init_clocks()
Ddpmc_modes.S252 P0.H = hi(SIC_IWR0);
253 P0.L = lo(SIC_IWR0);
362 #ifdef SIC_IWR0
363 PM_SYS_PUSH(SIC_IWR0)
759 #ifdef SIC_IWR0
760 PM_SYS_POP(SIC_IWR0)
Dpm.c85 #ifdef SIC_IWR0 in bfin_pm_suspend_standby_enter()
Dints-priority.c1119 #ifdef SIC_IWR0
/arch/blackfin/mach-bf561/include/mach/
Dblackfin.h52 #define SIC_IWR0 SICA_IWR0 macro
/arch/blackfin/mach-bf518/include/mach/
DcdefBF51x_base.h83 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
84 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
85 #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
86 #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
1168 iwr0 = bfin_read32(SIC_IWR0); in bfin_write_PLL_CTL()
1171 bfin_write32(SIC_IWR0, IWR_ENABLE(0)); in bfin_write_PLL_CTL()
1178 bfin_write32(SIC_IWR0, iwr0); in bfin_write_PLL_CTL()
1193 iwr0 = bfin_read32(SIC_IWR0); in bfin_write_VR_CTL()
1196 bfin_write32(SIC_IWR0, IWR_ENABLE(0)); in bfin_write_VR_CTL()
1203 bfin_write32(SIC_IWR0, iwr0); in bfin_write_VR_CTL()
DdefBF51x_base.h58 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ macro
/arch/blackfin/mach-bf527/include/mach/
DcdefBF52x_base.h83 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
84 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
85 #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
86 #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
1168 iwr0 = bfin_read32(SIC_IWR0); in bfin_write_PLL_CTL()
1171 bfin_write32(SIC_IWR0, IWR_ENABLE(0)); in bfin_write_PLL_CTL()
1178 bfin_write32(SIC_IWR0, iwr0); in bfin_write_PLL_CTL()
1193 iwr0 = bfin_read32(SIC_IWR0); in bfin_write_VR_CTL()
1196 bfin_write32(SIC_IWR0, IWR_ENABLE(0)); in bfin_write_VR_CTL()
1203 bfin_write32(SIC_IWR0, iwr0); in bfin_write_VR_CTL()
DdefBF52x_base.h61 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ macro
/arch/blackfin/mach-bf538/include/mach/
DcdefBF538.h72 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
73 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
76 #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
77 #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
2068 iwr0 = bfin_read32(SIC_IWR0); in bfin_write_PLL_CTL()
2071 bfin_write32(SIC_IWR0, IWR_ENABLE(0)); in bfin_write_PLL_CTL()
2078 bfin_write32(SIC_IWR0, iwr0); in bfin_write_PLL_CTL()
2093 iwr0 = bfin_read32(SIC_IWR0); in bfin_write_VR_CTL()
2096 bfin_write32(SIC_IWR0, IWR_ENABLE(0)); in bfin_write_VR_CTL()
2103 bfin_write32(SIC_IWR0, iwr0); in bfin_write_VR_CTL()
DdefBF539.h79 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ macro
/arch/blackfin/mach-bf548/include/mach/
DcdefBF54x_base.h85 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
86 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
2707 iwr0 = bfin_read32(SIC_IWR0); in bfin_write_PLL_CTL()
2711 bfin_write32(SIC_IWR0, IWR_ENABLE(0)); in bfin_write_PLL_CTL()
2719 bfin_write32(SIC_IWR0, iwr0); in bfin_write_PLL_CTL()
2735 iwr0 = bfin_read32(SIC_IWR0); in bfin_write_VR_CTL()
2739 bfin_write32(SIC_IWR0, IWR_ENABLE(0)); in bfin_write_VR_CTL()
2747 bfin_write32(SIC_IWR0, iwr0); in bfin_write_VR_CTL()
DdefBF54x_base.h68 #define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */ macro