1 /* 2 * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory 3 * 4 * Copyright 2004-2008 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9 #include <linux/linkage.h> 10 #include <linux/init.h> 11 #include <asm/blackfin.h> 12 13 #include <asm/dma.h> 14 #include <asm/clocks.h> 15 #include <asm/mem_init.h> 16 17 #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ 18 #define PLL_CTL_VAL \ 19 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ 20 (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) 21 22 __attribute__((l1_text)) do_sync(void)23static void do_sync(void) 24 { 25 __builtin_bfin_ssync(); 26 } 27 28 __attribute__((l1_text)) init_clocks(void)29void init_clocks(void) 30 { 31 /* Kill any active DMAs as they may trigger external memory accesses 32 * in the middle of reprogramming things, and that'll screw us up. 33 * For example, any automatic DMAs left by U-Boot for splash screens. 34 */ 35 size_t i; 36 for (i = 0; i < MAX_DMA_CHANNELS; ++i) { 37 struct dma_register *dma = dma_io_base_addr[i]; 38 dma->cfg = 0; 39 } 40 41 do_sync(); 42 43 #ifdef SIC_IWR0 44 bfin_write_SIC_IWR0(IWR_ENABLE(0)); 45 # ifdef SIC_IWR1 46 /* BF52x system reset does not properly reset SIC_IWR1 which 47 * will screw up the bootrom as it relies on MDMA0/1 waking it 48 * up from IDLE instructions. See this report for more info: 49 * http://blackfin.uclinux.org/gf/tracker/4323 50 */ 51 if (ANOMALY_05000435) 52 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); 53 else 54 bfin_write_SIC_IWR1(IWR_DISABLE_ALL); 55 # endif 56 # ifdef SIC_IWR2 57 bfin_write_SIC_IWR2(IWR_DISABLE_ALL); 58 # endif 59 #else 60 bfin_write_SIC_IWR(IWR_ENABLE(0)); 61 #endif 62 do_sync(); 63 #ifdef EBIU_SDGCTL 64 bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); 65 do_sync(); 66 #endif 67 68 #ifdef CLKBUFOE 69 bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE); 70 do_sync(); 71 __asm__ __volatile__("IDLE;"); 72 #endif 73 bfin_write_PLL_LOCKCNT(0x300); 74 do_sync(); 75 bfin_write16(PLL_CTL, PLL_CTL_VAL); 76 __asm__ __volatile__("IDLE;"); 77 bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); 78 #ifdef EBIU_SDGCTL 79 bfin_write_EBIU_SDRRC(mem_SDRRC); 80 bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL); 81 #else 82 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); 83 do_sync(); 84 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1); 85 bfin_write_EBIU_DDRCTL0(mem_DDRCTL0); 86 bfin_write_EBIU_DDRCTL1(mem_DDRCTL1); 87 bfin_write_EBIU_DDRCTL2(mem_DDRCTL2); 88 #ifdef CONFIG_MEM_EBIU_DDRQUE 89 bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE); 90 #endif 91 #endif 92 do_sync(); 93 bfin_read16(0); 94 } 95