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Searched refs:SR (Results 1 – 25 of 25) sorted by relevance

/arch/alpha/math-emu/
Dmath.c101 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in alpha_fp_emul()
135 FP_SUB_S(SR, SA, SB); in alpha_fp_emul()
139 FP_ADD_S(SR, SA, SB); in alpha_fp_emul()
143 FP_MUL_S(SR, SA, SB); in alpha_fp_emul()
147 FP_DIV_S(SR, SA, SB); in alpha_fp_emul()
151 FP_SQRT_S(SR, SB); in alpha_fp_emul()
221 FP_CONV(S,D,1,1,SR,DB); in alpha_fp_emul()
259 FP_FROM_INT_S(SR, ((long)vb), 64, long); in alpha_fp_emul()
271 FP_PACK_SP(&vc, SR); in alpha_fp_emul()
/arch/sparc/math-emu/
Dmath_32.c282 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_one_mathemu()
424 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_one_mathemu()
428 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_one_mathemu()
432 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_one_mathemu()
440 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_one_mathemu()
444 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_one_mathemu()
456 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_one_mathemu()
463 case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break; in do_one_mathemu()
464 case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break; in do_one_mathemu()
503 case 5: FP_PACK_SP (rd, SR); break; in do_one_mathemu()
Dmath_64.c178 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_mathemu()
421 case FADDS: FP_ADD_S (SR, SA, SB); break; in do_mathemu()
425 case FSUBS: FP_SUB_S (SR, SA, SB); break; in do_mathemu()
429 case FMULS: FP_MUL_S (SR, SA, SB); break; in do_mathemu()
437 case FDIVS: FP_DIV_S (SR, SA, SB); break; in do_mathemu()
441 case FSQRTS: FP_SQRT_S (SR, SB); break; in do_mathemu()
459 case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break; in do_mathemu()
462 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_mathemu()
469 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break; in do_mathemu()
470 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break; in do_mathemu()
[all …]
/arch/s390/math-emu/
Dmath.c199 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in emu_aebr()
206 FP_ADD_S(SR, SA, SB); in emu_aebr()
207 FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR); in emu_aebr()
214 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in emu_aeb()
221 FP_ADD_S(SR, SA, SB); in emu_aeb()
222 FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR); in emu_aeb()
445 FP_DECL_S(SR); in emu_cefbr()
452 FP_FROM_INT_S(SR, si, 32, int); in emu_cefbr()
453 FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR); in emu_cefbr()
571 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in emu_debr()
[all …]
/arch/avr32/include/asm/
Dirqflags.h15 return sysreg_read(SR); in __raw_local_save_flags()
30 sysreg_write(SR, flags); in raw_local_irq_restore()
/arch/avr32/mach-at32ap/
Dintc.c81 status_reg = sysreg_read(SR); in do_IRQ()
84 sysreg_write(SR, status_reg); in do_IRQ()
136 sysreg_write(SR, (sysreg_read(SR) in init_IRQ()
/arch/sh/kernel/
Dhead_64.S165 getcon SR, r29
167 putcon r20, SR
256 getcon SR, r21
299 getcon SR, r21
302 putcon r22, SR /* Try to enable */
303 getcon SR, r22
/arch/sh/include/cpu-sh5/cpu/
Dregisters.h25 #define SR cr0
87 #define __SR __str(SR)
/arch/sh/kernel/cpu/sh2a/
Dentry.S49 bld.b #6,@(0,r2) !previus SR.MD
50 bst.b #6,@(4*4,r15) !set cpu mode to SR.MD
53 bset.b #6,@(0,r2) !set SR.MD
66 mov.l r0,@-r15 ! original SR
94 mov.l @r8+,r11 ! old SR
/arch/powerpc/math-emu/
Dmath_efp.c222 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); in do_spe_mathemu()
255 FP_ADD_S(SR, SA, SB); in do_spe_mathemu()
259 FP_SUB_S(SR, SA, SB); in do_spe_mathemu()
263 FP_MUL_S(SR, SA, SB); in do_spe_mathemu()
267 FP_DIV_S(SR, SA, SB); in do_spe_mathemu()
310 FP_CONV(S, D, 1, 2, SR, DB); in do_spe_mathemu()
335 FP_PACK_SP(vc.wp + 1, SR); in do_spe_mathemu()
/arch/m68k/ifpsp060/
DCHANGES79 SR = SR at time of exception
101 SR = SR at time of exception
Diskeleton.S72 btst #0x5,%sp@ | supervisor bit set in saved SR?
107 | * SR * * SR *
147 | * SR * * SR *
/arch/sh/kernel/cpu/sh2/
Dentry.S51 mov.l @(5*4,r15),r3 ! previous SR
55 mov.l r3,@(5*4,r15) ! update SR
71 mov.l r0,@-r15 ! original SR
115 mov.l @r2+,r0 ! old SR
121 mov.l r0,@-r2 ! save old SR
/arch/sh/
DKconfig.cpu97 This will enable the use of SR.RB register bank usage. Processors
102 information on SR.RB and register banking in the kernel in general.
DKconfig.debug137 bool "Debug: set SR.WATCH to enable hardware watchpoints and trace"
/arch/sh/kernel/cpu/sh3/
Dentry.S252 mov.l @r15+, k3 ! original SR
292 ! Calculate new SR value
293 mov k3, k2 ! original SR value
297 and k1, k2 ! Mask orignal SR value
/arch/sh/kernel/cpu/sh5/
Dentry.S82 getcon SR, r6; \
84 putcon r6, SR;
87 getcon SR, r6; \
89 putcon r6, SR;
605 ! construct useful SR for handle_exception
612 ! SSR is now the current SR with the MD and MMU bits set
851 getcon SR, r6
854 putcon r6, SR
857 putcon r6, SR
940 getcon SR, r7
[all …]
/arch/avr32/kernel/
Dkprobes.c73 BUG_ON(!(sysreg_read(SR) & SYSREG_BIT(SR_D))); in prepare_singlestep()
Dsignal.c320 if ((sysreg_read(SR) & MODE_MASK) == MODE_SUPERVISOR) in do_notify_resume()
/arch/mips/include/asm/emma/
Demma2rh.h301 #define SR 0x000000ff macro
/arch/frv/kernel/
Dcmode.S117 # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
/arch/m68k/kernel/
Dentry.S185 bclr #7,%sp@(PT_SR) | clear trace bit in SR
/arch/m68k/ifpsp060/src/
Dpfpsp.S2052 # * SR * * SR *
3001 mov.w 0xc(%sp),0x4(%sp) # move SR
3026 mov.l 0x8(%sp),(%sp) # store SR,hi(PC)
Dfpsp.S2053 # * SR * * SR *
3002 mov.w 0xc(%sp),0x4(%sp) # move SR
3027 mov.l 0x8(%sp),(%sp) # store SR,hi(PC)
4372 mov.l 0x2(%sp),(%sp) # shift SR,hi(PC) "down"
4378 mov.l 0x2(%sp),(%sp) # shift SR,hi(PC) "down"
4397 # ** Next PC ** * SR *
4399 # * SR * (4 words)
4406 mov.w EXC_SR(%a6),2+EXC_PC(%a6) # shift SR "up"
/arch/powerpc/xmon/
Dppc-opc.c481 #define SR SPRG + 1 macro
485 #define STRM SR + 1
3481 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3609 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
4323 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },