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Searched refs:ctr (Results 1 – 25 of 40) sorted by relevance

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/arch/alpha/oprofile/
Dop_model_ev4.c23 struct op_counter_config *ctr, in ev4_reg_setup() argument
41 ctl |= (ctr[0].enabled ? ctr[0].event << 8 : 14 << 8); in ev4_reg_setup()
42 ctl |= (ctr[1].enabled ? (ctr[1].event - 16) << 32 : 7ul << 32); in ev4_reg_setup()
50 count = ctr[0].count; in ev4_reg_setup()
55 ctr[0].count = count; in ev4_reg_setup()
56 ctl |= (ctr[0].enabled && hilo) << 3; in ev4_reg_setup()
58 count = ctr[1].count; in ev4_reg_setup()
63 ctr[1].count = count; in ev4_reg_setup()
64 ctl |= (ctr[1].enabled && hilo); in ev4_reg_setup()
96 struct op_counter_config *ctr) in ev4_handle_interrupt() argument
[all …]
Dop_model_ev6.c23 struct op_counter_config *ctr, in ev6_reg_setup() argument
31 if (ctr[0].enabled && ctr[0].event) in ev6_reg_setup()
32 ctl |= (ctr[0].event & 1) << 4; in ev6_reg_setup()
33 if (ctr[1].enabled) in ev6_reg_setup()
34 ctl |= (ctr[1].event - 2) & 15; in ev6_reg_setup()
49 unsigned long count = ctr[i].count; in ev6_reg_setup()
50 if (!ctr[i].enabled) in ev6_reg_setup()
55 ctr[i].count = count; in ev6_reg_setup()
81 ev6_reset_ctr(struct op_register_config *reg, unsigned long ctr) in ev6_reset_ctr() argument
83 wrperfmon(6, reg->reset_values | (1 << ctr)); in ev6_reset_ctr()
[all …]
Dop_model_ev67.c24 struct op_counter_config *ctr, in ev67_reg_setup() argument
34 if (ctr[1].enabled) { in ev67_reg_setup()
35 ctl |= (ctr[1].event & 3) << 2; in ev67_reg_setup()
37 if (ctr[0].event == 0) /* cycles */ in ev67_reg_setup()
54 unsigned long count = ctr[i].count; in ev67_reg_setup()
55 if (!ctr[i].enabled) in ev67_reg_setup()
60 ctr[i].count = count; in ev67_reg_setup()
86 ev67_reset_ctr(struct op_register_config *reg, unsigned long ctr) in ev67_reset_ctr() argument
88 wrperfmon(6, reg->reset_values | (1 << ctr)); in ev67_reset_ctr()
135 struct op_counter_config *ctr, unsigned long event) in op_add_pm() argument
[all …]
Dop_model_ev5.c28 struct op_counter_config *ctr, in common_reg_setup() argument
49 unsigned long event = ctr[i].event; in common_reg_setup()
50 if (!ctr[i].enabled) in common_reg_setup()
93 unsigned long max, hilo, count = ctr[i].count; in common_reg_setup()
94 if (!ctr[i].enabled) in common_reg_setup()
105 ctr[i].count = count; in common_reg_setup()
119 struct op_counter_config *ctr, in ev5_reg_setup() argument
122 common_reg_setup(reg, ctr, sys, 19, 22); in ev5_reg_setup()
127 struct op_counter_config *ctr, in pca56_reg_setup() argument
130 common_reg_setup(reg, ctr, sys, 8, 11); in pca56_reg_setup()
[all …]
Dcommon.c30 static struct op_counter_config ctr[20]; variable
39 model->handle_interrupt(which, regs, ctr); in op_handle_interrupt()
60 if (ctr[i].enabled) in op_axp_setup()
65 model->reg_setup(&reg, ctr, &sys); in op_axp_setup()
120 oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled); in op_axp_create_files()
121 oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event); in op_axp_create_files()
122 oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count); in op_axp_create_files()
124 oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel); in op_axp_create_files()
125 oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user); in op_axp_create_files()
126 oprofilefs_create_ulong(sb, dir, "unit_mask", &ctr[i].unit_mask); in op_axp_create_files()
/arch/powerpc/oprofile/
Dop_model_fsl_emb.c33 static inline u32 get_pmlca(int ctr) in get_pmlca() argument
37 switch (ctr) { in get_pmlca()
57 static inline void set_pmlca(int ctr, u32 pmlca) in set_pmlca() argument
59 switch (ctr) { in set_pmlca()
114 static void init_pmc_stop(int ctr) in init_pmc_stop() argument
120 switch (ctr) { in init_pmc_stop()
142 static void set_pmc_event(int ctr, int event) in set_pmc_event() argument
146 pmlca = get_pmlca(ctr); in set_pmc_event()
152 set_pmlca(ctr, pmlca); in set_pmc_event()
155 static void set_pmc_user_kernel(int ctr, int user, int kernel) in set_pmc_user_kernel() argument
[all …]
Dop_model_7450.c84 static int fsl7450_cpu_setup(struct op_counter_config *ctr) in fsl7450_cpu_setup() argument
99 static int fsl7450_reg_setup(struct op_counter_config *ctr, in fsl7450_reg_setup() argument
111 reset_value[i] = 0x80000000UL - ctr[i].count; in fsl7450_reg_setup()
114 mmcr0_val = MMCR0_INIT | mmcr0_event1(ctr[0].event) in fsl7450_reg_setup()
115 | mmcr0_event2(ctr[1].event); in fsl7450_reg_setup()
125 mmcr1_val = mmcr1_event3(ctr[2].event) in fsl7450_reg_setup()
126 | mmcr1_event4(ctr[3].event) in fsl7450_reg_setup()
127 | mmcr1_event5(ctr[4].event) in fsl7450_reg_setup()
128 | mmcr1_event6(ctr[5].event); in fsl7450_reg_setup()
136 static int fsl7450_start(struct op_counter_config *ctr) in fsl7450_start() argument
[all …]
Dop_model_cell.c288 static void set_pm_event(u32 ctr, int event, u32 unit_mask) in set_pm_event() argument
297 pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES; in set_pm_event()
298 p = &(pm_signal[ctr]); in set_pm_event()
305 pm_regs.pm07_cntrl[ctr] = 0; in set_pm_event()
315 p = &(pm_signal[ctr]); in set_pm_event()
321 pm_regs.pm07_cntrl[ctr] = 0; in set_pm_event()
322 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles); in set_pm_event()
323 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity); in set_pm_event()
324 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control); in set_pm_event()
349 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit); in set_pm_event()
[all …]
Dcommon.c29 static struct op_counter_config ctr[OP_MAX_COUNTER]; variable
36 model->handle_interrupt(regs, ctr); in op_handle_interrupt()
43 ret = model->cpu_setup(ctr); in op_powerpc_cpu_setup()
61 op_per_cpu_rc = model->reg_setup(ctr, &sys, model->num_counters); in op_powerpc_setup()
91 ret = model->start(ctr); in op_powerpc_cpu_start()
101 return model->global_start(ctr); in op_powerpc_start()
166 oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled); in op_powerpc_create_files()
167 oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event); in op_powerpc_create_files()
168 oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count); in op_powerpc_create_files()
177 oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel); in op_powerpc_create_files()
[all …]
Dop_model_rs64.c91 static int rs64_reg_setup(struct op_counter_config *ctr, in rs64_reg_setup() argument
100 reset_value[i] = 0x80000000UL - ctr[i].count; in rs64_reg_setup()
106 static int rs64_cpu_setup(struct op_counter_config *ctr) in rs64_cpu_setup() argument
133 static int rs64_start(struct op_counter_config *ctr) in rs64_start() argument
142 if (ctr[i].enabled) { in rs64_start()
144 ctrl_write(i, ctr[i].event); in rs64_start()
179 struct op_counter_config *ctr) in rs64_handle_interrupt() argument
195 if (ctr[i].enabled) { in rs64_handle_interrupt()
Dop_model_pa6t.c92 static int pa6t_reg_setup(struct op_counter_config *ctr, in pa6t_reg_setup() argument
106 if (!ctr[pmc].enabled) { in pa6t_reg_setup()
134 reset_value[pmc] = (0x1UL << 39) - ctr[pmc].count; in pa6t_reg_setup()
143 static int pa6t_cpu_setup(struct op_counter_config *ctr) in pa6t_cpu_setup() argument
163 static int pa6t_start(struct op_counter_config *ctr) in pa6t_start() argument
171 if (ctr[i].enabled) in pa6t_start()
201 struct op_counter_config *ctr) in pa6t_handle_interrupt() argument
219 if (oprofile_running && ctr[i].enabled) { in pa6t_handle_interrupt()
Dop_model_power4.c35 static int power4_reg_setup(struct op_counter_config *ctr, in power4_reg_setup() argument
51 reset_value[i] = 0x80000000UL - ctr[i].count; in power4_reg_setup()
89 static int power4_cpu_setup(struct op_counter_config *ctr) in power4_cpu_setup() argument
120 static int power4_start(struct op_counter_config *ctr) in power4_start() argument
129 if (ctr[i].enabled) { in power4_start()
258 struct op_counter_config *ctr) in power4_handle_interrupt() argument
278 if (oprofile_running && ctr[i].enabled) { in power4_handle_interrupt()
/arch/avr32/oprofile/
Dop_model_avr32.c66 struct avr32_perf_counter *ctr = dev_id; in avr32_perf_counter_interrupt() local
81 if (ctr->enabled && (pccr & ctr->flag_mask)) { in avr32_perf_counter_interrupt()
82 sysreg_write(PCCNT, -ctr->count); in avr32_perf_counter_interrupt()
85 ctr++; in avr32_perf_counter_interrupt()
87 if (ctr->enabled && (pccr & ctr->flag_mask)) { in avr32_perf_counter_interrupt()
88 sysreg_write(PCNT0, -ctr->count); in avr32_perf_counter_interrupt()
91 ctr++; in avr32_perf_counter_interrupt()
93 if (ctr->enabled && (pccr & ctr->flag_mask)) { in avr32_perf_counter_interrupt()
94 sysreg_write(PCNT1, -ctr->count); in avr32_perf_counter_interrupt()
133 struct avr32_perf_counter *ctr; in avr32_perf_counter_setup() local
[all …]
/arch/mips/oprofile/
Dcommon.c22 static struct op_counter_config ctr[20]; variable
27 model->reg_setup(ctr); in op_mips_setup()
46 oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled); in op_mips_create_files()
47 oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event); in op_mips_create_files()
48 oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count); in op_mips_create_files()
49 oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel); in op_mips_create_files()
50 oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user); in op_mips_create_files()
51 oprofilefs_create_ulong(sb, dir, "exl", &ctr[i].exl); in op_mips_create_files()
53 oprofilefs_create_ulong(sb, dir, "unit_mask", &ctr[i].unit_mask); in op_mips_create_files()
Dop_model_rm9000.c39 static void rm9000_reg_setup(struct op_counter_config *ctr) in rm9000_reg_setup() argument
45 if (ctr[0].enabled) in rm9000_reg_setup()
46 control |= RM9K_COUNTER1_EVENT(ctr[0].event) | in rm9000_reg_setup()
50 if (ctr[1].enabled) in rm9000_reg_setup()
51 control |= RM9K_COUNTER2_EVENT(ctr[1].event) | in rm9000_reg_setup()
57 reg.reset_counter1 = 0x80000000 - ctr[0].count; in rm9000_reg_setup()
58 reg.reset_counter2 = 0x80000000 - ctr[1].count; in rm9000_reg_setup()
Dop_model_mipsxx.c134 static void mipsxx_reg_setup(struct op_counter_config *ctr) in mipsxx_reg_setup() argument
144 if (!ctr[i].enabled) in mipsxx_reg_setup()
147 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | in mipsxx_reg_setup()
149 if (ctr[i].kernel) in mipsxx_reg_setup()
151 if (ctr[i].user) in mipsxx_reg_setup()
153 if (ctr[i].exl) in mipsxx_reg_setup()
155 reg.counter[i] = 0x80000000 - ctr[i].count; in mipsxx_reg_setup()
/arch/powerpc/include/asm/
Dcell-pmu.h35 #define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1)))) argument
65 #define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7))) argument
81 extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
82 extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
84 extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
85 extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
/arch/sh/oprofile/
Dcommon.c28 static struct op_counter_config ctr[20]; variable
35 model->reg_setup(ctr); in op_sh_setup()
54 ret |= oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled); in op_sh_create_files()
55 ret |= oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event); in op_sh_create_files()
56 ret |= oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel); in op_sh_create_files()
57 ret |= oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user); in op_sh_create_files()
62 ret |= oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count); in op_sh_create_files()
65 ret |= oprofilefs_create_ulong(sb, dir, "unit_mask", &ctr[i].unit_mask); in op_sh_create_files()
Dop_model_sh7750.c171 static void sh7750_ppc_reg_setup(struct op_counter_config *ctr) in sh7750_ppc_reg_setup() argument
181 if (!ctr[i].enabled) in sh7750_ppc_reg_setup()
184 regcache[i].ctrl |= ctr[i].event | PMCR_PMEN | PMCR_PMST; in sh7750_ppc_reg_setup()
185 regcache[i].cnt_hi = (unsigned long)((ctr->count >> 32) & 0xffff); in sh7750_ppc_reg_setup()
186 regcache[i].cnt_lo = (unsigned long)(ctr->count & 0xffffffff); in sh7750_ppc_reg_setup()
/arch/powerpc/platforms/cell/
Dpmu.c125 u32 cbe_read_ctr(u32 cpu, u32 ctr) in cbe_read_ctr() argument
128 u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1); in cbe_read_ctr()
133 val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff); in cbe_read_ctr()
139 void cbe_write_ctr(u32 cpu, u32 ctr, u32 val) in cbe_write_ctr() argument
144 phys_ctr = ctr & (NR_PHYS_CTRS - 1); in cbe_write_ctr()
149 if (ctr < NR_PHYS_CTRS) in cbe_write_ctr()
164 u32 cbe_read_pm07_control(u32 cpu, u32 ctr) in cbe_read_pm07_control() argument
168 if (ctr < NR_CTRS) in cbe_read_pm07_control()
169 READ_SHADOW_REG(pm07_control, pm07_control[ctr]); in cbe_read_pm07_control()
175 void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val) in cbe_write_pm07_control() argument
[all …]
/arch/x86/oprofile/
Dop_model_p4.c373 #define CTR_OVERFLOW_P(ctr) (!((ctr) & 0x80000000)) argument
488 static void pmc_setup_one_p4_counter(unsigned int ctr) in pmc_setup_one_p4_counter() argument
502 counter_bit = 1 << VIRT_CTR(stag, ctr); in pmc_setup_one_p4_counter()
505 if (counter_config[ctr].event <= 0 || counter_config[ctr].event > NUM_EVENTS) { in pmc_setup_one_p4_counter()
508 counter_config[ctr].event); in pmc_setup_one_p4_counter()
512 ev = &(p4_events[counter_config[ctr].event - 1]); in pmc_setup_one_p4_counter()
521 ESCR_SET_USR_0(escr, counter_config[ctr].user); in pmc_setup_one_p4_counter()
522 ESCR_SET_OS_0(escr, counter_config[ctr].kernel); in pmc_setup_one_p4_counter()
524 ESCR_SET_USR_1(escr, counter_config[ctr].user); in pmc_setup_one_p4_counter()
525 ESCR_SET_OS_1(escr, counter_config[ctr].kernel); in pmc_setup_one_p4_counter()
[all …]
/arch/x86/boot/
Da20.c51 int saved, ctr; in a20_test() local
56 saved = ctr = rdfs32(A20_TEST_ADDR); in a20_test()
59 wrfs32(++ctr, A20_TEST_ADDR); in a20_test()
61 ok = rdgs32(A20_TEST_ADDR+0x10) ^ ctr; in a20_test()
/arch/sparc/kernel/
Dwindows.c19 register int ctr asm("g5"); in flush_user_windows()
21 ctr = 0; in flush_user_windows()
33 : "=&r" (ctr) in flush_user_windows()
34 : "0" (ctr), in flush_user_windows()
/arch/mn10300/kernel/
Dmn10300-watchdog.c84 u8 ctr; in setup_watchdog() local
93 ctr = WDCTR_WDCK_65536th; in setup_watchdog()
94 WDCTR = WDCTR_WDRST | ctr; in setup_watchdog()
95 WDCTR = ctr; in setup_watchdog()
98 tmp = __muldiv64u(1 << (16 + ctr * 2), 1000000, MN10300_WDCLK); in setup_watchdog()
/arch/powerpc/lib/
Dsstep.c36 --regs->ctr; in branch_taken()
37 if (((bo >> 1) & 1) ^ (regs->ctr == 0)) in branch_taken()
108 imm = (instr & 0x400)? regs->ctr: regs->link; in emulate_step()
170 regs->gpr[rd] = regs->ctr; in emulate_step()
195 regs->ctr = regs->gpr[rd]; in emulate_step()

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