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Searched refs:icache (Results 1 – 25 of 28) sorted by relevance

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/arch/sh/kernel/cpu/sh5/
Dprobe.c40 boot_cpu_data.icache.ways = 4; in detect_cpu_and_cache_system()
41 boot_cpu_data.icache.sets = 256; in detect_cpu_and_cache_system()
42 boot_cpu_data.icache.linesz = L1_CACHE_BYTES; in detect_cpu_and_cache_system()
43 boot_cpu_data.icache.way_incr = (1 << 13); in detect_cpu_and_cache_system()
44 boot_cpu_data.icache.entry_shift = 5; in detect_cpu_and_cache_system()
45 boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets * in detect_cpu_and_cache_system()
46 boot_cpu_data.icache.linesz; in detect_cpu_and_cache_system()
47 boot_cpu_data.icache.entry_mask = 0x1fe0; in detect_cpu_and_cache_system()
48 boot_cpu_data.icache.flags = 0; in detect_cpu_and_cache_system()
60 boot_cpu_data.dcache = boot_cpu_data.icache; in detect_cpu_and_cache_system()
/arch/mips/mm/
Dc-octeon.c186 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
187 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
188 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_octeon()
189 c->icache.flags |= MIPS_CACHE_VTAG; in probe_octeon()
191 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
192 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; in probe_octeon()
211 c->icache.waysize = icache_size / c->icache.ways; in probe_octeon()
214 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); in probe_octeon()
223 c->icache.ways, c->icache.sets, c->icache.linesz); in probe_octeon()
Dc-r4k.c165 unsigned long end = start + current_cpu_data.icache.waysize; in tx49_blast_icache32()
166 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; in tx49_blast_icache32()
167 unsigned long ws_end = current_cpu_data.icache.ways << in tx49_blast_icache32()
168 current_cpu_data.icache.waybit; in tx49_blast_icache32()
194 unsigned long indexmask = current_cpu_data.icache.waysize - 1; in tx49_blast_icache32_page_indexed()
197 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; in tx49_blast_icache32_page_indexed()
198 unsigned long ws_end = current_cpu_data.icache.ways << in tx49_blast_icache32_page_indexed()
199 current_cpu_data.icache.waybit; in tx49_blast_icache32_page_indexed()
759 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
760 c->icache.ways = 2; in probe_pcache()
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Dc-tx39.c291 unsigned long ic_lsize = current_cpu_data.icache.linesz; in tx39_flush_cache_sigtramp()
319 current_cpu_data.icache.linesz = 16; in tx39_probe_cache()
322 current_cpu_data.icache.ways = 1; in tx39_probe_cache()
328 current_cpu_data.icache.ways = 2; in tx39_probe_cache()
335 current_cpu_data.icache.ways = 1; in tx39_probe_cache()
411 current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways; in tx39_cache_init()
414 current_cpu_data.icache.sets = in tx39_cache_init()
415 current_cpu_data.icache.waysize / current_cpu_data.icache.linesz; in tx39_cache_init()
422 current_cpu_data.icache.waybit = 0; in tx39_cache_init()
426 icache_size >> 10, current_cpu_data.icache.linesz); in tx39_cache_init()
/arch/sh/kernel/cpu/sh4/
Dprobe.c38 boot_cpu_data.icache.way_incr = (1 << 13); in detect_cpu_and_cache_system()
39 boot_cpu_data.icache.entry_shift = 5; in detect_cpu_and_cache_system()
40 boot_cpu_data.icache.sets = 256; in detect_cpu_and_cache_system()
41 boot_cpu_data.icache.ways = 1; in detect_cpu_and_cache_system()
42 boot_cpu_data.icache.linesz = L1_CACHE_BYTES; in detect_cpu_and_cache_system()
96 boot_cpu_data.icache.ways = 4; in detect_cpu_and_cache_system()
110 boot_cpu_data.icache.ways = 4; in detect_cpu_and_cache_system()
120 boot_cpu_data.icache.ways = 4; in detect_cpu_and_cache_system()
127 boot_cpu_data.icache.ways = 4; in detect_cpu_and_cache_system()
133 boot_cpu_data.icache.ways = 4; in detect_cpu_and_cache_system()
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/arch/sh/kernel/cpu/
Dinit.c169 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); in detect_cache_shape()
247 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - in sh_cpu_init()
248 current_cpu_data.icache.linesz; in sh_cpu_init()
250 current_cpu_data.icache.way_size = current_cpu_data.icache.sets * in sh_cpu_init()
251 current_cpu_data.icache.linesz; in sh_cpu_init()
/arch/sh/mm/
Dcache-sh4.c59 boot_cpu_data.icache.ways, in emit_cache_params()
60 boot_cpu_data.icache.sets, in emit_cache_params()
61 boot_cpu_data.icache.way_incr); in emit_cache_params()
63 boot_cpu_data.icache.entry_mask, in emit_cache_params()
64 boot_cpu_data.icache.alias_mask, in emit_cache_params()
65 boot_cpu_data.icache.n_aliases); in emit_cache_params()
98 compute_alias(&boot_cpu_data.icache); in p3_cache_init()
211 v & cpu_data->icache.entry_mask); in flush_icache_range()
213 for (i = 0; i < cpu_data->icache.ways; in flush_icache_range()
214 i++, icacheaddr += cpu_data->icache.way_incr) in flush_icache_range()
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Dcache-debugfs.c53 cache = &current_cpu_data.icache; in cache_seq_show()
/arch/avr32/kernel/
Dcpu.c279 boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1); in setup_processor()
280 boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1); in setup_processor()
281 boot_cpu_data.icache.linesz = 1 << (tmp + 1); in setup_processor()
337 icache_size = boot_cpu_data.icache.ways * in c_show()
338 boot_cpu_data.icache.sets * in c_show()
339 boot_cpu_data.icache.linesz; in c_show()
363 boot_cpu_data.icache.ways, in c_show()
364 boot_cpu_data.icache.sets, in c_show()
365 boot_cpu_data.icache.linesz); in c_show()
/arch/mips/include/asm/
Dcpu-features.h96 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
102 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
121 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
218 #define cpu_icache_line_size() cpu_data[0].icache.linesz
Dr4kcache.h397 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
400 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
402 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
436 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
Dcpu-info.h55 struct cache_desc icache; /* Primary I-cache */ member
/arch/frv/lib/
Dcache.S40 # Invalidate a range of dcache and icache
61 # Invalidate a range of icache
81 # Write back and invalidate a range of dcache and icache
/arch/sh/kernel/cpu/sh2/
Dprobe.c31 boot_cpu_data.icache = boot_cpu_data.dcache; in detect_cpu_and_cache_system()
/arch/frv/kernel/
Dsleep.S84 # preload and lock into icache that code which may have to run
126 # - we want it to be be cacheline aligned so we can lock it into the icache easily
206 # locked in icache.
277 # unlock the icache which was locked before going to sleep
302 # Preload into icache.
363 # Unlock from icache
/arch/sh/kernel/cpu/sh2a/
Dprobe.c51 boot_cpu_data.icache = boot_cpu_data.dcache; in detect_cpu_and_cache_system()
/arch/sh/include/asm/
Dprocessor.h69 struct cache_info icache; /* Primary I-cache */ member
/arch/powerpc/kernel/
Dcacheinfo.c339 struct cache *dcache, *icache; in cache_do_one_devnode_split() local
345 icache = new_cache(CACHE_TYPE_INSTRUCTION, level, node); in cache_do_one_devnode_split()
347 if (!dcache || !icache) in cache_do_one_devnode_split()
350 dcache->next_local = icache; in cache_do_one_devnode_split()
355 release_cache(icache); in cache_do_one_devnode_split()
/arch/sh/kernel/
Dsetup.c516 if (c->icache.flags & SH_CACHE_COMBINED) { in show_cpuinfo()
518 show_cacheinfo(m, "cache", c->icache); in show_cpuinfo()
521 show_cacheinfo(m, "icache", c->icache); in show_cpuinfo()
/arch/sh/kernel/cpu/sh3/
Dprobe.c108 boot_cpu_data.icache = boot_cpu_data.dcache; in detect_cpu_and_cache_system()
/arch/avr32/include/asm/
Dprocessor.h67 struct cache_info icache; member
/arch/mn10300/mm/
Dcache-mn10300.S35 # Invalidate the entire icache
51 # disable the icache
/arch/avr32/mm/
Dcache.c82 linesz = boot_cpu_data.icache.linesz; in invalidate_icache_region()
/arch/mips/include/asm/octeon/
Dcvmx-mio-defs.h791 uint64_t icache:24; member
802 uint64_t icache:24; member
813 uint64_t icache:24; member
822 uint64_t icache:24; member
/arch/arm/mach-omap2/
Dsram243x.S239 mcrr p15, 1, r8, r4, c12 @ preload into icache

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