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Searched refs:k0 (Results 1 – 13 of 13) sorted by relevance

/arch/mips/mm/
Dcex-sb1.S64 sd k0,0x170($0)
77 sll k0,k1,1
97 bltz k0,unrecoverable
98 sll k0,1
105 bgez k0,unrecoverable
113 mfc0 k0,C0_CERR_I /* delay slot */
115 and k1,k0
117 andi k0,0x1fe0
124 cache Index_Invalidate_I,(0<<13)(k0)
125 cache Index_Invalidate_I,(1<<13)(k0)
[all …]
Dcex-gen.S30 mfc0 k0,CP0_CONFIG
32 and k0,k0,k1
33 ori k0,k0,CONF_CM_UNCACHED
34 mtc0 k0,CP0_CONFIG
Dcex-oct.S30 rdhwr k0, $0 /* get core_id */
32 sll k0, k0, 3
33 PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */
35 dmfc0 k0, CP0_CACHEERR, 1
36 sd k0, (k1)
/arch/mips/kernel/
Dgenex.S56 mfc0 k0, CP0_INDEX
63 PTR_L k0, exception_handlers(k1)
64 jr k0
79 li k0, 31<<2
84 beq k1, k0, handle_vced
85 li k0, 14<<2
86 beq k1, k0, handle_vcei
91 PTR_L k0, exception_handlers(k1)
92 jr k0
101 MFC0 k0, CP0_BADVADDR
[all …]
Dsmtc-asm.S57 mfc0 k0,CP0_STATUS
58 ori k0,k0,ST0_EXL
59 mtc0 k0,CP0_STATUS
74 sll k1,k0,3
83 or k1,k1,k0
90 lw k0,PT_TCSTATUS(k1)
92 mtc0 k0,$2,1
94 lw k0,PT_EPC(k1)
95 mtc0 k0,CP0_EPC
Docteon_switch.S446 dmfc0 k0, $9,7 /* CvmCtl register. */
447 bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */
451 v3mulu k0, $0, $0
453 sd k0, PT_MTP(sp) /* PT_MTP has P0 */
454 v3mulu k0, $0, $0
458 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
459 v3mulu k0, $0, $0
462 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
484 ld k0, PT_MPL+16(sp) /* MPL2 */
495 MTM2 k0 /* MPL2 */
/arch/mips/alchemy/common/
Dsleeper.S50 mfc0 k0, CP0_STATUS
51 sw k0, 0x20(sp)
52 mfc0 k0, CP0_CONTEXT
53 sw k0, 0x1c(sp)
54 mfc0 k0, CP0_PAGEMASK
55 sw k0, 0x18(sp)
56 mfc0 k0, CP0_CONFIG
57 sw k0, 0x14(sp)
72 la k0, 3f /* resume path */
73 sw k0, 0x001c(t3)
[all …]
/arch/sh/kernel/cpu/sh3/
Dentry.S74 #define k0 r0 macro
209 mov.l @r15+, k0
216 mov k0, r15
218 mov.l 2f, k0
219 mov.l @k0, k0
220 jmp @k0
259 mov.l @r15+, k0 ! DSP mode marker
261 cmp/eq k0, k1 ! Do we have a DSP stack frame?
264 stc sr, k0 ! Enable CPU DSP mode
265 or k1, k0 ! (within kernel it may be disabled)
[all …]
/arch/mips/dec/prom/
Dlocore.S19 mfc0 k0, CP0_STATUS
22 sw k0, 0(k1)
24 mfc0 k0, CP0_EPC
26 addiu k0, 4 # skip the causing instruction
27 jr k0
/arch/sh/boards/mach-hp6xx/
Dpm_wakeup.S13 #define k0 r0 macro
34 and #127, k0
35 mov.b k0, @k2
38 mov.w 6f, k0
39 mov.w k0, @k1
/arch/mips/include/asm/
Dstackframe.h91 mfc0 k0, CP0_TCBIND
93 MFC0 k0, CP0_CONTEXT
104 LONG_SRL k0, PTEBASE_SHIFT
105 LONG_ADDU k1, k0
141 mfc0 k0, CP0_STATUS
142 sll k0, 3 /* extract cu0 bit */
144 bltz k0, 8f
150 8: move k0, sp
153 .set at=k0
156 move k0, sp
[all …]
Dregdef.h47 #define k0 $26 /* kernel scratch */ macro
90 #define k0 $26 /* kernel temporary */ macro
/arch/ia64/kvm/
Dtrampoline.S117 mov r16 = ar.k0; \
154 mov ar.k0=r16; \