1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle 7 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 2000 MIPS Technologies, Inc. 11 * written by Carsten Langgaard, carstenl@mips.com 12 */ 13#include <asm/asm.h> 14#include <asm/cachectl.h> 15#include <asm/fpregdef.h> 16#include <asm/mipsregs.h> 17#include <asm/asm-offsets.h> 18#include <asm/page.h> 19#include <asm/pgtable-bits.h> 20#include <asm/regdef.h> 21#include <asm/stackframe.h> 22#include <asm/thread_info.h> 23 24#include <asm/asmmacro.h> 25 26/* 27 * Offset to the current process status flags, the first 32 bytes of the 28 * stack are not used. 29 */ 30#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) 31 32/* 33 * task_struct *resume(task_struct *prev, task_struct *next, 34 * struct thread_info *next_ti) 35 */ 36 .align 7 37 LEAF(resume) 38 .set arch=octeon 39#ifndef CONFIG_CPU_HAS_LLSC 40 sw zero, ll_bit 41#endif 42 mfc0 t1, CP0_STATUS 43 LONG_S t1, THREAD_STATUS(a0) 44 cpu_save_nonscratch a0 45 LONG_S ra, THREAD_REG31(a0) 46 47 /* check if we need to save COP2 registers */ 48 PTR_L t2, TASK_THREAD_INFO(a0) 49 LONG_L t0, ST_OFF(t2) 50 bbit0 t0, 30, 1f 51 52 /* Disable COP2 in the stored process state */ 53 li t1, ST0_CU2 54 xor t0, t1 55 LONG_S t0, ST_OFF(t2) 56 57 /* Enable COP2 so we can save it */ 58 mfc0 t0, CP0_STATUS 59 or t0, t1 60 mtc0 t0, CP0_STATUS 61 62 /* Save COP2 */ 63 daddu a0, THREAD_CP2 64 jal octeon_cop2_save 65 dsubu a0, THREAD_CP2 66 67 /* Disable COP2 now that we are done */ 68 mfc0 t0, CP0_STATUS 69 li t1, ST0_CU2 70 xor t0, t1 71 mtc0 t0, CP0_STATUS 72 731: 74#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 75 /* Check if we need to store CVMSEG state */ 76 mfc0 t0, $11,7 /* CvmMemCtl */ 77 bbit0 t0, 6, 3f /* Is user access enabled? */ 78 79 /* Store the CVMSEG state */ 80 /* Extract the size of CVMSEG */ 81 andi t0, 0x3f 82 /* Multiply * (cache line size/sizeof(long)/2) */ 83 sll t0, 7-LONGLOG-1 84 li t1, -32768 /* Base address of CVMSEG */ 85 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */ 86 synciobdma 872: 88 .set noreorder 89 LONG_L t8, 0(t1) /* Load from CVMSEG */ 90 subu t0, 1 /* Decrement loop var */ 91 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */ 92 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */ 93 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */ 94 LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */ 95 bnez t0, 2b /* Loop until we've copied it all */ 96 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */ 97 .set reorder 98 99 /* Disable access to CVMSEG */ 100 mfc0 t0, $11,7 /* CvmMemCtl */ 101 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */ 102 mtc0 t0, $11,7 /* CvmMemCtl */ 103#endif 1043: 105 /* 106 * The order of restoring the registers takes care of the race 107 * updating $28, $29 and kernelsp without disabling ints. 108 */ 109 move $28, a2 110 cpu_restore_nonscratch a1 111 112#if (_THREAD_SIZE - 32) < 0x8000 113 PTR_ADDIU t0, $28, _THREAD_SIZE - 32 114#else 115 PTR_LI t0, _THREAD_SIZE - 32 116 PTR_ADDU t0, $28 117#endif 118 set_saved_sp t0, t1, t2 119 120 mfc0 t1, CP0_STATUS /* Do we really need this? */ 121 li a3, 0xff01 122 and t1, a3 123 LONG_L a2, THREAD_STATUS(a1) 124 nor a3, $0, a3 125 and a2, a3 126 or a2, t1 127 mtc0 a2, CP0_STATUS 128 move v0, a0 129 jr ra 130 END(resume) 131 132/* 133 * void octeon_cop2_save(struct octeon_cop2_state *a0) 134 */ 135 .align 7 136 LEAF(octeon_cop2_save) 137 138 dmfc0 t9, $9,7 /* CvmCtl register. */ 139 140 /* Save the COP2 CRC state */ 141 dmfc2 t0, 0x0201 142 dmfc2 t1, 0x0202 143 dmfc2 t2, 0x0200 144 sd t0, OCTEON_CP2_CRC_IV(a0) 145 sd t1, OCTEON_CP2_CRC_LENGTH(a0) 146 sd t2, OCTEON_CP2_CRC_POLY(a0) 147 /* Skip next instructions if CvmCtl[NODFA_CP2] set */ 148 bbit1 t9, 28, 1f 149 150 /* Save the LLM state */ 151 dmfc2 t0, 0x0402 152 dmfc2 t1, 0x040A 153 sd t0, OCTEON_CP2_LLM_DAT(a0) 154 sd t1, OCTEON_CP2_LLM_DAT+8(a0) 155 1561: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */ 157 158 /* Save the COP2 crypto state */ 159 /* this part is mostly common to both pass 1 and later revisions */ 160 dmfc2 t0, 0x0084 161 dmfc2 t1, 0x0080 162 dmfc2 t2, 0x0081 163 dmfc2 t3, 0x0082 164 sd t0, OCTEON_CP2_3DES_IV(a0) 165 dmfc2 t0, 0x0088 166 sd t1, OCTEON_CP2_3DES_KEY(a0) 167 dmfc2 t1, 0x0111 /* only necessary for pass 1 */ 168 sd t2, OCTEON_CP2_3DES_KEY+8(a0) 169 dmfc2 t2, 0x0102 170 sd t3, OCTEON_CP2_3DES_KEY+16(a0) 171 dmfc2 t3, 0x0103 172 sd t0, OCTEON_CP2_3DES_RESULT(a0) 173 dmfc2 t0, 0x0104 174 sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */ 175 dmfc2 t1, 0x0105 176 sd t2, OCTEON_CP2_AES_IV(a0) 177 dmfc2 t2, 0x0106 178 sd t3, OCTEON_CP2_AES_IV+8(a0) 179 dmfc2 t3, 0x0107 180 sd t0, OCTEON_CP2_AES_KEY(a0) 181 dmfc2 t0, 0x0110 182 sd t1, OCTEON_CP2_AES_KEY+8(a0) 183 dmfc2 t1, 0x0100 184 sd t2, OCTEON_CP2_AES_KEY+16(a0) 185 dmfc2 t2, 0x0101 186 sd t3, OCTEON_CP2_AES_KEY+24(a0) 187 mfc0 t3, $15,0 /* Get the processor ID register */ 188 sd t0, OCTEON_CP2_AES_KEYLEN(a0) 189 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ 190 sd t1, OCTEON_CP2_AES_RESULT(a0) 191 sd t2, OCTEON_CP2_AES_RESULT+8(a0) 192 /* Skip to the Pass1 version of the remainder of the COP2 state */ 193 beq t3, t0, 2f 194 195 /* the non-pass1 state when !CvmCtl[NOCRYPTO] */ 196 dmfc2 t1, 0x0240 197 dmfc2 t2, 0x0241 198 dmfc2 t3, 0x0242 199 dmfc2 t0, 0x0243 200 sd t1, OCTEON_CP2_HSH_DATW(a0) 201 dmfc2 t1, 0x0244 202 sd t2, OCTEON_CP2_HSH_DATW+8(a0) 203 dmfc2 t2, 0x0245 204 sd t3, OCTEON_CP2_HSH_DATW+16(a0) 205 dmfc2 t3, 0x0246 206 sd t0, OCTEON_CP2_HSH_DATW+24(a0) 207 dmfc2 t0, 0x0247 208 sd t1, OCTEON_CP2_HSH_DATW+32(a0) 209 dmfc2 t1, 0x0248 210 sd t2, OCTEON_CP2_HSH_DATW+40(a0) 211 dmfc2 t2, 0x0249 212 sd t3, OCTEON_CP2_HSH_DATW+48(a0) 213 dmfc2 t3, 0x024A 214 sd t0, OCTEON_CP2_HSH_DATW+56(a0) 215 dmfc2 t0, 0x024B 216 sd t1, OCTEON_CP2_HSH_DATW+64(a0) 217 dmfc2 t1, 0x024C 218 sd t2, OCTEON_CP2_HSH_DATW+72(a0) 219 dmfc2 t2, 0x024D 220 sd t3, OCTEON_CP2_HSH_DATW+80(a0) 221 dmfc2 t3, 0x024E 222 sd t0, OCTEON_CP2_HSH_DATW+88(a0) 223 dmfc2 t0, 0x0250 224 sd t1, OCTEON_CP2_HSH_DATW+96(a0) 225 dmfc2 t1, 0x0251 226 sd t2, OCTEON_CP2_HSH_DATW+104(a0) 227 dmfc2 t2, 0x0252 228 sd t3, OCTEON_CP2_HSH_DATW+112(a0) 229 dmfc2 t3, 0x0253 230 sd t0, OCTEON_CP2_HSH_IVW(a0) 231 dmfc2 t0, 0x0254 232 sd t1, OCTEON_CP2_HSH_IVW+8(a0) 233 dmfc2 t1, 0x0255 234 sd t2, OCTEON_CP2_HSH_IVW+16(a0) 235 dmfc2 t2, 0x0256 236 sd t3, OCTEON_CP2_HSH_IVW+24(a0) 237 dmfc2 t3, 0x0257 238 sd t0, OCTEON_CP2_HSH_IVW+32(a0) 239 dmfc2 t0, 0x0258 240 sd t1, OCTEON_CP2_HSH_IVW+40(a0) 241 dmfc2 t1, 0x0259 242 sd t2, OCTEON_CP2_HSH_IVW+48(a0) 243 dmfc2 t2, 0x025E 244 sd t3, OCTEON_CP2_HSH_IVW+56(a0) 245 dmfc2 t3, 0x025A 246 sd t0, OCTEON_CP2_GFM_MULT(a0) 247 dmfc2 t0, 0x025B 248 sd t1, OCTEON_CP2_GFM_MULT+8(a0) 249 sd t2, OCTEON_CP2_GFM_POLY(a0) 250 sd t3, OCTEON_CP2_GFM_RESULT(a0) 251 sd t0, OCTEON_CP2_GFM_RESULT+8(a0) 252 jr ra 253 2542: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */ 255 dmfc2 t3, 0x0040 256 dmfc2 t0, 0x0041 257 dmfc2 t1, 0x0042 258 dmfc2 t2, 0x0043 259 sd t3, OCTEON_CP2_HSH_DATW(a0) 260 dmfc2 t3, 0x0044 261 sd t0, OCTEON_CP2_HSH_DATW+8(a0) 262 dmfc2 t0, 0x0045 263 sd t1, OCTEON_CP2_HSH_DATW+16(a0) 264 dmfc2 t1, 0x0046 265 sd t2, OCTEON_CP2_HSH_DATW+24(a0) 266 dmfc2 t2, 0x0048 267 sd t3, OCTEON_CP2_HSH_DATW+32(a0) 268 dmfc2 t3, 0x0049 269 sd t0, OCTEON_CP2_HSH_DATW+40(a0) 270 dmfc2 t0, 0x004A 271 sd t1, OCTEON_CP2_HSH_DATW+48(a0) 272 sd t2, OCTEON_CP2_HSH_IVW(a0) 273 sd t3, OCTEON_CP2_HSH_IVW+8(a0) 274 sd t0, OCTEON_CP2_HSH_IVW+16(a0) 275 2763: /* pass 1 or CvmCtl[NOCRYPTO] set */ 277 jr ra 278 END(octeon_cop2_save) 279 280/* 281 * void octeon_cop2_restore(struct octeon_cop2_state *a0) 282 */ 283 .align 7 284 .set push 285 .set noreorder 286 LEAF(octeon_cop2_restore) 287 /* First cache line was prefetched before the call */ 288 pref 4, 128(a0) 289 dmfc0 t9, $9,7 /* CvmCtl register. */ 290 291 pref 4, 256(a0) 292 ld t0, OCTEON_CP2_CRC_IV(a0) 293 pref 4, 384(a0) 294 ld t1, OCTEON_CP2_CRC_LENGTH(a0) 295 ld t2, OCTEON_CP2_CRC_POLY(a0) 296 297 /* Restore the COP2 CRC state */ 298 dmtc2 t0, 0x0201 299 dmtc2 t1, 0x1202 300 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */ 301 dmtc2 t2, 0x4200 302 303 /* Restore the LLM state */ 304 ld t0, OCTEON_CP2_LLM_DAT(a0) 305 ld t1, OCTEON_CP2_LLM_DAT+8(a0) 306 dmtc2 t0, 0x0402 307 dmtc2 t1, 0x040A 308 3092: 310 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */ 311 nop 312 313 /* Restore the COP2 crypto state common to pass 1 and pass 2 */ 314 ld t0, OCTEON_CP2_3DES_IV(a0) 315 ld t1, OCTEON_CP2_3DES_KEY(a0) 316 ld t2, OCTEON_CP2_3DES_KEY+8(a0) 317 dmtc2 t0, 0x0084 318 ld t0, OCTEON_CP2_3DES_KEY+16(a0) 319 dmtc2 t1, 0x0080 320 ld t1, OCTEON_CP2_3DES_RESULT(a0) 321 dmtc2 t2, 0x0081 322 ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */ 323 dmtc2 t0, 0x0082 324 ld t0, OCTEON_CP2_AES_IV(a0) 325 dmtc2 t1, 0x0098 326 ld t1, OCTEON_CP2_AES_IV+8(a0) 327 dmtc2 t2, 0x010A /* only really needed for pass 1 */ 328 ld t2, OCTEON_CP2_AES_KEY(a0) 329 dmtc2 t0, 0x0102 330 ld t0, OCTEON_CP2_AES_KEY+8(a0) 331 dmtc2 t1, 0x0103 332 ld t1, OCTEON_CP2_AES_KEY+16(a0) 333 dmtc2 t2, 0x0104 334 ld t2, OCTEON_CP2_AES_KEY+24(a0) 335 dmtc2 t0, 0x0105 336 ld t0, OCTEON_CP2_AES_KEYLEN(a0) 337 dmtc2 t1, 0x0106 338 ld t1, OCTEON_CP2_AES_RESULT(a0) 339 dmtc2 t2, 0x0107 340 ld t2, OCTEON_CP2_AES_RESULT+8(a0) 341 mfc0 t3, $15,0 /* Get the processor ID register */ 342 dmtc2 t0, 0x0110 343 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ 344 dmtc2 t1, 0x0100 345 bne t0, t3, 3f /* Skip the next stuff for non-pass1 */ 346 dmtc2 t2, 0x0101 347 348 /* this code is specific for pass 1 */ 349 ld t0, OCTEON_CP2_HSH_DATW(a0) 350 ld t1, OCTEON_CP2_HSH_DATW+8(a0) 351 ld t2, OCTEON_CP2_HSH_DATW+16(a0) 352 dmtc2 t0, 0x0040 353 ld t0, OCTEON_CP2_HSH_DATW+24(a0) 354 dmtc2 t1, 0x0041 355 ld t1, OCTEON_CP2_HSH_DATW+32(a0) 356 dmtc2 t2, 0x0042 357 ld t2, OCTEON_CP2_HSH_DATW+40(a0) 358 dmtc2 t0, 0x0043 359 ld t0, OCTEON_CP2_HSH_DATW+48(a0) 360 dmtc2 t1, 0x0044 361 ld t1, OCTEON_CP2_HSH_IVW(a0) 362 dmtc2 t2, 0x0045 363 ld t2, OCTEON_CP2_HSH_IVW+8(a0) 364 dmtc2 t0, 0x0046 365 ld t0, OCTEON_CP2_HSH_IVW+16(a0) 366 dmtc2 t1, 0x0048 367 dmtc2 t2, 0x0049 368 b done_restore /* unconditional branch */ 369 dmtc2 t0, 0x004A 370 3713: /* this is post-pass1 code */ 372 ld t2, OCTEON_CP2_HSH_DATW(a0) 373 ld t0, OCTEON_CP2_HSH_DATW+8(a0) 374 ld t1, OCTEON_CP2_HSH_DATW+16(a0) 375 dmtc2 t2, 0x0240 376 ld t2, OCTEON_CP2_HSH_DATW+24(a0) 377 dmtc2 t0, 0x0241 378 ld t0, OCTEON_CP2_HSH_DATW+32(a0) 379 dmtc2 t1, 0x0242 380 ld t1, OCTEON_CP2_HSH_DATW+40(a0) 381 dmtc2 t2, 0x0243 382 ld t2, OCTEON_CP2_HSH_DATW+48(a0) 383 dmtc2 t0, 0x0244 384 ld t0, OCTEON_CP2_HSH_DATW+56(a0) 385 dmtc2 t1, 0x0245 386 ld t1, OCTEON_CP2_HSH_DATW+64(a0) 387 dmtc2 t2, 0x0246 388 ld t2, OCTEON_CP2_HSH_DATW+72(a0) 389 dmtc2 t0, 0x0247 390 ld t0, OCTEON_CP2_HSH_DATW+80(a0) 391 dmtc2 t1, 0x0248 392 ld t1, OCTEON_CP2_HSH_DATW+88(a0) 393 dmtc2 t2, 0x0249 394 ld t2, OCTEON_CP2_HSH_DATW+96(a0) 395 dmtc2 t0, 0x024A 396 ld t0, OCTEON_CP2_HSH_DATW+104(a0) 397 dmtc2 t1, 0x024B 398 ld t1, OCTEON_CP2_HSH_DATW+112(a0) 399 dmtc2 t2, 0x024C 400 ld t2, OCTEON_CP2_HSH_IVW(a0) 401 dmtc2 t0, 0x024D 402 ld t0, OCTEON_CP2_HSH_IVW+8(a0) 403 dmtc2 t1, 0x024E 404 ld t1, OCTEON_CP2_HSH_IVW+16(a0) 405 dmtc2 t2, 0x0250 406 ld t2, OCTEON_CP2_HSH_IVW+24(a0) 407 dmtc2 t0, 0x0251 408 ld t0, OCTEON_CP2_HSH_IVW+32(a0) 409 dmtc2 t1, 0x0252 410 ld t1, OCTEON_CP2_HSH_IVW+40(a0) 411 dmtc2 t2, 0x0253 412 ld t2, OCTEON_CP2_HSH_IVW+48(a0) 413 dmtc2 t0, 0x0254 414 ld t0, OCTEON_CP2_HSH_IVW+56(a0) 415 dmtc2 t1, 0x0255 416 ld t1, OCTEON_CP2_GFM_MULT(a0) 417 dmtc2 t2, 0x0256 418 ld t2, OCTEON_CP2_GFM_MULT+8(a0) 419 dmtc2 t0, 0x0257 420 ld t0, OCTEON_CP2_GFM_POLY(a0) 421 dmtc2 t1, 0x0258 422 ld t1, OCTEON_CP2_GFM_RESULT(a0) 423 dmtc2 t2, 0x0259 424 ld t2, OCTEON_CP2_GFM_RESULT+8(a0) 425 dmtc2 t0, 0x025E 426 dmtc2 t1, 0x025A 427 dmtc2 t2, 0x025B 428 429done_restore: 430 jr ra 431 nop 432 END(octeon_cop2_restore) 433 .set pop 434 435/* 436 * void octeon_mult_save() 437 * sp is assumed to point to a struct pt_regs 438 * 439 * NOTE: This is called in SAVE_SOME in stackframe.h. It can only 440 * safely modify k0 and k1. 441 */ 442 .align 7 443 .set push 444 .set noreorder 445 LEAF(octeon_mult_save) 446 dmfc0 k0, $9,7 /* CvmCtl register. */ 447 bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */ 448 nop 449 450 /* Save the multiplier state */ 451 v3mulu k0, $0, $0 452 v3mulu k1, $0, $0 453 sd k0, PT_MTP(sp) /* PT_MTP has P0 */ 454 v3mulu k0, $0, $0 455 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */ 456 ori k1, $0, 1 457 v3mulu k1, k1, $0 458 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */ 459 v3mulu k0, $0, $0 460 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */ 461 v3mulu k1, $0, $0 462 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */ 463 jr ra 464 sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */ 465 4661: /* Resume here if CvmCtl[NOMUL] */ 467 jr ra 468 END(octeon_mult_save) 469 .set pop 470 471/* 472 * void octeon_mult_restore() 473 * sp is assumed to point to a struct pt_regs 474 * 475 * NOTE: This is called in RESTORE_SOME in stackframe.h. 476 */ 477 .align 7 478 .set push 479 .set noreorder 480 LEAF(octeon_mult_restore) 481 dmfc0 k1, $9,7 /* CvmCtl register. */ 482 ld v0, PT_MPL(sp) /* MPL0 */ 483 ld v1, PT_MPL+8(sp) /* MPL1 */ 484 ld k0, PT_MPL+16(sp) /* MPL2 */ 485 bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */ 486 /* Normally falls through, so no time wasted here */ 487 nop 488 489 /* Restore the multiplier state */ 490 ld k1, PT_MTP+16(sp) /* P2 */ 491 MTM0 v0 /* MPL0 */ 492 ld v0, PT_MTP+8(sp) /* P1 */ 493 MTM1 v1 /* MPL1 */ 494 ld v1, PT_MTP(sp) /* P0 */ 495 MTM2 k0 /* MPL2 */ 496 MTP2 k1 /* P2 */ 497 MTP1 v0 /* P1 */ 498 jr ra 499 MTP0 v1 /* P0 */ 500 5011: /* Resume here if CvmCtl[NOMUL] */ 502 jr ra 503 nop 504 END(octeon_mult_restore) 505 .set pop 506 507