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Searched refs:mcr (Results 1 – 25 of 76) sorted by relevance

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/arch/arm/mm/
Dproc-arm940.S47 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
71 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
102 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
106 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
155 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
160 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
Dproc-arm1020.S89 mcr p15, 0, r0, c1, c0, 0 @ disable caches
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
105 mcr p15, 0, ip, c7, c10, 4 @ drain WB
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
144 mcr p15, 0, ip, c7, c10, 4 @ drain WB
147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
148 mcr p15, 0, ip, c7, c10, 4 @ drain WB
178 mcr p15, 0, ip, c7, c10, 4
[all …]
Dcache-v6.S33 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
34 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
36 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
98 1: mcr p15, 0, r0, c7, c10, 1 @ clean D line
105 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
106 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
108 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
124 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
126 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
133 mcr p15, 0, r0, c7, c10, 4
[all …]
Dproc-arm925.S102 mcr p15, 0, r0, c1, c0, 0 @ disable caches
124 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
125 mcr p15, 0, ip, c7, c10, 4 @ drain WB
127 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
132 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
144 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
146 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
147 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
148 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
170 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
[all …]
Dproc-arm946.S54 mcr p15, 0, r0, c1, c0, 0 @ disable caches
64 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
65 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
70 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
78 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
97 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
101 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
131 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
134 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
Dproc-arm926.S71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
87 mcr p15, 0, ip, c7, c10, 4 @ drain WB
89 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
106 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
111 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
112 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
113 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
136 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
[all …]
Dproc-arm920.S83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB
101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
114 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
140 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
166 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
201 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
202 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dproc-arm922.S85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
142 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
203 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
204 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dproc-arm1020e.S89 mcr p15, 0, r0, c1, c0, 0 @ disable caches
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
105 mcr p15, 0, ip, c7, c10, 4 @ drain WB
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
144 mcr p15, 0, ip, c7, c10, 4 @ drain WB
147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
177 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
216 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
[all …]
Dproc-feroceon.S86 mcr p15, 1, r0, c15, c9, 0 @ clean L2
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
93 mcr p15, 0, r0, c1, c0, 0 @ disable caches
108 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
109 mcr p15, 0, ip, c7, c10, 4 @ drain WB
111 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
116 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
127 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
128 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
153 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
[all …]
Dproc-xsc3.S72 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
100 mcr p15, 0, r0, c1, c0, 0 @ disable caches
119 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
120 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
122 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
125 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
142 mcr p14, 0, r0, c7, c0, 0 @ go to idle
191 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
218 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
223 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
[all …]
Dproc-arm1022.S78 mcr p15, 0, r0, c1, c0, 0 @ disable caches
93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c7, c10, 4 @ drain WB
96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
101 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
135 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
165 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
205 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
Dproc-arm1026.S78 mcr p15, 0, r0, c1, c0, 0 @ disable caches
93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c7, c10, 4 @ drain WB
96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
101 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
199 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
202 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
207 mcr p15, 0, ip, c7, c10, 4 @ drain WB
[all …]
Dproc-sa110.S40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
52 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
56 mcr p15, 0, r0, c1, c0, 0 @ disable caches
71 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
72 mcr p15, 0, ip, c7, c10, 4 @ drain WB
74 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
79 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
96 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
102 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
106 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
[all …]
Dtlb-v6.S38 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
47 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
51 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
56 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
57 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
70 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
85 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
[all …]
Dproc-sa1100.S44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
62 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
66 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
82 mcr p15, 0, ip, c7, c10, 4 @ drain WB
84 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
89 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
114 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
116 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
[all …]
Dproc-v6.S48 mcr p15, 0, r0, c1, c0, 0 @ disable caches
75 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
81 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
103 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
104 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
105 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
106 mcr p15, 0, r1, c13, c0, 1 @ set context ID
156 mcr p15, 0, r0, c1, c0, 1
160 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
[all …]
Dproc-arm740.S45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
46 mcr p15, 0, r0, c7, c0, 0 @ invalidate cache
56 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
59 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
67 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
69 mcr p15, 0, r0, c6, c3 @ disable area 3~7
70 mcr p15, 0, r0, c6, c4
71 mcr p15, 0, r0, c6, c5
72 mcr p15, 0, r0, c6, c6
73 mcr p15, 0, r0, c6, c7
[all …]
Dcache-v4wb.S68 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
85 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
107 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
108 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
153 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
154 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
159 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcr p15, 0, ip, c7, c10, 4 @ drain WB
181 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
185 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
[all …]
Dproc-xscale.S94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
120 mcr p15, 0, r1, c1, c0, 1
134 mcr p15, 0, r0, c1, c0, 0 @ disable caches
152 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
153 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
159 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
161 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
[all …]
Dproc-arm720.S63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
64 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
84 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
85 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
86 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
110 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
112 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
117 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
125 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
127 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
[all …]
/arch/sh/drivers/pci/
Dfixups-rts7751r2d.c20 unsigned long bcr1, mcr; in pci_fixup_pcic() local
33 mcr = ctrl_inl(SH7751_MCR); in pci_fixup_pcic()
34 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; in pci_fixup_pcic()
35 pci_write_reg(mcr, SH4_PCIMCR); in pci_fixup_pcic()
Dfixups-lboxre2.c19 unsigned long bcr1, mcr; in pci_fixup_pcic() local
31 mcr = ctrl_inl(SH7751_MCR); in pci_fixup_pcic()
32 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; in pci_fixup_pcic()
33 pci_write_reg(mcr, SH4_PCIMCR); in pci_fixup_pcic()
/arch/arm/boot/compressed/
Dhead.S28 mcr p14, 0, \ch, c0, c5, 0
34 mcr p14, 0, \ch, c1, c0, 0
337 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
338 mcr p15, 0, r0, c6, c7, 1
341 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
342 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
343 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
346 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
347 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
350 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
[all …]
/arch/arm/mach-msm/
Didle.S27 mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
30 mcr p15, 0, r0, c7, c10, 0 /* flush the cache */
31 mcr p15, 0, r0, c7, c10, 4 /* memory barrier */
32 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
34 mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */

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