| /arch/sh/lib/ |
| D | checksum.S | 51 mov r4, r0
52 tst #3, r0 ! Check alignment.
56 tst #1, r0 ! Check alignment.
63 mov.b @r4+, r0
64 extu.b r0, r0
65 addc r0, r6 ! t=0 from previous tst
66 mov r6, r0
68 shlr16 r0
69 shlr8 r0
70 or r0, r6
[all …]
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| D | ashrsi3.S | 51 ! r0: Result
62 mov #31,r0
63 and r0,r5
64 mova ashrsi3_table,r0
65 mov.b @(r0,r5),r5
67 add r5,r0
68 jmp @r0
72 mov r4,r0
110 rotcl r0
112 subc r0,r0
[all …]
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| D | ashlsi3.S | 51 ! r0: Result
61 mov #31,r0
62 and r0,r5
63 mova ashlsi3_table,r0
64 mov.b @(r0,r5),r5
66 add r5,r0
67 jmp @r0
71 mov r4,r0
109 shll2 r0
111 shll2 r0
[all …]
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| D | lshrsi3.S | 51 ! r0: Result
61 mov #31,r0
62 and r0,r5
63 mova lshrsi3_table,r0
64 mov.b @(r0,r5),r5
66 add r5,r0
67 jmp @r0
71 mov r4,r0
109 shlr2 r0
111 shlr2 r0
[all …]
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| D | udivsi3_i4i.S | 65 mov r4,r0
66 shlr8 r0
72 shlr r0
76 div1 r5,r0
78 div1 r5,r0
79 div1 r5,r0
81 div1 r5,r0
84 mova div_table_ix,r0
86 mov.b @(r0,r5),r1
89 mova div_table_ix,r0
[all …]
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| D | copy_page.S | 33 mov.l .Lpsz,r0
34 add r0,r8
36 1: mov.l @r11+,r0
45 movca.l r0,@r10
46 mov r10,r0
48 mov.l r0,@r10
59 ocbwb @r0
90 mov #11,r0
92 cmp/gt r0,r6 ! r6 (len) > r0 (11)
98 neg r5,r0
[all …]
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| /arch/arm/mach-pxa/ |
| D | standby.S | 23 ldr r0, =PSSR
32 str r1, [r0] @ make sure PSSR_PH/STS are clear
65 mcr p14, 0, r0, c7, c0, 0
70 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
71 bic r0, r0, #PXA3_DDR_HCAL_HCEN
72 str r0, [r1, #PXA3_DDR_HCAL]
73 1: ldr r0, [r1, #PXA3_DDR_HCAL]
74 tst r0, #PXA3_DDR_HCAL_HCEN
77 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
78 orr r0, r0, #PXA3_RCOMP_SWEVAL
[all …]
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| /arch/arm/mm/ |
| D | cache-v6.S | 31 mov r0, #0
33 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
34 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
36 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
97 bic r0, r0, #CACHE_LINE_SIZE - 1
98 1: mcr p15, 0, r0, c7, c10, 1 @ clean D line
99 add r0, r0, #CACHE_LINE_SIZE
100 cmp r0, r1
103 mov r0, #0
105 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
[all …]
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| D | proc-arm946.S | 51 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
52 bic r0, r0, #0x00001000 @ i-cache
53 bic r0, r0, #0x00000004 @ d-cache
54 mcr p15, 0, r0, c1, c0, 0 @ disable caches
71 mov pc, r0
78 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
125 sub r3, r1, r0 @ calculate total size
131 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
132 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
133 add r0, r0, #CACHE_DLINESIZE
[all …]
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| D | proc-arm925.S | 99 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
100 bic r0, r0, #0x1000 @ ...i............
101 bic r0, r0, #0x000e @ ............wca.
102 mcr p15, 0, r0, c1, c0, 0 @ disable caches
133 mov pc, r0
142 mov r0, #0
144 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
147 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
195 sub r3, r1, r0 @ calculate total size
200 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
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| D | proc-arm926.S | 68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 bic r0, r0, #0x1000 @ ...i............
70 bic r0, r0, #0x000e @ ............wca.
71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
95 mov pc, r0
104 mov r0, #0
106 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
112 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
158 sub r3, r1, r0 @ calculate total size
163 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
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| D | proc-arm740.S | 42 mrc p15, 0, r0, c1, c0, 0
43 bic r0, r0, #0x3f000000 @ bank/f/lock/s
44 bic r0, r0, #0x0000000c @ w-buffer/cache
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
46 mcr p15, 0, r0, c7, c0, 0 @ invalidate cache
60 mov pc, r0
66 mov r0, #0
67 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
69 mcr p15, 0, r0, c6, c3 @ disable area 3~7
70 mcr p15, 0, r0, c6, c4
[all …]
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| D | proc-arm920.S | 80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0, #0x1000 @ ...i............
82 bic r0, r0, #0x000e @ ............wca.
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
107 mov pc, r0
114 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
162 sub r3, r1, r0 @ calculate total size
166 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
168 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
169 add r0, r0, #CACHE_DLINESIZE
[all …]
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| D | proc-arm922.S | 82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mov pc, r0
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
164 sub r3, r1, r0 @ calculate total size
168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
171 add r0, r0, #CACHE_DLINESIZE
[all …]
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| D | proc-feroceon.S | 60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
63 tst r0, #(1 << 16) @ get way
64 mov r0, r0, lsr #18 @ get cache size order
66 and r0, r0, #0xf
68 mov r2, r2, lsl r0 @ actual cache size
85 mov r0, #0
86 mcr p15, 1, r0, c15, c9, 0 @ clean L2
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
90 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
91 bic r0, r0, #0x1000 @ ...i............
[all …]
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| /arch/arm/lib/ |
| D | delay.S | 26 mul r0, r2, r0
27 ENTRY(__const_udelay) @ 0 <= r0 <= 0x7fffff06
30 mov r0, r0, lsr #14 @ max = 0x0001ffff
32 mul r0, r2, r0 @ max = 2^32-1
33 movs r0, r0, lsr #6
44 subs r0, r0, #1
47 subs r0, r0, #1
49 subs r0, r0, #1
51 subs r0, r0, #1
53 subs r0, r0, #1
[all …]
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| /arch/m32r/lib/ |
| D | checksum.S | 55 ; r0: unsigned char *buff
60 and3 r7, r0, #1 ; Check alignment.
63 ldub r4, @r0 || addi r0, #1
65 cmp r0, r0 || addi r1, #-1
70 and3 r4, r0, #2 ; Check alignment.
73 cmp r0, r0 || addi r1, #-2
79 lduh r4, @r0 || ldi r3, #0
80 addx r2, r4 || addi r0, #2
85 cmp r0, r0 ; clear c-bit
90 1: ld r3, @r0+
[all …]
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| /arch/sh/kernel/cpu/sh5/ |
| D | switchto.S | 45 movi FRAME_SIZE, r0
46 sub.l r15, r0, r15
56 addi.l r1, 24, r0 ! base of pt_regs.regs
57 addi.l r0, (63*8), r8 ! base of pt_regs.trregs
66 st.q r0, ( 9*8), r9
67 st.q r0, (10*8), r10
68 st.q r0, (11*8), r11
69 st.q r0, (12*8), r12
70 st.q r0, (13*8), r13
71 st.q r0, (14*8), r14 ! for unwind, want to look as though we took a trap at
[all …]
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| /arch/sh/kernel/vsyscall/ |
| D | vsyscall-sigreturn.S | 11 or r0, r0
12 or r0, r0
13 or r0, r0
14 or r0, r0
15 or r0, r0
28 or r0, r0
29 or r0, r0
30 or r0, r0
31 or r0, r0
32 or r0, r0
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| /arch/powerpc/kernel/ |
| D | cpu_setup_ppc970.S | 21 mfmsr r0
22 rldicl. r0,r0,4,63
29 li r0,0
31 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
32 rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
38 rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
45 mfspr r0,SPRN_HID1
48 or r0,r0,r3
49 mtspr SPRN_HID1,r0
50 mtspr SPRN_HID1,r0
[all …]
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| /arch/m32r/mm/ |
| D | page.S | 27 ld r3, @r0 /* cache line allocate */
34 st r4, @r0
35 st r5, @+r0
36 st r6, @+r0
37 st r7, @+r0
39 addi r0, #4
43 ld r3, @r0 /* cache line allocate */
47 st r4, @r0
48 st r5, @+r0
49 st r6, @+r0
[all …]
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| /arch/s390/kernel/vdso32/ |
| D | clock_gettime.S | 36 lm %r0,%r1,24(%r15)
37 s %r0,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
40 ahi %r0,-1
41 2: mhi %r0,1000 /* cyc2ns(clock,cycle_delta) */
42 lr %r2,%r0
43 lhi %r0,1000
45 mr %r0,%r0
47 ahi %r0,1000
48 3: alr %r0,%r2
49 srdl %r0,12
[all …]
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| /arch/powerpc/lib/ |
| D | checksum_32.S | 27 lwz r0,0(r3)
30 addc r0,r0,r5
34 adde r0,r0,r4
36 addze r0,r0 /* add in final carry */
37 rlwinm r3,r0,16,0,31 /* fold two halves together */
38 add r3,r0,r3
49 addc r0,r3,r4 /* add 4 32-bit words together */
50 adde r0,r0,r5
51 adde r0,r0,r7
52 addze r0,r0 /* add in final carry */
[all …]
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| /arch/powerpc/mm/ |
| D | hash_low_32.S | 56 lis r0,0x0fff
64 stwcx. r0,0,r8
69 lis r0,KERNELBASE@h /* check if kernel address */
70 cmplw 0,r4,r0
102 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
103 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
125 or r5,r0,r6 /* set accessed/dirty bits */
139 mfctr r0
140 stw r0,_CTR(r11)
146 li r0,0
[all …]
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| /arch/cris/arch-v32/kernel/ |
| D | kgdb_asm.S | 326 move.d [$acr], $r0
327 move $r0, $s0
329 move.d [$acr], $r0
330 move $r0, $s1
332 move.d [$acr], $r0
333 move $r0, $s2
335 move.d [$acr], $r0
336 move $r0, $s3
338 move.d [$acr], $r0
339 move $r0, $s4
[all …]
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