| /arch/arm/mach-pnx4008/ |
| D | clock.c | 434 .set_rate = &ck_13MHz_set_rate,
459 .set_rate = &pll1_set_rate,
473 .set_rate = &pll160_set_rate,
488 .set_rate = &pll160_set_rate,
502 .set_rate = &pll160_set_rate,
516 .set_rate = &hclk_set_rate,
528 .set_rate = &per_clk_set_rate,
540 .set_rate = &on_off_inv_set_rate,
551 .set_rate = &on_off_set_rate,
562 .set_rate = &on_off_set_rate,
[all …]
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| D | clock.h | 33 int (*set_rate) (struct clk *, u32); member
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| /arch/arm/mach-mx1/ |
| D | clock.c | 87 return clk->parent->set_rate(clk->parent, rate); in _clk_parent_set_rate()
271 .set_rate = hclk_set_rate,
313 .set_rate = clk48m_set_rate,
434 .set_rate = perclk1_set_rate,
441 .set_rate = perclk2_set_rate,
448 .set_rate = perclk3_set_rate,
474 if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) { in clko_set_parent()
475 clk->set_rate = _clk_parent_set_rate; in clko_set_parent()
478 clk->set_rate = NULL; in clko_set_parent()
494 .set_rate = _clk_parent_set_rate,
[all …]
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| /arch/arm/plat-s3c/ |
| D | clock.c | 181 WARN_ON(clk->set_rate == NULL); in clk_set_rate()
183 if (clk->set_rate == NULL) in clk_set_rate()
187 ret = (clk->set_rate)(clk, rate); in clk_set_rate()
254 .set_rate = clk_default_setrate,
270 .set_rate = clk_default_setrate,
279 .set_rate = clk_default_setrate,
288 .set_rate = clk_default_setrate,
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| D | pwm-clock.c | 138 .set_rate = clk_pwm_scaler_set_rate,
145 .set_rate = clk_pwm_scaler_set_rate,
265 .set_rate = clk_pwm_tdiv_set_rate,
274 .set_rate = clk_pwm_tdiv_set_rate,
283 .set_rate = clk_pwm_tdiv_set_rate,
292 .set_rate = clk_pwm_tdiv_set_rate,
301 .set_rate = clk_pwm_tdiv_set_rate,
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| /arch/arm/plat-s3c64xx/ |
| D | s3c6400-clock.c | 308 .set_rate = s3c64xx_setrate_clksrc,
325 .set_rate = s3c64xx_setrate_clksrc,
343 .set_rate = s3c64xx_setrate_clksrc,
362 .set_rate = s3c64xx_setrate_clksrc,
380 .set_rate = s3c64xx_setrate_clksrc,
400 .set_rate = s3c64xx_setrate_clksrc,
418 .set_rate = s3c64xx_setrate_clksrc,
464 .set_rate = s3c64xx_setrate_clksrc,
495 .set_rate = s3c64xx_setrate_clksrc,
513 .set_rate = s3c64xx_setrate_clksrc,
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| /arch/avr32/mach-at32ap/ |
| D | clock.c | 123 if (!clk->set_rate) in clk_round_rate()
127 actual_rate = clk->set_rate(clk, rate, 0); in clk_round_rate()
139 if (!clk->set_rate) in clk_set_rate()
143 ret = clk->set_rate(clk, rate, 1); in clk_set_rate()
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| D | clock.h | 27 long (*set_rate)(struct clk *clk, unsigned long rate, member
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| /arch/arm/mach-omap1/ |
| D | clock.h | 194 .set_rate = &omap1_set_sossi_rate,
331 .set_rate = &omap1_clk_set_rate_dsp_domain,
542 .set_rate = &omap1_set_uart_rate,
574 .set_rate = &omap1_set_uart_rate,
590 .set_rate = &omap1_set_uart_rate,
677 .set_rate = &omap1_set_ext_clk_rate,
699 .set_rate = &omap1_set_ext_clk_rate,
740 .set_rate = &omap1_select_table_rate,
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| /arch/sh/kernel/cpu/sh4/ |
| D | clock-sh4-202.c | 85 if (clk->ops->set_rate(clk, clk->parent->rate / in shoc_clk_init()
138 .set_rate = shoc_clk_set_rate,
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| /arch/arm/plat-mxc/include/mach/ |
| D | clock.h | 49 int (*set_rate) (struct clk *, unsigned long); member
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| /arch/arm/plat-s3c24xx/ |
| D | clock-dclk.c | 170 .set_rate = s3c24xx_set_dclk_rate,
180 .set_rate = s3c24xx_set_dclk_rate,
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| /arch/arm/mach-s3c2443/ |
| D | clock.c | 345 .set_rate = s3c2443_setrate_uart,
388 .set_rate = s3c2443_setrate_hsspi,
430 .set_rate = s3c2443_setrate_usbhost,
472 .set_rate = s3c2443_setrate_hsmmc_div,
547 .set_rate = s3c2443_setrate_i2s_eplldiv,
622 .set_rate = s3c2443_setrate_cam,
664 .set_rate = s3c2443_setrate_display,
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| /arch/arm/mach-omap2/ |
| D | clock24xx.h | 693 .set_rate = &omap2_reprogram_dpllcore,
798 .set_rate = &omap2_clksel_set_rate
831 .set_rate = &omap2_clksel_set_rate
902 .set_rate = &omap2_clksel_set_rate
930 .set_rate = &omap2_clksel_set_rate
947 .set_rate = &omap2_clksel_set_rate
966 .set_rate = &omap2_clksel_set_rate
1017 .set_rate = &omap2_clksel_set_rate
1060 .set_rate = &omap2_clksel_set_rate
1087 .set_rate = &omap2_clksel_set_rate
[all …]
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| /arch/arm/plat-s3c/include/plat/ |
| D | clock.h | 25 int (*set_rate)(struct clk *c, unsigned long rate); member
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| /arch/sh/include/asm/ |
| D | clock.h | 17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); member
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| /arch/arm/mach-s3c2442/ |
| D | clock.c | 112 .set_rate = s3c2442_camif_upll_setrate,
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| /arch/arm/mach-s3c2440/ |
| D | clock.c | 101 .set_rate = s3c2440_camif_upll_setrate,
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| /arch/arm/mach-mx2/ |
| D | clock_imx27.c | 448 return clk->parent->set_rate(clk->parent, rate); in _clk_parent_set_rate()
610 .set_rate = _clk_cpu_set_rate,
694 .set_rate = _clk_perclkx_set_rate,
705 .set_rate = _clk_perclkx_set_rate,
1041 .set_rate = _clk_parent_set_rate,
1066 .set_rate = _clk_parent_set_rate,
1441 .set_rate = _clk_clko_set_rate,
1565 cpu_clk.set_rate = NULL; in probe_mxc_clocks()
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| /arch/arm/mach-s3c2412/ |
| D | clock.c | 203 .set_rate = s3c2412_setrate_usbsrc,
341 .set_rate = s3c2412_setrate_uart,
392 .set_rate = s3c2412_setrate_i2s,
442 .set_rate = s3c2412_setrate_cam,
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| /arch/arm/plat-mxc/ |
| D | clock.c | 218 if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) in clk_set_rate()
222 ret = clk->set_rate(clk, rate); in clk_set_rate()
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| /arch/arm/mach-mx3/ |
| D | clock.c | 492 .set_rate = _clk_pll_set_rate,
505 .set_rate = _clk_pll_set_rate,
514 .set_rate = _clk_pll_set_rate,
682 .set_rate = _clk_csi_set_rate,
811 .set_rate = _clk_firi_set_rate,
1036 .set_rate = _clk_cko1_set_rate,
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| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7722.c | 193 .set_rate = master_clk_setrate,
407 .set_rate = sh7722_frqcr_set_rate,
464 .set_rate = sh7722_siu_set_rate,
509 .set_rate = sh7722_video_set_rate,
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| /arch/sh/kernel/cpu/ |
| D | clock.c | 212 if (likely(clk->ops && clk->ops->set_rate)) { in clk_set_rate_ex()
216 ret = clk->ops->set_rate(clk, rate, algo_id); in clk_set_rate_ex()
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| /arch/arm/plat-omap/include/mach/ |
| D | clock.h | 72 int (*set_rate)(struct clk *, unsigned long); member
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